Commit 743a6d92 authored by Tony Lindgren's avatar Tony Lindgren

Merge tag 'omap-devel-b-for-3.5' of...

Merge tag 'omap-devel-b-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-prcm

Some OMAP PRCM updates for 3.5.  Includes some clock, clockdomain,
powerdomain, PRM, and CM changes.
parents 1df82cd6 0135f6a0
...@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk) ...@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
clk->ops->disable(clk); clk->ops->disable(clk);
} }
if (clk->clkdm != NULL) if (clk->clkdm != NULL)
pwrdm_clkdm_state_switch(clk->clkdm); pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
} }
#endif #endif
......
/* /*
* OMAP3 clock data * OMAP3 clock data
* *
* Copyright (C) 2007-2010 Texas Instruments, Inc. * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation * Copyright (C) 2007-2011 Nokia Corporation
* *
* Written by Paul Walmsley * Written by Paul Walmsley
...@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = { ...@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = {
.name = "hdq_fck", .name = "hdq_fck",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt_wait,
.parent = &core_12m_fck, .parent = &core_12m_fck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT, .enable_bit = OMAP3430_EN_HDQ_SHIFT,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = { ...@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
...@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = { ...@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
...@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void) ...@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void)
struct omap_clk *c; struct omap_clk *c;
u32 cpu_clkflg = 0; u32 cpu_clkflg = 0;
/* if (cpu_is_omap3517()) {
* 3505 must be tested before 3517, since 3517 returns true
* for both AM3517 chips and AM3517 family chips, which
* includes 3505. Unfortunately there's no obvious family
* test for 3517/3505 :-(
*/
if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_3505;
} else if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_34XX; cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_3505; cpu_clkflg = CK_AM35XX;
} else if (cpu_is_omap3630()) { } else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX; cpu_clkflg = CK_36XX;
......
...@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
......
...@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm) ...@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
spin_lock_irqsave(&clkdm->lock, flags); spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_allow_idle(clkdm); arch_clkdm->clkdm_allow_idle(clkdm);
pwrdm_clkdm_state_switch(clkdm); pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags); spin_unlock_irqrestore(&clkdm->lock, flags);
} }
...@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) ...@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
spin_lock_irqsave(&clkdm->lock, flags); spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_enable(clkdm); arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr); pwrdm_state_switch(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags); spin_unlock_irqrestore(&clkdm->lock, flags);
pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name); pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
...@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) ...@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
spin_lock_irqsave(&clkdm->lock, flags); spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_disable(clkdm); arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_clkdm_state_switch(clkdm); pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags); spin_unlock_irqrestore(&clkdm->lock, flags);
pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name); pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
......
...@@ -53,9 +53,9 @@ ...@@ -53,9 +53,9 @@
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
*/ */
static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
{ .clkdm_name = "iva2_clkdm", }, { .clkdm_name = "iva2_clkdm" },
{ .clkdm_name = "mpu_clkdm", }, { .clkdm_name = "mpu_clkdm" },
{ .clkdm_name = "wkup_clkdm", }, { .clkdm_name = "wkup_clkdm" },
{ NULL }, { NULL },
}; };
......
...@@ -79,7 +79,7 @@ ...@@ -79,7 +79,7 @@
/* CM_CLKSEL1_PLL_IVA2 */ /* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19
#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
...@@ -124,7 +124,7 @@ ...@@ -124,7 +124,7 @@
/* CM_CLKSEL1_PLL_MPU */ /* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT 19 #define OMAP3430_MPU_CLK_SRC_SHIFT 19
#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0
......
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include "prcm44xx.h" #include "prcm44xx.h"
#include "prm44xx.h" #include "prm44xx.h"
#include "prcm_mpu44xx.h" #include "prcm_mpu44xx.h"
#include "prcm-common.h"
/* /*
* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
...@@ -49,14 +50,21 @@ ...@@ -49,14 +50,21 @@
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3 #define CLKCTRL_IDLEST_DISABLED 0x3
static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
[OMAP4430_INVALID_PRCM_PARTITION] = 0,
[OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, /**
[OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, * omap_cm_base_init - Populates the cm partitions
[OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, *
[OMAP4430_SCRM_PARTITION] = 0, * Populates the base addresses of the _cm_bases
[OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, * array used for read/write of cm module registers.
}; */
void omap_cm_base_init(void)
{
_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
_cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
_cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
}
/* Private functions */ /* Private functions */
...@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) ...@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]); !_cm_bases[part]);
return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); return __raw_readl(_cm_bases[part] + inst + idx);
} }
/* Write into a register in a CM instance */ /* Write into a register in a CM instance */
...@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) ...@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]); !_cm_bases[part]);
__raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); __raw_writel(val, _cm_bases[part] + inst + idx);
} }
/* Read-modify-write a register in CM1. Caller must lock */ /* Read-modify-write a register in CM1. Caller must lock */
......
...@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = { ...@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = {
.prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
.cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
.prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
}; };
void __init omap2_set_globals_443x(void) void __init omap2_set_globals_443x(void)
......
...@@ -111,6 +111,7 @@ struct omap_globals { ...@@ -111,6 +111,7 @@ struct omap_globals {
void __iomem *prm; /* Power and Reset Management */ void __iomem *prm; /* Power and Reset Management */
void __iomem *cm; /* Clock Management */ void __iomem *cm; /* Clock Management */
void __iomem *cm2; void __iomem *cm2;
void __iomem *prcm_mpu;
}; };
void omap2_set_globals_242x(void); void omap2_set_globals_242x(void);
......
...@@ -142,6 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) ...@@ -142,6 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
ai = omap3_dpll_autoidle_read(clk); ai = omap3_dpll_autoidle_read(clk);
if (ai)
omap3_dpll_deny_idle(clk); omap3_dpll_deny_idle(clk);
_omap3_dpll_write_clken(clk, DPLL_LOCKED); _omap3_dpll_write_clken(clk, DPLL_LOCKED);
...@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) ...@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
if (ai) if (ai)
omap3_dpll_allow_idle(clk); omap3_dpll_allow_idle(clk);
else
omap3_dpll_deny_idle(clk);
return r; return r;
} }
...@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) ...@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
if (ai) if (ai)
omap3_dpll_allow_idle(clk); omap3_dpll_allow_idle(clk);
else
omap3_dpll_deny_idle(clk);
return 0; return 0;
} }
...@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
dd = clk->dpll_data; dd = clk->dpll_data;
if (!dd->autoidle_reg)
return -EINVAL;
v = __raw_readl(dd->autoidle_reg); v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask; v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask); v >>= __ffs(dd->autoidle_mask);
...@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk) ...@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
dd = clk->dpll_data; dd = clk->dpll_data;
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
clk->name);
return;
}
/* /*
* REVISIT: CORE DPLL can optionally enter low-power bypass * REVISIT: CORE DPLL can optionally enter low-power bypass
* by writing 0x5 instead of 0x1. Add some mechanism to * by writing 0x5 instead of 0x1. Add some mechanism to
...@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk) ...@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
v &= ~dd->autoidle_mask; v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg); __raw_writel(v, dd->autoidle_reg);
} }
/** /**
...@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk) ...@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
dd = clk->dpll_data; dd = clk->dpll_data;
if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
clk->name);
return;
}
v = __raw_readl(dd->autoidle_reg); v = __raw_readl(dd->autoidle_reg);
v &= ~dd->autoidle_mask; v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
......
...@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm) ...@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
return ret; return ret;
} }
int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
{
if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
pwrdm_wait_transition(clkdm->pwrdm.ptr);
return pwrdm_state_switch(clkdm->pwrdm.ptr);
}
return -EINVAL;
}
int pwrdm_pre_transition(void) int pwrdm_pre_transition(void)
{ {
pwrdm_for_each(_pwrdm_pre_transition_cb, NULL); pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
......
...@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); ...@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm); int pwrdm_wait_transition(struct powerdomain *pwrdm);
int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_state_switch(struct powerdomain *pwrdm);
int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
int pwrdm_pre_transition(void); int pwrdm_pre_transition(void);
int pwrdm_post_transition(void); int pwrdm_post_transition(void);
int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
......
...@@ -177,6 +177,8 @@ ...@@ -177,6 +177,8 @@
/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
#define OMAP24XX_ST_GPIOS_SHIFT 2 #define OMAP24XX_ST_GPIOS_SHIFT 2
#define OMAP24XX_ST_GPIOS_MASK (1 << 2) #define OMAP24XX_ST_GPIOS_MASK (1 << 2)
#define OMAP24XX_ST_32KSYNC_SHIFT 1
#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
#define OMAP24XX_ST_GPT1_SHIFT 0 #define OMAP24XX_ST_GPT1_SHIFT 0
#define OMAP24XX_ST_GPT1_MASK (1 << 0) #define OMAP24XX_ST_GPT1_MASK (1 << 0)
...@@ -307,6 +309,8 @@ ...@@ -307,6 +309,8 @@
#define OMAP3430_ST_SR1_MASK (1 << 6) #define OMAP3430_ST_SR1_MASK (1 << 6)
#define OMAP3430_ST_GPIO1_SHIFT 3 #define OMAP3430_ST_GPIO1_SHIFT 3
#define OMAP3430_ST_GPIO1_MASK (1 << 3) #define OMAP3430_ST_GPIO1_MASK (1 << 3)
#define OMAP3430_ST_32KSYNC_SHIFT 2
#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
#define OMAP3430_ST_GPT12_SHIFT 1 #define OMAP3430_ST_GPT12_SHIFT 1
#define OMAP3430_ST_GPT12_MASK (1 << 1) #define OMAP3430_ST_GPT12_MASK (1 << 1)
#define OMAP3430_ST_GPT1_SHIFT 0 #define OMAP3430_ST_GPT1_SHIFT 0
...@@ -410,6 +414,19 @@ ...@@ -410,6 +414,19 @@
extern void __iomem *prm_base; extern void __iomem *prm_base;
extern void __iomem *cm_base; extern void __iomem *cm_base;
extern void __iomem *cm2_base; extern void __iomem *cm2_base;
extern void __iomem *prcm_mpu_base;
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
extern void omap_prm_base_init(void);
extern void omap_cm_base_init(void);
#else
static inline void omap_prm_base_init(void)
{
}
static inline void omap_cm_base_init(void)
{
}
#endif
/** /**
* struct omap_prcm_irq - describes a PRCM interrupt bit * struct omap_prcm_irq - describes a PRCM interrupt bit
......
...@@ -42,6 +42,7 @@ ...@@ -42,6 +42,7 @@
void __iomem *prm_base; void __iomem *prm_base;
void __iomem *cm_base; void __iomem *cm_base;
void __iomem *cm2_base; void __iomem *cm2_base;
void __iomem *prcm_mpu_base;
#define MAX_MODULE_ENABLE_WAIT 100000 #define MAX_MODULE_ENABLE_WAIT 100000
...@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) ...@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
cm_base = omap2_globals->cm; cm_base = omap2_globals->cm;
if (omap2_globals->cm2) if (omap2_globals->cm2)
cm2_base = omap2_globals->cm2; cm2_base = omap2_globals->cm2;
if (omap2_globals->prcm_mpu)
prcm_mpu_base = omap2_globals->prcm_mpu;
if (cpu_is_omap44xx()) {
omap_prm_base_init();
omap_cm_base_init();
}
} }
...@@ -18,20 +18,26 @@ ...@@ -18,20 +18,26 @@
#include "iomap.h" #include "iomap.h"
#include "common.h" #include "common.h"
#include "prcm-common.h"
#include "prm44xx.h" #include "prm44xx.h"
#include "prminst44xx.h" #include "prminst44xx.h"
#include "prm-regbits-44xx.h" #include "prm-regbits-44xx.h"
#include "prcm44xx.h" #include "prcm44xx.h"
#include "prcm_mpu44xx.h" #include "prcm_mpu44xx.h"
static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
[OMAP4430_INVALID_PRCM_PARTITION] = 0,
[OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, /**
[OMAP4430_CM1_PARTITION] = 0, * omap_prm_base_init - Populates the prm partitions
[OMAP4430_CM2_PARTITION] = 0, *
[OMAP4430_SCRM_PARTITION] = 0, * Populates the base addresses of the _prm_bases
[OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, * array used for read/write of prm module registers.
}; */
void omap_prm_base_init(void)
{
_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
}
/* Read a register in a PRM instance */ /* Read a register in a PRM instance */
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
...@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) ...@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]); !_prm_bases[part]);
return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + return __raw_readl(_prm_bases[part] + inst + idx);
idx));
} }
/* Write into a register in a PRM instance */ /* Write into a register in a PRM instance */
...@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) ...@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]); !_prm_bases[part]);
__raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx)); __raw_writel(val, _prm_bases[part] + inst + idx);
} }
/* Read-modify-write a register in PRM. Caller must lock */ /* Read-modify-write a register in PRM. Caller must lock */
......
...@@ -178,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, ...@@ -178,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
if (IS_ERR(timer->fclk)) if (IS_ERR(timer->fclk))
return -ENODEV; return -ENODEV;
sprintf(name, "gpt%d_ick", gptimer_id);
timer->iclk = clk_get(NULL, name);
if (IS_ERR(timer->iclk)) {
clk_put(timer->fclk);
return -ENODEV;
}
omap_hwmod_enable(oh); omap_hwmod_enable(oh);
sys_timer_reserved |= (1 << (gptimer_id - 1)); sys_timer_reserved |= (1 << (gptimer_id - 1));
......
...@@ -34,8 +34,7 @@ struct omap_clk { ...@@ -34,8 +34,7 @@ struct omap_clk {
#define CK_243X (1 << 5) /* 243x, 253x */ #define CK_243X (1 << 5) /* 243x, 253x */
#define CK_3430ES1 (1 << 6) /* 34xxES1 only */ #define CK_3430ES1 (1 << 6) /* 34xxES1 only */
#define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */ #define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */
#define CK_3505 (1 << 8) #define CK_AM35XX (1 << 9) /* Sitara AM35xx */
#define CK_3517 (1 << 9)
#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 11) #define CK_443X (1 << 11)
#define CK_TI816X (1 << 12) #define CK_TI816X (1 << 12)
...@@ -44,7 +43,6 @@ struct omap_clk { ...@@ -44,7 +43,6 @@ struct omap_clk {
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
......
...@@ -259,7 +259,7 @@ struct omap_dm_timer { ...@@ -259,7 +259,7 @@ struct omap_dm_timer {
unsigned long phys_base; unsigned long phys_base;
int id; int id;
int irq; int irq;
struct clk *iclk, *fclk; struct clk *fclk;
void __iomem *io_base; void __iomem *io_base;
void __iomem *sys_stat; /* TISTAT timer status */ void __iomem *sys_stat; /* TISTAT timer status */
......
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