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Commit 7458b82f authored by Christian Marangi's avatar Christian Marangi Committed by Bjorn Andersson
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clk: qcom: lcc-ipq806x: convert to parent data 

Convert lcc-ipq806x driver to parent_data API.
Change parent_name for pll4 to pxo_board to prepare the future to
eventually drop the double pxo board clk.
Signed-off-by: default avatarChristian Marangi <ansuelsmth@gmail.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220724182329.9891-3-ansuelsmth@gmail.com
parent ce6bb04c
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Showing with 38 additions and 31 deletions
drivers/clk/qcom/lcc-ipq806x.c
View file @ 7458b82f
...@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { ...@@ -34,7 +34,9 @@ static struct clk_pll pll4 = {
.status_bit = 16, .status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "pll4", .name = "pll4",
.parent_names = (const char *[]){ "pxo" }, .parent_data = &(const struct clk_parent_data) {
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_pll_ops, .ops = &clk_pll_ops,
}, },
...@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { ...@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PLL4, 2 } { P_PLL4, 2 }
}; };
static const char * const lcc_pxo_pll4[] = { static const struct clk_parent_data lcc_pxo_pll4[] = {
"pxo", { .fw_name = "pxo", .name = "pxo_board" },
"pll4_vote", { .fw_name = "pll4_vote", .name = "pll4_vote" },
}; };
static struct freq_tbl clk_tbl_aif_mi2s[] = { static struct freq_tbl clk_tbl_aif_mi2s[] = {
...@@ -131,7 +133,7 @@ static struct clk_rcg mi2s_osr_src = { ...@@ -131,7 +133,7 @@ static struct clk_rcg mi2s_osr_src = {
.enable_mask = BIT(9), .enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mi2s_osr_src", .name = "mi2s_osr_src",
.parent_names = lcc_pxo_pll4, .parent_data = lcc_pxo_pll4,
.num_parents = 2, .num_parents = 2,
.ops = &clk_rcg_ops, .ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE, .flags = CLK_SET_RATE_GATE,
...@@ -139,10 +141,6 @@ static struct clk_rcg mi2s_osr_src = { ...@@ -139,10 +141,6 @@ static struct clk_rcg mi2s_osr_src = {
}, },
}; };
static const char * const lcc_mi2s_parents[] = {
"mi2s_osr_src",
};
static struct clk_branch mi2s_osr_clk = { static struct clk_branch mi2s_osr_clk = {
.halt_reg = 0x50, .halt_reg = 0x50,
.halt_bit = 1, .halt_bit = 1,
...@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = { ...@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = {
.enable_mask = BIT(17), .enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mi2s_osr_clk", .name = "mi2s_osr_clk",
.parent_names = lcc_mi2s_parents, .parent_hws = (const struct clk_hw*[]) {
&mi2s_osr_src.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch_ops, .ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_clk = { ...@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_clk = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mi2s_div_clk", .name = "mi2s_div_clk",
.parent_names = lcc_mi2s_parents, .parent_hws = (const struct clk_hw*[]) {
&mi2s_osr_src.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_regmap_div_ops, .ops = &clk_regmap_div_ops,
}, },
...@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_clk = { ...@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_clk = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mi2s_bit_div_clk", .name = "mi2s_bit_div_clk",
.parent_names = (const char *[]){ "mi2s_div_clk" }, .parent_hws = (const struct clk_hw*[]) {
&mi2s_div_clk.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch_ops, .ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_clk = { ...@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_clk = {
}, },
}; };
static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
{ .hw = &mi2s_bit_div_clk.clkr.hw, },
{ .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" },
};
static struct clk_regmap_mux mi2s_bit_clk = { static struct clk_regmap_mux mi2s_bit_clk = {
.reg = 0x48, .reg = 0x48,
...@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { ...@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_clk = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mi2s_bit_clk", .name = "mi2s_bit_clk",
.parent_names = (const char *[]){ .parent_data = lcc_mi2s_bit_div_codec_clk,
"mi2s_bit_div_clk", .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
"mi2s_codec_clk",
},
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -245,7 +250,7 @@ static struct clk_rcg pcm_src = { ...@@ -245,7 +250,7 @@ static struct clk_rcg pcm_src = {
.enable_mask = BIT(9), .enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcm_src", .name = "pcm_src",
.parent_names = lcc_pxo_pll4, .parent_data = lcc_pxo_pll4,
.num_parents = 2, .num_parents = 2,
.ops = &clk_rcg_ops, .ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE, .flags = CLK_SET_RATE_GATE,
...@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { ...@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = {
.enable_mask = BIT(11), .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcm_clk_out", .name = "pcm_clk_out",
.parent_names = (const char *[]){ "pcm_src" }, .parent_hws = (const struct clk_hw*[]) {
&pcm_src.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch_ops, .ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { ...@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = {
}, },
}; };
static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
{ .hw = &pcm_clk_out.clkr.hw, },
{ .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
};
static struct clk_regmap_mux pcm_clk = { static struct clk_regmap_mux pcm_clk = {
.reg = 0x54, .reg = 0x54,
.shift = 10, .shift = 10,
...@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { ...@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "pcm_clk", .name = "pcm_clk",
.parent_names = (const char *[]){ .parent_data = lcc_pcm_clk_out_codec_clk,
"pcm_clk_out", .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
"pcm_codec_clk",
},
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -325,7 +334,7 @@ static struct clk_rcg spdif_src = { ...@@ -325,7 +334,7 @@ static struct clk_rcg spdif_src = {
.enable_mask = BIT(9), .enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "spdif_src", .name = "spdif_src",
.parent_names = lcc_pxo_pll4, .parent_data = lcc_pxo_pll4,
.num_parents = 2, .num_parents = 2,
.ops = &clk_rcg_ops, .ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE, .flags = CLK_SET_RATE_GATE,
...@@ -333,10 +342,6 @@ static struct clk_rcg spdif_src = { ...@@ -333,10 +342,6 @@ static struct clk_rcg spdif_src = {
}, },
}; };
static const char * const lcc_spdif_parents[] = {
"spdif_src",
};
static struct clk_branch spdif_clk = { static struct clk_branch spdif_clk = {
.halt_reg = 0xd4, .halt_reg = 0xd4,
.halt_bit = 1, .halt_bit = 1,
...@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { ...@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = {
.enable_mask = BIT(12), .enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "spdif_clk", .name = "spdif_clk",
.parent_names = lcc_spdif_parents, .parent_hws = (const struct clk_hw*[]) {
&spdif_src.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch_ops, .ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -384,7 +391,7 @@ static struct clk_rcg ahbix_clk = { ...@@ -384,7 +391,7 @@ static struct clk_rcg ahbix_clk = {
.enable_mask = BIT(11), .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ahbix", .name = "ahbix",
.parent_names = lcc_pxo_pll4, .parent_data = lcc_pxo_pll4,
.num_parents = 2, .num_parents = 2,
.ops = &clk_rcg_lcc_ops, .ops = &clk_rcg_lcc_ops,
}, },
......
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