Commit 758b6712 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A slightly larger set of fixes than we'd like at this point in the
  release.  Hopefully our very last batch before 3.15:

  OMAP:
   - Fix boot regression with CPU_IDLE enabled
   - Fixes for audio playback on OMAP5
   - Clock rate setting fix for OMAP3
   - Misc idle/PM fixes
  Exynos:
   - Removal of a couple of power domains to work around issues with
     access when they are powered down
   - Enabling missing highspeed-i2c driver to make MMC regulators work
   - Secondary CPU spin-up fix for 4212
   - Remove MDMA1 engine to avoid conflicts on secure mode platforms
   - A few other DT fixes
  Marvell:
   - PCI-e fixes for clocks and resource allocation

  plus a few other smaller fixes, add a MAINTAINERS entry for reset
  drivers, etc"

* tag 'fixes-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits)
  MAINTAINERS: Add reset controller framework entry
  ARM: trusted_foundations: fix compile error on non-SMP
  ARM: at91: sam9260: fix compilation issues
  ARM: mvebu: fix definitions of PCIe interfaces on Armada 38x
  ARM: imx: fix error handling in ipu device registration
  ARM: OMAP4: Fix the boot regression with CPU_IDLE enabled
  ARM: dts: Keep LDO4 always ON for exynos5250-arndale board
  ARM: dts: Fix SPI interrupt numbers for exynos5420
  ARM: dts: fix incorrect ak8975 compatible for exynos4412-trats2 board
  ARM: OMAP2+: Fix DMA hang after off-idle
  ARM: OMAP2+: nand: Fix NAND on OMAP2 and OMAP3 boards
  ARM: dts: Remove g2d_pd node for exynos5420
  ARM: dts: Remove mau_pd node for exynos5420
  ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount
  ARM: dts: disable MDMA1 node for exynos5420
  ARM: EXYNOS: fix the secondary CPU boot of exynos4212
  ARM: omap5: hwmod_data: Correct IDLEMODE for McPDM
  ARM: mvebu: mvebu-soc-id: keep clock enabled if PCIe unit is enabled
  ARM: mvebu: mvebu-soc-id: add missing clk_put() call
  ARM: at91/dt: sam9260: correct external trigger value
  ...
parents 51d56652 1b0fe6be
...@@ -7405,6 +7405,14 @@ F: drivers/rpmsg/ ...@@ -7405,6 +7405,14 @@ F: drivers/rpmsg/
F: Documentation/rpmsg.txt F: Documentation/rpmsg.txt
F: include/linux/rpmsg.h F: include/linux/rpmsg.h
RESET CONTROLLER FRAMEWORK
M: Philipp Zabel <p.zabel@pengutronix.de>
S: Maintained
F: drivers/reset/
F: Documentation/devicetree/bindings/reset/
F: include/linux/reset.h
F: include/linux/reset-controller.h
RFKILL RFKILL
M: Johannes Berg <johannes@sipsolutions.net> M: Johannes Berg <johannes@sipsolutions.net>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
......
...@@ -99,7 +99,7 @@ pcie@2,0 { ...@@ -99,7 +99,7 @@ pcie@2,0 {
pcie@3,0 { pcie@3,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>; reg = <0x1800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
......
...@@ -110,7 +110,7 @@ pcie@2,0 { ...@@ -110,7 +110,7 @@ pcie@2,0 {
pcie@3,0 { pcie@3,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>; reg = <0x1800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
...@@ -131,7 +131,7 @@ pcie@3,0 { ...@@ -131,7 +131,7 @@ pcie@3,0 {
pcie@4,0 { pcie@4,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1000 0 0 0 0>; reg = <0x2000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
......
...@@ -641,7 +641,7 @@ trigger@2 { ...@@ -641,7 +641,7 @@ trigger@2 {
trigger@3 { trigger@3 {
reg = <3>; reg = <3>;
trigger-name = "external"; trigger-name = "external";
trigger-value = <0x13>; trigger-value = <0xd>;
trigger-external; trigger-external;
}; };
}; };
......
...@@ -503,7 +503,7 @@ i2c_ak8975: i2c-gpio-0 { ...@@ -503,7 +503,7 @@ i2c_ak8975: i2c-gpio-0 {
status = "okay"; status = "okay";
ak8975@0c { ak8975@0c {
compatible = "ak,ak8975"; compatible = "asahi-kasei,ak8975";
reg = <0x0c>; reg = <0x0c>;
gpios = <&gpj0 7 0>; gpios = <&gpj0 7 0>;
}; };
......
...@@ -107,6 +107,7 @@ ldo4_reg: LDO4 { ...@@ -107,6 +107,7 @@ ldo4_reg: LDO4 {
regulator-name = "VDD_IOPERI_1.8V"; regulator-name = "VDD_IOPERI_1.8V";
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; op_mode = <1>;
}; };
......
...@@ -364,16 +364,4 @@ wakeup { ...@@ -364,16 +364,4 @@ wakeup {
gpio-key,wakeup; gpio-key,wakeup;
}; };
}; };
amba {
mdma1: mdma@11C10000 {
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled";
};
};
}; };
...@@ -219,16 +219,6 @@ disp_pd: power-domain@100440C0 { ...@@ -219,16 +219,6 @@ disp_pd: power-domain@100440C0 {
reg = <0x100440C0 0x20>; reg = <0x100440C0 0x20>;
}; };
mau_pd: power-domain@100440E0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440E0 0x20>;
};
g2d_pd: power-domain@10044100 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044100 0x20>;
};
msc_pd: power-domain@10044120 { msc_pd: power-domain@10044120 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>; reg = <0x10044120 0x20>;
...@@ -336,6 +326,13 @@ mdma1: mdma@11C10000 { ...@@ -336,6 +326,13 @@ mdma1: mdma@11C10000 {
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <1>; #dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled";
}; };
}; };
...@@ -385,7 +382,7 @@ i2s2: i2s@12D70000 { ...@@ -385,7 +382,7 @@ i2s2: i2s@12D70000 {
spi_0: spi@12d20000 { spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi"; compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>; reg = <0x12d20000 0x100>;
interrupts = <0 66 0>; interrupts = <0 68 0>;
dmas = <&pdma0 5 dmas = <&pdma0 5
&pdma0 4>; &pdma0 4>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -401,7 +398,7 @@ spi_0: spi@12d20000 { ...@@ -401,7 +398,7 @@ spi_0: spi@12d20000 {
spi_1: spi@12d30000 { spi_1: spi@12d30000 {
compatible = "samsung,exynos4210-spi"; compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>; reg = <0x12d30000 0x100>;
interrupts = <0 67 0>; interrupts = <0 69 0>;
dmas = <&pdma1 5 dmas = <&pdma1 5
&pdma1 4>; &pdma1 4>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -417,7 +414,7 @@ spi_1: spi@12d30000 { ...@@ -417,7 +414,7 @@ spi_1: spi@12d30000 {
spi_2: spi@12d40000 { spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi"; compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>; reg = <0x12d40000 0x100>;
interrupts = <0 68 0>; interrupts = <0 70 0>;
dmas = <&pdma0 7 dmas = <&pdma0 7
&pdma0 6>; &pdma0 6>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
...@@ -730,6 +727,5 @@ sss@10830000 { ...@@ -730,6 +727,5 @@ sss@10830000 {
interrupts = <0 112 0>; interrupts = <0 112 0>;
clocks = <&clock 471>; clocks = <&clock 471>;
clock-names = "secss"; clock-names = "secss";
samsung,power-domain = <&g2d_pd>;
}; };
}; };
...@@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y ...@@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_I2C_MUX=y CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_EXYNOS5=y
CONFIG_I2C_S3C2410=y CONFIG_I2C_S3C2410=y
CONFIG_DEBUG_GPIO=y CONFIG_DEBUG_GPIO=y
# CONFIG_HWMON is not set # CONFIG_HWMON is not set
......
...@@ -54,7 +54,9 @@ static inline void register_trusted_foundations( ...@@ -54,7 +54,9 @@ static inline void register_trusted_foundations(
*/ */
pr_err("No support for Trusted Foundations, continuing in degraded mode.\n"); pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
pr_err("Secondary processors as well as CPU PM will be disabled.\n"); pr_err("Secondary processors as well as CPU PM will be disabled.\n");
#if IS_ENABLED(CONFIG_SMP)
setup_max_cpus = 0; setup_max_cpus = 0;
#endif
cpu_idle_poll_ctrl(true); cpu_idle_poll_ctrl(true);
} }
......
...@@ -1308,19 +1308,19 @@ static struct platform_device at91_adc_device = { ...@@ -1308,19 +1308,19 @@ static struct platform_device at91_adc_device = {
static struct at91_adc_trigger at91_adc_triggers[] = { static struct at91_adc_trigger at91_adc_triggers[] = {
[0] = { [0] = {
.name = "timer-counter-0", .name = "timer-counter-0",
.value = AT91_ADC_TRGSEL_TC0 | AT91_ADC_TRGEN, .value = 0x1,
}, },
[1] = { [1] = {
.name = "timer-counter-1", .name = "timer-counter-1",
.value = AT91_ADC_TRGSEL_TC1 | AT91_ADC_TRGEN, .value = 0x3,
}, },
[2] = { [2] = {
.name = "timer-counter-2", .name = "timer-counter-2",
.value = AT91_ADC_TRGSEL_TC2 | AT91_ADC_TRGEN, .value = 0x5,
}, },
[3] = { [3] = {
.name = "external", .name = "external",
.value = AT91_ADC_TRGSEL_EXTERNAL | AT91_ADC_TRGEN, .value = 0xd,
.is_external = true, .is_external = true,
}, },
}; };
......
...@@ -18,6 +18,8 @@ ...@@ -18,6 +18,8 @@
#include <mach/map.h> #include <mach/map.h>
#include <plat/cpu.h>
#include "smc.h" #include "smc.h"
static int exynos_do_idle(void) static int exynos_do_idle(void)
...@@ -28,13 +30,24 @@ static int exynos_do_idle(void) ...@@ -28,13 +30,24 @@ static int exynos_do_idle(void)
static int exynos_cpu_boot(int cpu) static int exynos_cpu_boot(int cpu)
{ {
/*
* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
* But, Exynos4212 has only one secondary CPU so second parameter
* isn't used for informing secure firmware about CPU id.
*/
if (soc_is_exynos4212())
cpu = 0;
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0; return 0;
} }
static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{ {
void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu; void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
if (!soc_is_exynos4212())
boot_reg += 4*cpu;
__raw_writel(boot_addr, boot_reg); __raw_writel(boot_addr, boot_reg);
return 0; return 0;
......
...@@ -77,7 +77,7 @@ struct platform_device *__init imx_alloc_mx3_camera( ...@@ -77,7 +77,7 @@ struct platform_device *__init imx_alloc_mx3_camera(
pdev = platform_device_alloc("mx3-camera", 0); pdev = platform_device_alloc("mx3-camera", 0);
if (!pdev) if (!pdev)
goto err; return ERR_PTR(-ENOMEM);
pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
if (!pdev->dev.dma_mask) if (!pdev->dev.dma_mask)
......
...@@ -108,7 +108,18 @@ static int __init mvebu_soc_id_init(void) ...@@ -108,7 +108,18 @@ static int __init mvebu_soc_id_init(void)
iounmap(pci_base); iounmap(pci_base);
res_ioremap: res_ioremap:
/*
* If the PCIe unit is actually enabled and we have PCI
* support in the kernel, we intentionally do not release the
* reference to the clock. We want to keep it running since
* the bootloader does some PCIe link configuration that the
* kernel is for now unable to do, and gating the clock would
* make us loose this precious configuration.
*/
if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) {
clk_disable_unprepare(clk); clk_disable_unprepare(clk);
clk_put(clk);
}
clk_err: clk_err:
of_node_put(child); of_node_put(child);
......
...@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, ...@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
board_nand_data.nr_parts = nr_parts; board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type; board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW; board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
gpmc_nand_init(&board_nand_data, gpmc_t); gpmc_nand_init(&board_nand_data, gpmc_t);
} }
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
......
...@@ -456,7 +456,8 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { ...@@ -456,7 +456,8 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = {
.clkdm_name = "dpll4_clkdm", .clkdm_name = "dpll4_clkdm",
}; };
DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops); DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
static struct clk dpll4_m5x2_ck_3630 = { static struct clk dpll4_m5x2_ck_3630 = {
.name = "dpll4_m5x2_ck", .name = "dpll4_m5x2_ck",
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/cpuidle.h> #include <linux/cpuidle.h>
#include <linux/cpu_pm.h> #include <linux/cpu_pm.h>
#include <linux/export.h> #include <linux/export.h>
#include <linux/clockchips.h>
#include <asm/cpuidle.h> #include <asm/cpuidle.h>
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
...@@ -83,6 +84,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, ...@@ -83,6 +84,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
{ {
struct idle_statedata *cx = state_ptr + index; struct idle_statedata *cx = state_ptr + index;
u32 mpuss_can_lose_context = 0; u32 mpuss_can_lose_context = 0;
int cpu_id = smp_processor_id();
/* /*
* CPU0 has to wait and stay ON until CPU1 is OFF state. * CPU0 has to wait and stay ON until CPU1 is OFF state.
...@@ -110,6 +112,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, ...@@ -110,6 +112,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) && mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
(cx->mpu_logic_state == PWRDM_POWER_OFF); (cx->mpu_logic_state == PWRDM_POWER_OFF);
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
/* /*
* Call idle CPU PM enter notifier chain so that * Call idle CPU PM enter notifier chain so that
* VFP and per CPU interrupt context is saved. * VFP and per CPU interrupt context is saved.
...@@ -165,6 +169,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, ...@@ -165,6 +169,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
if (dev->cpu == 0 && mpuss_can_lose_context) if (dev->cpu == 0 && mpuss_can_lose_context)
cpu_cluster_pm_exit(); cpu_cluster_pm_exit();
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
fail: fail:
cpuidle_coupled_parallel_barrier(dev, &abort_barrier); cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
cpu_done[dev->cpu] = false; cpu_done[dev->cpu] = false;
...@@ -172,6 +178,16 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, ...@@ -172,6 +178,16 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
return index; return index;
} }
/*
* For each cpu, setup the broadcast timer because local timers
* stops for the states above C1.
*/
static void omap_setup_broadcast_timer(void *arg)
{
int cpu = smp_processor_id();
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
}
static struct cpuidle_driver omap4_idle_driver = { static struct cpuidle_driver omap4_idle_driver = {
.name = "omap4_idle", .name = "omap4_idle",
.owner = THIS_MODULE, .owner = THIS_MODULE,
...@@ -189,8 +205,7 @@ static struct cpuidle_driver omap4_idle_driver = { ...@@ -189,8 +205,7 @@ static struct cpuidle_driver omap4_idle_driver = {
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
.exit_latency = 328 + 440, .exit_latency = 328 + 440,
.target_residency = 960, .target_residency = 960,
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
CPUIDLE_FLAG_TIMER_STOP,
.enter = omap_enter_idle_coupled, .enter = omap_enter_idle_coupled,
.name = "C2", .name = "C2",
.desc = "CPUx OFF, MPUSS CSWR", .desc = "CPUx OFF, MPUSS CSWR",
...@@ -199,8 +214,7 @@ static struct cpuidle_driver omap4_idle_driver = { ...@@ -199,8 +214,7 @@ static struct cpuidle_driver omap4_idle_driver = {
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
.exit_latency = 460 + 518, .exit_latency = 460 + 518,
.target_residency = 1100, .target_residency = 1100,
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
CPUIDLE_FLAG_TIMER_STOP,
.enter = omap_enter_idle_coupled, .enter = omap_enter_idle_coupled,
.name = "C3", .name = "C3",
.desc = "CPUx OFF, MPUSS OSWR", .desc = "CPUx OFF, MPUSS OSWR",
...@@ -231,5 +245,8 @@ int __init omap4_idle_init(void) ...@@ -231,5 +245,8 @@ int __init omap4_idle_init(void)
if (!cpu_clkdm[0] || !cpu_clkdm[1]) if (!cpu_clkdm[0] || !cpu_clkdm[1])
return -ENODEV; return -ENODEV;
/* Configure the broadcast timer on each cpu */
on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
return cpuidle_register(&omap4_idle_driver, cpu_online_mask); return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
} }
...@@ -895,7 +895,7 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = { ...@@ -895,7 +895,7 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = {
* current exception. * current exception.
*/ */
.flags = HWMOD_EXT_OPT_MAIN_CLK, .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
.main_clk = "pad_clks_ck", .main_clk = "pad_clks_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
......
...@@ -70,6 +70,7 @@ static u32 errata; ...@@ -70,6 +70,7 @@ static u32 errata;
static struct omap_dma_global_context_registers { static struct omap_dma_global_context_registers {
u32 dma_irqenable_l0; u32 dma_irqenable_l0;
u32 dma_irqenable_l1;
u32 dma_ocp_sysconfig; u32 dma_ocp_sysconfig;
u32 dma_gcr; u32 dma_gcr;
} omap_dma_global_context; } omap_dma_global_context;
...@@ -1973,10 +1974,17 @@ static struct irqaction omap24xx_dma_irq; ...@@ -1973,10 +1974,17 @@ static struct irqaction omap24xx_dma_irq;
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/*
* Note that we are currently using only IRQENABLE_L0 and L1.
* As the DSP may be using IRQENABLE_L2 and L3, let's not
* touch those for now.
*/
void omap_dma_global_context_save(void) void omap_dma_global_context_save(void)
{ {
omap_dma_global_context.dma_irqenable_l0 = omap_dma_global_context.dma_irqenable_l0 =
p->dma_read(IRQENABLE_L0, 0); p->dma_read(IRQENABLE_L0, 0);
omap_dma_global_context.dma_irqenable_l1 =
p->dma_read(IRQENABLE_L1, 0);
omap_dma_global_context.dma_ocp_sysconfig = omap_dma_global_context.dma_ocp_sysconfig =
p->dma_read(OCP_SYSCONFIG, 0); p->dma_read(OCP_SYSCONFIG, 0);
omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
...@@ -1991,6 +1999,8 @@ void omap_dma_global_context_restore(void) ...@@ -1991,6 +1999,8 @@ void omap_dma_global_context_restore(void)
OCP_SYSCONFIG, 0); OCP_SYSCONFIG, 0);
p->dma_write(omap_dma_global_context.dma_irqenable_l0, p->dma_write(omap_dma_global_context.dma_irqenable_l0,
IRQENABLE_L0, 0); IRQENABLE_L0, 0);
p->dma_write(omap_dma_global_context.dma_irqenable_l1,
IRQENABLE_L1, 0);
if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
p->dma_write(0x3 , IRQSTATUS_L0, 0); p->dma_write(0x3 , IRQSTATUS_L0, 0);
......
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