Commit 759e2a25 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin

Pull blackfin changes from Bob Liu:
 "The big changes are adding PM and HDMI support for bf60x, other
  patches are various bug fix and code cleanup."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin: (48 commits)
  bf60x: fix build warning
  PM: add BF60x flash suspend and resume support
  blackfin: twi: read twi mmr via bfin_read macro
  dpm: deepsleep: reserve stack
  bf60x: cpufreq: fix anomaly 05000273
  bf609: add adv7511 display support
  blackfin: cplb-nompu: fix ROM cplb size for bf609-ezkit
  bf60x: Add double fault, hardware error and NMI SEC handler
  bf60x: update anomaly id in serial and twi driver headers.
  bf60x: vs6624 pin update
  bf60x: add default anomaly setting.
  bf60x: update bf60x anomaly list.
  bf60x: sec: Enable sec interrupt source priority configuration.
  bf60x: sec: Clean up interrupt initialization code for SEC.
  bf609: reuse bf5xx-i2s-pcm.c as i2s pcm driver
  bf561: add capabilities in adv7183_inputs
  bf609: convert vs6624 blank_clocks to black_pixels
  blackfin: fix musb macro name
  cleanup: sec and linkport only built on bf60x
  bfin: pint: add pint suspend and resume
  ...
parents 90e66dd9 719154c6
...@@ -352,6 +352,11 @@ config MEM_MT48H32M16LFCJ_75 ...@@ -352,6 +352,11 @@ config MEM_MT48H32M16LFCJ_75
depends on (BFIN526_EZBRD) depends on (BFIN526_EZBRD)
default y default y
config MEM_MT47H64M16
bool
depends on (BFIN609_EZKIT)
default y
source "arch/blackfin/mach-bf518/Kconfig" source "arch/blackfin/mach-bf518/Kconfig"
source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf533/Kconfig"
...@@ -399,8 +404,9 @@ config ROM_BASE ...@@ -399,8 +404,9 @@ config ROM_BASE
hex "Kernel ROM Base" hex "Kernel ROM Base"
depends on ROMKERNEL depends on ROMKERNEL
default "0x20040040" default "0x20040040"
range 0x20000000 0x20400000 if !(BF54x || BF561) range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
range 0x20000000 0x30000000 if (BF54x || BF561) range 0x20000000 0x30000000 if (BF54x || BF561)
range 0xB0000000 0xC0000000 if (BF60x)
help help
Make sure your ROM base does not include any file-header Make sure your ROM base does not include any file-header
information that is prepended to the kernel. information that is prepended to the kernel.
...@@ -1009,6 +1015,12 @@ config HAVE_PWM ...@@ -1009,6 +1015,12 @@ config HAVE_PWM
choice choice
prompt "Uncached DMA region" prompt "Uncached DMA region"
default DMA_UNCACHED_1M default DMA_UNCACHED_1M
config DMA_UNCACHED_32M
bool "Enable 32M DMA region"
config DMA_UNCACHED_16M
bool "Enable 16M DMA region"
config DMA_UNCACHED_8M
bool "Enable 8M DMA region"
config DMA_UNCACHED_4M config DMA_UNCACHED_4M
bool "Enable 4M DMA region" bool "Enable 4M DMA region"
config DMA_UNCACHED_2M config DMA_UNCACHED_2M
...@@ -1038,7 +1050,7 @@ config BFIN_EXTMEM_ICACHEABLE ...@@ -1038,7 +1050,7 @@ config BFIN_EXTMEM_ICACHEABLE
config BFIN_L2_ICACHEABLE config BFIN_L2_ICACHEABLE
bool "Enable ICACHE for L2 SRAM" bool "Enable ICACHE for L2 SRAM"
depends on BFIN_ICACHE depends on BFIN_ICACHE
depends on BF54x || BF561 depends on (BF54x || BF561 || BF60x) && !SMP
default n default n
config BFIN_DCACHE config BFIN_DCACHE
......
...@@ -90,6 +90,7 @@ CONFIG_INPUT_BFIN_ROTARY=y ...@@ -90,6 +90,7 @@ CONFIG_INPUT_BFIN_ROTARY=y
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set # CONFIG_LEGACY_PTYS is not set
CONFIG_BFIN_SIMPLE_TIMER=m CONFIG_BFIN_SIMPLE_TIMER=m
# CONFIG_BFIN_CRC is not set
CONFIG_BFIN_LINKPORT=y CONFIG_BFIN_LINKPORT=y
# CONFIG_DEVKMEM is not set # CONFIG_DEVKMEM is not set
CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN=y
...@@ -153,3 +154,4 @@ CONFIG_CRYPTO_MD4=y ...@@ -153,3 +154,4 @@ CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DEV_BFIN_CRC=y
...@@ -14,7 +14,13 @@ ...@@ -14,7 +14,13 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/types.h> #include <linux/types.h>
#if defined(CONFIG_DMA_UNCACHED_4M) #if defined(CONFIG_DMA_UNCACHED_32M)
# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
#elif defined(CONFIG_DMA_UNCACHED_16M)
# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
#elif defined(CONFIG_DMA_UNCACHED_8M)
# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
#elif defined(CONFIG_DMA_UNCACHED_4M)
# define DMA_UNCACHED_REGION (4 * 1024 * 1024) # define DMA_UNCACHED_REGION (4 * 1024 * 1024)
#elif defined(CONFIG_DMA_UNCACHED_2M) #elif defined(CONFIG_DMA_UNCACHED_2M)
# define DMA_UNCACHED_REGION (2 * 1024 * 1024) # define DMA_UNCACHED_REGION (2 * 1024 * 1024)
......
...@@ -79,20 +79,6 @@ struct crc_register { ...@@ -79,20 +79,6 @@ struct crc_register {
u32 revid; u32 revid;
}; };
struct bfin_crc {
struct miscdevice mdev;
struct list_head list;
int irq;
int dma_ch_src;
int dma_ch_dest;
volatile struct crc_register *regs;
struct crc_info *info;
struct mutex mutex;
struct completion c;
unsigned short opmode;
char name[20];
};
/* CRC_STATUS Masks */ /* CRC_STATUS Masks */
#define CMPERR 0x00000002 /* Compare error */ #define CMPERR 0x00000002 /* Compare error */
#define DCNTEXP 0x00000010 /* datacnt register expired */ #define DCNTEXP 0x00000010 /* datacnt register expired */
......
...@@ -282,7 +282,7 @@ struct bfin_uart_regs { ...@@ -282,7 +282,7 @@ struct bfin_uart_regs {
#define UART_GET_GCTL(p) UART_GET_CTL(p) #define UART_GET_GCTL(p) UART_GET_CTL(p)
#define UART_GET_LCR(p) UART_GET_CTL(p) #define UART_GET_LCR(p) UART_GET_CTL(p)
#define UART_GET_MCR(p) UART_GET_CTL(p) #define UART_GET_MCR(p) UART_GET_CTL(p)
#if ANOMALY_05001001 #if ANOMALY_16000030
#define UART_GET_STAT(p) \ #define UART_GET_STAT(p) \
({ \ ({ \
u32 __ret; \ u32 __ret; \
......
...@@ -17,5 +17,11 @@ ...@@ -17,5 +17,11 @@
#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) #define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) #define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) #define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0
#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1
#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2
#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3
#endif #endif
...@@ -66,9 +66,9 @@ struct bfin_twi_iface { ...@@ -66,9 +66,9 @@ struct bfin_twi_iface {
#define DEFINE_TWI_REG(reg_name, reg) \ #define DEFINE_TWI_REG(reg_name, reg) \
static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
{ return iface->regs_base->reg; } \ { return bfin_read16(&iface->regs_base->reg); } \
static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
{ iface->regs_base->reg = v; } { bfin_write16(&iface->regs_base->reg, v); }
DEFINE_TWI_REG(CLKDIV, clkdiv) DEFINE_TWI_REG(CLKDIV, clkdiv)
DEFINE_TWI_REG(CONTROL, control) DEFINE_TWI_REG(CONTROL, control)
...@@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl) ...@@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
DEFINE_TWI_REG(FIFO_STAT, fifo_stat) DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
DEFINE_TWI_REG(XMT_DATA8, xmt_data8) DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
DEFINE_TWI_REG(XMT_DATA16, xmt_data16) DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
#if !ANOMALY_05001001 #if !ANOMALY_16000030
DEFINE_TWI_REG(RCV_DATA8, rcv_data8) DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
DEFINE_TWI_REG(RCV_DATA16, rcv_data16) DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
#else #else
...@@ -94,7 +94,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) ...@@ -94,7 +94,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
unsigned long flags; unsigned long flags;
flags = hard_local_irq_save(); flags = hard_local_irq_save();
ret = iface->regs_base->rcv_data8; ret = bfin_read16(&iface->regs_base->rcv_data8);
hard_local_irq_restore(flags); hard_local_irq_restore(flags);
return ret; return ret;
...@@ -106,7 +106,7 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) ...@@ -106,7 +106,7 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
unsigned long flags; unsigned long flags;
flags = hard_local_irq_save(); flags = hard_local_irq_save();
ret = iface->regs_base->rcv_data16; ret = bfin_read16(&iface->regs_base->rcv_data16);
hard_local_irq_restore(flags); hard_local_irq_restore(flags);
return ret; return ret;
......
...@@ -396,3 +396,12 @@ ...@@ -396,3 +396,12 @@
call \func; call \func;
#endif #endif
.endm .endm
#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
# define EX_SCRATCH_REG RETN
#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
# define EX_SCRATCH_REG RETE
#else
# define EX_SCRATCH_REG CYCLES
#endif
...@@ -280,7 +280,7 @@ ...@@ -280,7 +280,7 @@
PM_POP_SYNC(9) PM_POP_SYNC(9)
#endif #endif
#ifdef EBIU_AMBCTL #ifdef EBIU_AMGCTL
PM_SYS_POP(9, EBIU_AMBCTL1) PM_SYS_POP(9, EBIU_AMBCTL1)
PM_SYS_POP(8, EBIU_AMBCTL0) PM_SYS_POP(8, EBIU_AMBCTL0)
PM_SYS_POP16(7, EBIU_AMGCTL) PM_SYS_POP16(7, EBIU_AMGCTL)
......
...@@ -141,6 +141,8 @@ static inline void bfin_pm_standby_restore(void) ...@@ -141,6 +141,8 @@ static inline void bfin_pm_standby_restore(void)
void bfin_gpio_pm_hibernate_restore(void); void bfin_gpio_pm_hibernate_restore(void);
void bfin_gpio_pm_hibernate_suspend(void); void bfin_gpio_pm_hibernate_suspend(void);
void bfin_pint_suspend(void);
void bfin_pint_resume(void);
# if !BFIN_GPIO_PINT # if !BFIN_GPIO_PINT
int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
......
...@@ -20,6 +20,16 @@ ...@@ -20,6 +20,16 @@
/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
#include <mach/irq.h> #include <mach/irq.h>
/*
* pm save bfin pint registers
*/
struct bfin_pm_pint_save {
u32 mask_set;
u32 assign;
u32 edge_set;
u32 invert_set;
};
#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
# define NOP_PAD_ANOMALY_05000244 "nop; nop;" # define NOP_PAD_ANOMALY_05000244 "nop; nop;"
#else #else
......
...@@ -6,6 +6,9 @@ ...@@ -6,6 +6,9 @@
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
#ifndef __MEM_INIT_H__
#define __MEM_INIT_H__
#if defined(EBIU_SDGCTL) #if defined(EBIU_SDGCTL)
#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
...@@ -277,3 +280,212 @@ ...@@ -277,3 +280,212 @@
#else #else
#define PLL_BYPASS 0 #define PLL_BYPASS 0
#endif #endif
#ifdef CONFIG_BF60x
/* DMC status bits */
#define IDLE 0x1
#define MEMINITDONE 0x4
#define SRACK 0x8
#define PDACK 0x10
#define DPDACK 0x20
#define DLLCALDONE 0x2000
#define PENDREF 0xF0000
#define PHYRDPHASE 0xF00000
#define PHYRDPHASE_OFFSET 20
/* DMC control bits */
#define LPDDR 0x2
#define INIT 0x4
#define SRREQ 0x8
#define PDREQ 0x10
#define DPDREQ 0x20
#define PREC 0x40
#define ADDRMODE 0x100
#define RDTOWR 0xE00
#define PPREF 0x1000
#define DLLCAL 0x2000
/* DMC DLL control bits */
#define DLLCALRDCNT 0xFF
#define DATACYC 0xF00
#define DATACYC_OFFSET 8
/* CGU Divisor bits */
#define CSEL_OFFSET 0
#define S0SEL_OFFSET 5
#define SYSSEL_OFFSET 8
#define S1SEL_OFFSET 13
#define DSEL_OFFSET 16
#define OSEL_OFFSET 22
#define ALGN 0x20000000
#define UPDT 0x40000000
#define LOCK 0x80000000
/* CGU Status bits */
#define PLLEN 0x1
#define PLLBP 0x2
#define PLOCK 0x4
#define CLKSALGN 0x8
/* CGU Control bits */
#define MSEL_MASK 0x7F00
#define DF_MASK 0x1
struct ddr_config {
u32 ddr_clk;
u32 dmc_ddrctl;
u32 dmc_ddrcfg;
u32 dmc_ddrtr0;
u32 dmc_ddrtr1;
u32 dmc_ddrtr2;
u32 dmc_ddrmr;
u32 dmc_ddrmr1;
};
#if defined(CONFIG_MEM_MT47H64M16)
static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
[0] = {
.ddr_clk = 125,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20705212,
.dmc_ddrtr1 = 0x201003CF,
.dmc_ddrtr2 = 0x00320107,
.dmc_ddrmr = 0x00000422,
.dmc_ddrmr1 = 0x4,
},
[1] = {
.ddr_clk = 133,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20806313,
.dmc_ddrtr1 = 0x2013040D,
.dmc_ddrtr2 = 0x00320108,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[2] = {
.ddr_clk = 150,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20A07323,
.dmc_ddrtr1 = 0x20160492,
.dmc_ddrtr2 = 0x00320209,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[3] = {
.ddr_clk = 166,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20A07323,
.dmc_ddrtr1 = 0x2016050E,
.dmc_ddrtr2 = 0x00320209,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[4] = {
.ddr_clk = 200,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20a07323,
.dmc_ddrtr1 = 0x2016050f,
.dmc_ddrtr2 = 0x00320509,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[5] = {
.ddr_clk = 225,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20E0A424,
.dmc_ddrtr1 = 0x302006DB,
.dmc_ddrtr2 = 0x0032020D,
.dmc_ddrmr = 0x00000842,
.dmc_ddrmr1 = 0x4,
},
[6] = {
.ddr_clk = 250,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20E0A424,
.dmc_ddrtr1 = 0x3020079E,
.dmc_ddrtr2 = 0x0032020D,
.dmc_ddrmr = 0x00000842,
.dmc_ddrmr1 = 0x4,
},
};
#endif
static inline void dmc_enter_self_refresh(void)
{
if (bfin_read_DMC0_STAT() & MEMINITDONE) {
bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
while (!(bfin_read_DMC0_STAT() & SRACK))
continue;
}
}
static inline void dmc_exit_self_refresh(void)
{
if (bfin_read_DMC0_STAT() & MEMINITDONE) {
bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
while (bfin_read_DMC0_STAT() & SRACK)
continue;
}
}
static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
{
dmc_enter_self_refresh();
/* Don't set the same value of MSEL and DF to CGU_CTL */
if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
!= cgu_ctl) {
bfin_write32(CGU0_DIV, cgu_div);
bfin_write32(CGU0_CTL, cgu_ctl);
while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
!(bfin_read32(CGU0_STAT) & PLOCK))
continue;
}
bfin_write32(CGU0_DIV, cgu_div | UPDT);
while (bfin_read32(CGU0_STAT) & CLKSALGN)
continue;
dmc_exit_self_refresh();
}
static inline void init_dmc(u32 dmc_clk)
{
int i, dlldatacycle, dll_ctl;
for (i = 0; i < 7; i++) {
if (ddr_config_table[i].ddr_clk == dmc_clk) {
bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
break;
}
}
while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
continue;
dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
dll_ctl = bfin_read_DMC0_DLLCTL();
dll_ctl &= ~DATACYC;
bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
continue;
}
#endif
#endif /*__MEM_INIT_H__*/
...@@ -125,5 +125,7 @@ ...@@ -125,5 +125,7 @@
level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
level " only instructions.\n" level " only instructions.\n"
extern void double_fault_c(struct pt_regs *fp);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* _BFIN_TRAPS_H */ #endif /* _BFIN_TRAPS_H */
...@@ -45,7 +45,7 @@ static int __init blackfin_dma_init(void) ...@@ -45,7 +45,7 @@ static int __init blackfin_dma_init(void)
atomic_set(&dma_ch[i].chan_status, 0); atomic_set(&dma_ch[i].chan_status, 0);
dma_ch[i].regs = dma_io_base_addr[i]; dma_ch[i].regs = dma_io_base_addr[i];
} }
#ifdef CH_MEM_STREAM3_SRC #if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
/* Mark MEMDMA Channel 3 as requested since we're using it internally */ /* Mark MEMDMA Channel 3 as requested since we're using it internally */
request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy"); request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy"); request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
...@@ -361,7 +361,7 @@ void __init early_dma_memcpy_done(void) ...@@ -361,7 +361,7 @@ void __init early_dma_memcpy_done(void)
__builtin_bfin_ssync(); __builtin_bfin_ssync();
} }
#ifdef CH_MEM_STREAM3_SRC #if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG #define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG #define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR #define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
......
...@@ -58,11 +58,19 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) ...@@ -58,11 +58,19 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
#ifdef CONFIG_ROMKERNEL #ifdef CONFIG_ROMKERNEL
/* Cover kernel XIP flash area */ /* Cover kernel XIP flash area */
#ifdef CONFIG_BF60x
addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
d_tbl[i_d].addr = addr;
d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
i_tbl[i_i].addr = addr;
i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
#else
addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1); addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
d_tbl[i_d].addr = addr; d_tbl[i_d].addr = addr;
d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
i_tbl[i_i].addr = addr; i_tbl[i_i].addr = addr;
i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
#endif
#endif #endif
/* Cover L1 memory. One 4M area for code and data each is enough. */ /* Cover L1 memory. One 4M area for code and data each is enough. */
......
...@@ -122,12 +122,13 @@ void __dma_sync(dma_addr_t addr, size_t size, ...@@ -122,12 +122,13 @@ void __dma_sync(dma_addr_t addr, size_t size,
EXPORT_SYMBOL(__dma_sync); EXPORT_SYMBOL(__dma_sync);
int int
dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, dma_map_sg(struct device *dev, struct scatterlist *sg_list, int nents,
enum dma_data_direction direction) enum dma_data_direction direction)
{ {
struct scatterlist *sg;
int i; int i;
for (i = 0; i < nents; i++, sg++) { for_each_sg(sg_list, sg, nents, i) {
sg->dma_address = (dma_addr_t) sg_virt(sg); sg->dma_address = (dma_addr_t) sg_virt(sg);
__dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
} }
...@@ -136,12 +137,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, ...@@ -136,12 +137,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
} }
EXPORT_SYMBOL(dma_map_sg); EXPORT_SYMBOL(dma_map_sg);
void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg_list,
int nelems, enum dma_data_direction direction) int nelems, enum dma_data_direction direction)
{ {
struct scatterlist *sg;
int i; int i;
for (i = 0; i < nelems; i++, sg++) { for_each_sg(sg_list, sg, nelems, i) {
sg->dma_address = (dma_addr_t) sg_virt(sg); sg->dma_address = (dma_addr_t) sg_virt(sg);
__dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
} }
......
...@@ -114,9 +114,9 @@ static struct musb_hdrc_config musb_config = { ...@@ -114,9 +114,9 @@ static struct musb_hdrc_config musb_config = {
}; };
static struct musb_hdrc_platform_data musb_plat = { static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG) #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_OTG, .mode = MUSB_OTG,
#elif defined(CONFIG_USB_MUSB_HDRC_HCD) #elif defined(CONFIG_USB_MUSB_HDRC)
.mode = MUSB_HOST, .mode = MUSB_HOST,
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL, .mode = MUSB_PERIPHERAL,
......
...@@ -635,9 +635,9 @@ static struct musb_hdrc_config musb_config = { ...@@ -635,9 +635,9 @@ static struct musb_hdrc_config musb_config = {
}; };
static struct musb_hdrc_platform_data musb_plat = { static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG) #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_OTG, .mode = MUSB_OTG,
#elif defined(CONFIG_USB_MUSB_HDRC_HCD) #elif defined(CONFIG_USB_MUSB_HDRC)
.mode = MUSB_HOST, .mode = MUSB_HOST,
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL, .mode = MUSB_PERIPHERAL,
......
...@@ -171,6 +171,8 @@ ...@@ -171,6 +171,8 @@
#define MAX_BLACKFIN_GPIOS 160 #define MAX_BLACKFIN_GPIOS 160
#define BFIN_GPIO_PINT 1 #define BFIN_GPIO_PINT 1
#define NR_PINT_SYS_IRQS 4
#define NR_PINTS 160
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
......
...@@ -452,18 +452,21 @@ static struct v4l2_input adv7183_inputs[] = { ...@@ -452,18 +452,21 @@ static struct v4l2_input adv7183_inputs[] = {
.name = "Composite", .name = "Composite",
.type = V4L2_INPUT_TYPE_CAMERA, .type = V4L2_INPUT_TYPE_CAMERA,
.std = V4L2_STD_ALL, .std = V4L2_STD_ALL,
.capabilities = V4L2_IN_CAP_STD,
}, },
{ {
.index = 1, .index = 1,
.name = "S-Video", .name = "S-Video",
.type = V4L2_INPUT_TYPE_CAMERA, .type = V4L2_INPUT_TYPE_CAMERA,
.std = V4L2_STD_ALL, .std = V4L2_STD_ALL,
.capabilities = V4L2_IN_CAP_STD,
}, },
{ {
.index = 2, .index = 2,
.name = "Component", .name = "Component",
.type = V4L2_INPUT_TYPE_CAMERA, .type = V4L2_INPUT_TYPE_CAMERA,
.std = V4L2_STD_ALL, .std = V4L2_STD_ALL,
.capabilities = V4L2_IN_CAP_STD,
}, },
}; };
......
...@@ -51,6 +51,14 @@ config PINT5_ASSIGN ...@@ -51,6 +51,14 @@ config PINT5_ASSIGN
endmenu endmenu
config SEC_IRQ_PRIORITY_LEVELS
int "SEC interrupt priority levels"
default 7
range 0 7
help
Devide the total number of interrupt priority levels into sub-levels.
There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
endmenu endmenu
endif endif
...@@ -2,5 +2,5 @@ ...@@ -2,5 +2,5 @@
# arch/blackfin/mach-bf609/Makefile # arch/blackfin/mach-bf609/Makefile
# #
obj-y := dma.o clock.o obj-y := dma.o clock.o ints-priority.o
obj-$(CONFIG_PM) += pm.o hibernate.o obj-$(CONFIG_PM) += pm.o dpm.o
This diff is collapsed.
...@@ -97,9 +97,10 @@ int wait_for_pll_align(void) ...@@ -97,9 +97,10 @@ int wait_for_pll_align(void)
while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN)); while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) { if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
printk(KERN_DEBUG "fail to align clk\n"); printk(KERN_CRIT "fail to align clk\n");
return -1; return -1;
} }
return 0; return 0;
} }
......
...@@ -2,6 +2,8 @@ ...@@ -2,6 +2,8 @@
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/dpmc.h> #include <asm/dpmc.h>
#include <asm/context.S>
#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) #define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
.section .l1.text .section .l1.text
...@@ -30,7 +32,97 @@ ENTRY(_enter_hibernate) ...@@ -30,7 +32,97 @@ ENTRY(_enter_hibernate)
[P0] = R3; [P0] = R3;
SSYNC; SSYNC;
ENDPROC(_enter_hibernate_mode) ENDPROC(_enter_hibernate)
/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
* is disabled. This behavior differ from bf5xx serial processor.
*/
ENTRY(_dummy_deepsleep)
[--sp] = SYSCFG;
[--sp] = (R7:0,P5:0);
cli r0;
/* get wake up interrupt ID */
P0.l = LO(SEC_SCI_BASE + SEC_CSID);
P0.h = HI(SEC_SCI_BASE + SEC_CSID);
R0 = [P0];
/* ACK wake up interrupt in SEC */
P1.l = LO(SEC_END);
P1.h = HI(SEC_END);
[P1] = R0;
SSYNC;
/* restore EVT 11 entry */
p0.h = hi(EVT11);
p0.l = lo(EVT11);
p1.h = _evt_evt11;
p1.l = _evt_evt11;
[p0] = p1;
SSYNC;
(R7:0,P5:0) = [sp++];
SYSCFG = [sp++];
RTI;
ENDPROC(_dummy_deepsleep)
ENTRY(_enter_deepsleep)
LINK 0xC;
[--sp] = (R7:0,P5:0);
/* Change EVT 11 entry to dummy handler for wake up event */
p0.h = hi(EVT11);
p0.l = lo(EVT11);
p1.h = _dummy_deepsleep;
p1.l = _dummy_deepsleep;
[p0] = p1;
P0.H = HI(PM_STACK);
P0.L = LO(PM_STACK);
EX_SCRATCH_REG = SP;
SP = P0;
SSYNC;
/* should put ddr to self refresh mode before sleep */
call _bf609_ddr_sr;
/* Set DPM controller to deep sleep mode */
P0.H = HI(DPM0_CTL);
P0.L = LO(DPM0_CTL);
R3.H = HI(0x00000008);
R3.L = LO(0x00000008);
[P0] = R3;
CSYNC;
/* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
r0.l = 0x800;
r0.h = 0;
sti r0;
SSYNC;
bfin_init_pm_bench_cycles;
/* Fall into deep sleep in idle*/
idle;
SSYNC;
/* Restore PLL after wake up from deep sleep */
call _bf609_resume_ccbuf;
/* turn ddr out of self refresh mode */
call _bf609_ddr_sr_exit;
SP = EX_SCRATCH_REG;
(R7:0,P5:0) = [SP++];
UNLINK;
RTS;
ENDPROC(_enter_deepsleep)
.section .text .section .text
ENTRY(_bf609_hibernate) ENTRY(_bf609_hibernate)
......
...@@ -5,126 +5,99 @@ ...@@ -5,126 +5,99 @@
* and can be replaced with that version at any time * and can be replaced with that version at any time
* DO NOT EDIT THIS FILE * DO NOT EDIT THIS FILE
* *
* Copyright 2004-2011 Analog Devices Inc. * Copyright 2004-2012 Analog Devices Inc.
* Licensed under the Clear BSD license. * Licensed under the Clear BSD license.
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
*/ */
#if __SILICON_REVISION__ < 0 #if __SILICON_REVISION__ < 0
# error will not work on BF506 silicon version # error will not work on BF609 silicon version
#endif #endif
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
#define ANOMALY_05000074 (1) #define ANOMALY_16000003 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* The EPPI Data Enable (DEN) Signal is Not Functional */
#define ANOMALY_05000119 (1) #define ANOMALY_16000004 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Using L1 Instruction Cache with Parity Enabled is Unreliable */
#define ANOMALY_05000122 (1) #define ANOMALY_16000005 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
#define ANOMALY_05000245 (1) #define ANOMALY_16000006 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ /* DDR2 Memory Reads May Fail Intermittently */
#define ANOMALY_05000254 (1) #define ANOMALY_16000007 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000265 (1) #define ANOMALY_16000008 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* TestSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000310 (1) #define ANOMALY_16000009 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_16000010 (1)
/* UART IrDA Receiver Fails on Extended Bit Pulses */
#define ANOMALY_05000447 (1)
/* False Hardware Error when RETI Points to Invalid Memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_16000011 (1)
/* PLL Latches Incorrect Settings During Reset */ /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000469 (1) #define ANOMALY_16000012 (1)
/* Incorrect Default MSEL Value in PLL_CTL */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000472 (1) #define ANOMALY_16000013 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000473 (1) #define ANOMALY_16000014 (1)
/* TESTSET Instruction Cannot Be Interrupted */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000477 (1) #define ANOMALY_16000015 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ /* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000481 (1) #define ANOMALY_16000017 (1)
/* IFLUSH sucks at life */ /* RSI Boot Cleanup Routine Does Not Clear Registers */
#define ANOMALY_05000491 (1) #define ANOMALY_16000018 (1)
/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */ /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
#define ANOMALY_05001001 (__SILICON_REVISION__ < 1) #define ANOMALY_16000019 (1)
/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
#define ANOMALY_16000020 (1)
/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
#define ANOMALY_16000021 (1)
/* Boot Code Fails to Enable Parity Fault Detection */
#define ANOMALY_16000022 (1)
/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
#define ANOMALY_16000027 (1)
/* Interrupted Core Reads of MMRs May Cause Data Loss */
#define ANOMALY_16000030 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0) #define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0) #define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0) #define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0) #define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000357 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000440 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0) #define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0) #define ANOMALY_05000456 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000480 (0) #define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0) #define ANOMALY_05000481 (1)
/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
#define ANOMALY_05000491 ANOMALY_16000008
#define ANOMALY_05000477 ANOMALY_16000009
#define ANOMALY_05000443 ANOMALY_16000010
#define ANOMALY_05000461 ANOMALY_16000011
#define ANOMALY_05000426 ANOMALY_16000012
#define ANOMALY_05000310 ANOMALY_16000013
#define ANOMALY_05000245 ANOMALY_16000014
#define ANOMALY_05000074 ANOMALY_16000015
#define ANOMALY_05000416 ANOMALY_16000017
#endif #endif
...@@ -2665,7 +2665,6 @@ ...@@ -2665,7 +2665,6 @@
#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */ #define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */ #define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
/* ========================= /* =========================
L2CTL Registers L2CTL Registers
========================= */ ========================= */
......
...@@ -123,6 +123,8 @@ ...@@ -123,6 +123,8 @@
#define BFIN_GPIO_PINT 1 #define BFIN_GPIO_PINT 1
#define NR_PINT_SYS_IRQS 6
#define NR_PINTS 112
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
......
...@@ -293,9 +293,13 @@ ...@@ -293,9 +293,13 @@
#define NR_MACH_IRQS (IRQ_PG15 + 1) #define NR_MACH_IRQS (IRQ_PG15 + 1)
#define SEC_SCTL_PRIO_OFFSET 8
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <linux/types.h> #include <linux/types.h>
extern u8 sec_int_priority[];
/* /*
* bfin pint registers layout * bfin pint registers layout
*/ */
......
...@@ -11,11 +11,14 @@ ...@@ -11,11 +11,14 @@
#include <linux/suspend.h> #include <linux/suspend.h>
int bfin609_pm_enter(suspend_state_t state); extern int bfin609_pm_enter(suspend_state_t state);
int bf609_pm_prepare(void); extern int bf609_pm_prepare(void);
void bf609_pm_finish(void); extern void bf609_pm_finish(void);
void bf609_hibernate(void); void bf609_hibernate(void);
void bfin_sec_raise_irq(unsigned int sid); void bfin_sec_raise_irq(unsigned int sid);
void coreb_enable(void); void coreb_enable(void);
int bf609_nor_flash_init(void);
void bf609_nor_flash_exit(void);
#endif #endif
/*
* Copyright 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*
* Set up the interrupt priorities
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/blackfin.h>
u8 sec_int_priority[] = {
255, /* IRQ_SEC_ERR */
255, /* IRQ_CGU_EVT */
254, /* IRQ_WATCH0 */
254, /* IRQ_WATCH1 */
253, /* IRQ_L2CTL0_ECC_ERR */
253, /* IRQ_L2CTL0_ECC_WARN */
253, /* IRQ_C0_DBL_FAULT */
253, /* IRQ_C1_DBL_FAULT */
252, /* IRQ_C0_HW_ERR */
252, /* IRQ_C1_HW_ERR */
255, /* IRQ_C0_NMI_L1_PARITY_ERR */
255, /* IRQ_C1_NMI_L1_PARITY_ERR */
50, /* IRQ_TIMER0 */
50, /* IRQ_TIMER1 */
50, /* IRQ_TIMER2 */
50, /* IRQ_TIMER3 */
50, /* IRQ_TIMER4 */
50, /* IRQ_TIMER5 */
50, /* IRQ_TIMER6 */
50, /* IRQ_TIMER7 */
50, /* IRQ_TIMER_STAT */
0, /* IRQ_PINT0 */
0, /* IRQ_PINT1 */
0, /* IRQ_PINT2 */
0, /* IRQ_PINT3 */
0, /* IRQ_PINT4 */
0, /* IRQ_PINT5 */
0, /* IRQ_CNT */
50, /* RQ_PWM0_TRIP */
50, /* IRQ_PWM0_SYNC */
50, /* IRQ_PWM1_TRIP */
50, /* IRQ_PWM1_SYNC */
0, /* IRQ_TWI0 */
0, /* IRQ_TWI1 */
10, /* IRQ_SOFT0 */
10, /* IRQ_SOFT1 */
10, /* IRQ_SOFT2 */
10, /* IRQ_SOFT3 */
0, /* IRQ_ACM_EVT_MISS */
0, /* IRQ_ACM_EVT_COMPLETE */
0, /* IRQ_CAN0_RX */
0, /* IRQ_CAN0_TX */
0, /* IRQ_CAN0_STAT */
100, /* IRQ_SPORT0_TX */
100, /* IRQ_SPORT0_TX_STAT */
100, /* IRQ_SPORT0_RX */
100, /* IRQ_SPORT0_RX_STAT */
100, /* IRQ_SPORT1_TX */
100, /* IRQ_SPORT1_TX_STAT */
100, /* IRQ_SPORT1_RX */
100, /* IRQ_SPORT1_RX_STAT */
100, /* IRQ_SPORT2_TX */
100, /* IRQ_SPORT2_TX_STAT */
100, /* IRQ_SPORT2_RX */
100, /* IRQ_SPORT2_RX_STAT */
0, /* IRQ_SPI0_TX */
0, /* IRQ_SPI0_RX */
0, /* IRQ_SPI0_STAT */
0, /* IRQ_SPI1_TX */
0, /* IRQ_SPI1_RX */
0, /* IRQ_SPI1_STAT */
0, /* IRQ_RSI */
0, /* IRQ_RSI_INT0 */
0, /* IRQ_RSI_INT1 */
0, /* DMA11 Data (SDU) */
0, /* DMA12 Data (Reserved) */
0, /* Reserved */
0, /* Reserved */
30, /* IRQ_EMAC0_STAT */
0, /* EMAC0 Power (Reserved) */
30, /* IRQ_EMAC1_STAT */
0, /* EMAC1 Power (Reserved) */
0, /* IRQ_LP0 */
0, /* IRQ_LP0_STAT */
0, /* IRQ_LP1 */
0, /* IRQ_LP1_STAT */
0, /* IRQ_LP2 */
0, /* IRQ_LP2_STAT */
0, /* IRQ_LP3 */
0, /* IRQ_LP3_STAT */
0, /* IRQ_UART0_TX */
0, /* IRQ_UART0_RX */
0, /* IRQ_UART0_STAT */
0, /* IRQ_UART1_TX */
0, /* IRQ_UART1_RX */
0, /* IRQ_UART1_STAT */
0, /* IRQ_MDMA0_SRC_CRC0 */
0, /* IRQ_MDMA0_DEST_CRC0 */
0, /* IRQ_CRC0_DCNTEXP */
0, /* IRQ_CRC0_ERR */
0, /* IRQ_MDMA1_SRC_CRC1 */
0, /* IRQ_MDMA1_DEST_CRC1 */
0, /* IRQ_CRC1_DCNTEXP */
0, /* IRQ_CRC1_ERR */
0, /* IRQ_MDMA2_SRC */
0, /* IRQ_MDMA2_DEST */
0, /* IRQ_MDMA3_SRC */
0, /* IRQ_MDMA3_DEST */
120, /* IRQ_EPPI0_CH0 */
120, /* IRQ_EPPI0_CH1 */
120, /* IRQ_EPPI0_STAT */
120, /* IRQ_EPPI2_CH0 */
120, /* IRQ_EPPI2_CH1 */
120, /* IRQ_EPPI2_STAT */
120, /* IRQ_EPPI1_CH0 */
120, /* IRQ_EPPI1_CH1 */
120, /* IRQ_EPPI1_STAT */
120, /* IRQ_PIXC_CH0 */
120, /* IRQ_PIXC_CH1 */
120, /* IRQ_PIXC_CH2 */
120, /* IRQ_PIXC_STAT */
120, /* IRQ_PVP_CPDOB */
120, /* IRQ_PVP_CPDOC */
120, /* IRQ_PVP_CPSTAT */
120, /* IRQ_PVP_CPCI */
120, /* IRQ_PVP_STAT0 */
120, /* IRQ_PVP_MPDO */
120, /* IRQ_PVP_MPDI */
120, /* IRQ_PVP_MPSTAT */
120, /* IRQ_PVP_MPCI */
120, /* IRQ_PVP_CPDOA */
120, /* IRQ_PVP_STAT1 */
0, /* IRQ_USB_STAT */
0, /* IRQ_USB_DMA */
0, /* IRQ_TRU_INT0 */
0, /* IRQ_TRU_INT1 */
0, /* IRQ_TRU_INT2 */
0, /* IRQ_TRU_INT3 */
0, /* IRQ_DMAC0_ERROR */
0, /* IRQ_CGU0_ERROR */
0, /* Reserved */
0, /* IRQ_DPM */
0, /* Reserved */
0, /* IRQ_SWU0 */
0, /* IRQ_SWU1 */
0, /* IRQ_SWU2 */
0, /* IRQ_SWU3 */
0, /* IRQ_SWU4 */
0, /* IRQ_SWU4 */
0, /* IRQ_SWU6 */
};
...@@ -11,13 +11,14 @@ ...@@ -11,13 +11,14 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/syscore_ops.h>
#include <asm/dpmc.h> #include <asm/dpmc.h>
#include <asm/pm.h> #include <asm/pm.h>
#include <mach/pm.h> #include <mach/pm.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/mem_init.h>
/***********************************************************/ /***********************************************************/
/* */ /* */
...@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void) ...@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void)
} }
__attribute__((l1_text)) __attribute__((l1_text))
void bfin_deepsleep(unsigned long mask) void bf609_ddr_sr(void)
{ {
uint32_t dpm0_ctl; dmc_enter_self_refresh();
bfin_write32(DPM0_WAKE_EN, 0x10);
bfin_write32(DPM0_WAKE_POL, 0x10);
dpm0_ctl = 0x00000008;
bfin_write32(DPM0_CTL, dpm0_ctl);
SSYNC();
__asm__ __volatile__( \
".align 8;" \
"idle;" \
: : \
);
#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
__asm__ __volatile__(
"R0 = 0;"
"CYCLES = R0;"
"CYCLES2 = R0;"
"R0 = SYSCFG;"
"BITSET(R0, 1);"
"SYSCFG = R0;"
: : : "R0"
);
#endif
} }
__attribute__((l1_text)) __attribute__((l1_text))
void bf609_ddr_sr(void) void bf609_ddr_sr_exit(void)
{ {
uint32_t reg; dmc_exit_self_refresh();
reg = bfin_read_DMC0_CTL(); /* After wake up from deep sleep and exit DDR from self refress mode,
reg |= 0x8; * should wait till CGU PLL is locked.
bfin_write_DMC0_CTL(reg); */
while (bfin_read32(CGU0_STAT) & CLKSALGN)
while (!(bfin_read_DMC0_STAT() & 0x8))
continue; continue;
} }
__attribute__((l1_text)) __attribute__((l1_text))
void bf609_ddr_sr_exit(void) void bf609_resume_ccbuf(void)
{ {
uint32_t reg; bfin_write32(DPM0_CCBF_EN, 3);
while (!(bfin_read_DMC0_STAT() & 0x1)) bfin_write32(DPM0_CTL, 2);
continue;
reg = bfin_read_DMC0_CTL();
reg &= ~0x8;
bfin_write_DMC0_CTL(reg);
while ((bfin_read_DMC0_STAT() & 0x8)) while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
continue;
} }
__attribute__((l1_text)) __attribute__((l1_text))
...@@ -203,20 +174,25 @@ void bfin_hibernate_syscontrol(void) ...@@ -203,20 +174,25 @@ void bfin_hibernate_syscontrol(void)
bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
} }
#ifndef CONFIG_BF60x #define IRQ_SID(irq) ((irq) - IVG15)
# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) asmlinkage void enter_deepsleep(void);
#else
# define SIC_SYSIRQ(irq) ((irq) - IVG15) __attribute__((l1_text))
#endif void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
void bfin_hibernate(unsigned long mask) {
bfin_write32(DPM0_WAKE_EN, mask);
bfin_write32(DPM0_WAKE_POL, pol_mask);
SSYNC();
enter_deepsleep();
}
void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
{ {
bfin_write32(DPM0_WAKE_EN, 0x10); bfin_write32(DPM0_WAKE_EN, mask);
bfin_write32(DPM0_WAKE_POL, 0x10); bfin_write32(DPM0_WAKE_POL, pol_mask);
bfin_write32(DPM0_PGCNTR, 0x0000FFFF); bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
bfin_write32(DPM0_HIB_DIS, 0xFFFF); bfin_write32(DPM0_HIB_DIS, 0xFFFF);
printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
bf609_hibernate(); bf609_hibernate();
} }
...@@ -290,10 +266,11 @@ void bf609_cpu_pm_enter(suspend_state_t state) ...@@ -290,10 +266,11 @@ void bf609_cpu_pm_enter(suspend_state_t state)
printk(KERN_DEBUG "Unable to get irq wake\n"); printk(KERN_DEBUG "Unable to get irq wake\n");
if (state == PM_SUSPEND_STANDBY) if (state == PM_SUSPEND_STANDBY)
bfin_deepsleep(wakeup); bfin_deepsleep(wakeup, wakeup_pol);
else { else {
bfin_hibernate(wakeup); bfin_hibernate(wakeup, wakeup_pol);
} }
} }
int bf609_cpu_pm_prepare(void) int bf609_cpu_pm_prepare(void)
...@@ -312,20 +289,36 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = { ...@@ -312,20 +289,36 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = {
.finish = bf609_cpu_pm_finish, .finish = bf609_cpu_pm_finish,
}; };
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static int smc_pm_syscore_suspend(void)
{
bf609_nor_flash_exit();
return 0;
}
static void smc_pm_syscore_resume(void)
{
bf609_nor_flash_init();
}
static struct syscore_ops smc_pm_syscore_ops = {
.suspend = smc_pm_syscore_suspend,
.resume = smc_pm_syscore_resume,
};
#endif
static irqreturn_t test_isr(int irq, void *dev_id) static irqreturn_t test_isr(int irq, void *dev_id)
{ {
printk(KERN_DEBUG "gpio irq %d\n", irq); printk(KERN_DEBUG "gpio irq %d\n", irq);
if (irq == 231)
bfin_sec_raise_irq(IRQ_SID(IRQ_SOFT1));
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static irqreturn_t dpm0_isr(int irq, void *dev_id) static irqreturn_t dpm0_isr(int irq, void *dev_id)
{ {
uint32_t wake_stat; bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
wake_stat = bfin_read32(DPM0_WAKE_STAT);
printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
bfin_write32(DPM0_WAKE_STAT, wake_stat);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -334,7 +327,11 @@ static int __init bf609_init_pm(void) ...@@ -334,7 +327,11 @@ static int __init bf609_init_pm(void)
int irq; int irq;
int error; int error;
#if CONFIG_PM_BFIN_WAKE_PE12 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
register_syscore_ops(&smc_pm_syscore_ops);
#endif
#ifdef CONFIG_PM_BFIN_WAKE_PE12
irq = gpio_to_irq(GPIO_PE12); irq = gpio_to_irq(GPIO_PE12);
if (irq < 0) { if (irq < 0) {
error = irq; error = irq;
...@@ -342,16 +339,19 @@ static int __init bf609_init_pm(void) ...@@ -342,16 +339,19 @@ static int __init bf609_init_pm(void)
GPIO_PE12, error); GPIO_PE12, error);
} }
error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL); error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
| IRQF_FORCE_RESUME, "gpiope12", NULL);
if(error < 0) if(error < 0)
printk(KERN_DEBUG "Unable to get irq\n"); printk(KERN_DEBUG "Unable to get irq\n");
#endif #endif
error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL); error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
IRQF_FORCE_RESUME, "cgu0 event", NULL);
if(error < 0) if(error < 0)
printk(KERN_DEBUG "Unable to get irq\n"); printk(KERN_DEBUG "Unable to get irq\n");
error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL); error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
IRQF_FORCE_RESUME, "dpm0 event", NULL);
if (error < 0) if (error < 0)
printk(KERN_DEBUG "Unable to get irq\n"); printk(KERN_DEBUG "Unable to get irq\n");
......
...@@ -16,23 +16,14 @@ ...@@ -16,23 +16,14 @@
#include <asm/dpmc.h> #include <asm/dpmc.h>
#ifdef CONFIG_BF60x #ifdef CONFIG_BF60x
#define CSEL_P 0
#define S0SEL_P 5
#define SYSSEL_P 8
#define S1SEL_P 13
#define DSEL_P 16
#define OSEL_P 22
#define ALGN_P 29
#define UPDT_P 30
#define LOCK_P 31
#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
#define CGU_DIV_VAL \ #define CGU_DIV_VAL \
((CONFIG_CCLK_DIV << CSEL_P) | \ ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
(CONFIG_SCLK_DIV << SYSSEL_P) | \ (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
(CONFIG_SCLK0_DIV << S0SEL_P) | \ (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
(CONFIG_SCLK1_DIV << S1SEL_P) | \ (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
(CONFIG_DCLK_DIV << DSEL_P)) (CONFIG_DCLK_DIV << DSEL_OFFSET))
#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
#if ((CONFIG_BFIN_DCLK != 125) && \ #if ((CONFIG_BFIN_DCLK != 125) && \
...@@ -41,89 +32,7 @@ ...@@ -41,89 +32,7 @@
(CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
#endif #endif
struct ddr_config {
u32 ddr_clk;
u32 dmc_ddrctl;
u32 dmc_ddrcfg;
u32 dmc_ddrtr0;
u32 dmc_ddrtr1;
u32 dmc_ddrtr2;
u32 dmc_ddrmr;
u32 dmc_ddrmr1;
};
struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
[0] = {
.ddr_clk = 125,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20705212,
.dmc_ddrtr1 = 0x201003CF,
.dmc_ddrtr2 = 0x00320107,
.dmc_ddrmr = 0x00000422,
.dmc_ddrmr1 = 0x4,
},
[1] = {
.ddr_clk = 133,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20806313,
.dmc_ddrtr1 = 0x2013040D,
.dmc_ddrtr2 = 0x00320108,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[2] = {
.ddr_clk = 150,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20A07323,
.dmc_ddrtr1 = 0x20160492,
.dmc_ddrtr2 = 0x00320209,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[3] = {
.ddr_clk = 166,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20A07323,
.dmc_ddrtr1 = 0x2016050E,
.dmc_ddrtr2 = 0x00320209,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[4] = {
.ddr_clk = 200,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20a07323,
.dmc_ddrtr1 = 0x2016050f,
.dmc_ddrtr2 = 0x00320509,
.dmc_ddrmr = 0x00000632,
.dmc_ddrmr1 = 0x4,
},
[5] = {
.ddr_clk = 225,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20E0A424,
.dmc_ddrtr1 = 0x302006DB,
.dmc_ddrtr2 = 0x0032020D,
.dmc_ddrmr = 0x00000842,
.dmc_ddrmr1 = 0x4,
},
[6] = {
.ddr_clk = 250,
.dmc_ddrctl = 0x00000904,
.dmc_ddrcfg = 0x00000422,
.dmc_ddrtr0 = 0x20E0A424,
.dmc_ddrtr1 = 0x3020079E,
.dmc_ddrtr2 = 0x0032020D,
.dmc_ddrmr = 0x00000842,
.dmc_ddrmr1 = 0x4,
},
};
#else #else
#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
#define PLL_CTL_VAL \ #define PLL_CTL_VAL \
...@@ -144,43 +53,9 @@ void init_clocks(void) ...@@ -144,43 +53,9 @@ void init_clocks(void)
* in the middle of reprogramming things, and that'll screw us up. * in the middle of reprogramming things, and that'll screw us up.
* For example, any automatic DMAs left by U-Boot for splash screens. * For example, any automatic DMAs left by U-Boot for splash screens.
*/ */
#ifdef CONFIG_BF60x #ifdef CONFIG_BF60x
int i, dlldatacycle, dll_ctl; init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
bfin_write32(CGU0_DIV, CGU_DIV_VAL); init_dmc(CONFIG_BFIN_DCLK);
bfin_write32(CGU0_CTL, CGU_CTL_VAL);
while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
continue;
bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
while (bfin_read32(CGU0_STAT) & (1 << 3))
continue;
for (i = 0; i < 7; i++) {
if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
break;
}
}
do_sync();
while (!(bfin_read_DDR0_STAT() & 0x4))
continue;
dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
dll_ctl = bfin_read_DDR0_DLLCTL();
dll_ctl &= 0x0ff;
bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
do_sync();
while (!(bfin_read_DDR0_STAT() & 0x2000))
continue;
#else #else
size_t i; size_t i;
for (i = 0; i < MAX_DMA_CHANNELS; ++i) { for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
......
...@@ -64,7 +64,8 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) ...@@ -64,7 +64,8 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
/* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
#if ANOMALY_05000273 || ANOMALY_05000274 || \ #if ANOMALY_05000273 || ANOMALY_05000274 || \
(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
&& defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
min_cclk = sclk * 2; min_cclk = sclk * 2;
#else #else
min_cclk = sclk; min_cclk = sclk;
...@@ -173,7 +174,7 @@ static int bfin_target(struct cpufreq_policy *poli, ...@@ -173,7 +174,7 @@ static int bfin_target(struct cpufreq_policy *poli,
#else #else
ret = cpu_set_cclk(cpu, freqs.new * 1000); ret = cpu_set_cclk(cpu, freqs.new * 1000);
if (ret != 0) { if (ret != 0) {
pr_debug("cpufreq set freq failed %d\n", ret); WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
break; break;
} }
#endif #endif
......
...@@ -25,13 +25,6 @@ ...@@ -25,13 +25,6 @@
#include <asm/context.S> #include <asm/context.S>
#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
# define EX_SCRATCH_REG RETN
#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
# define EX_SCRATCH_REG RETE
#else
# define EX_SCRATCH_REG CYCLES
#endif
#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
.section .l1.text .section .l1.text
......
This diff is collapsed.
...@@ -172,6 +172,10 @@ int bfin_pm_suspend_mem_enter(void) ...@@ -172,6 +172,10 @@ int bfin_pm_suspend_mem_enter(void)
bfin_gpio_pm_hibernate_suspend(); bfin_gpio_pm_hibernate_suspend();
#if BFIN_GPIO_PINT
bfin_pint_suspend();
#endif
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
flushinv_all_dcache(); flushinv_all_dcache();
#endif #endif
...@@ -190,6 +194,10 @@ int bfin_pm_suspend_mem_enter(void) ...@@ -190,6 +194,10 @@ int bfin_pm_suspend_mem_enter(void)
_enable_icplb(); _enable_icplb();
_enable_dcplb(); _enable_dcplb();
#if BFIN_GPIO_PINT
bfin_pint_resume();
#endif
bfin_gpio_pm_hibernate_restore(); bfin_gpio_pm_hibernate_restore();
blackfin_dma_resume(); blackfin_dma_resume();
......
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