Commit 75dee3b6 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'mailbox-v5.9' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:
 "mediatek:
   - add support for mt6779 gce
   - shutdown cleanup and address shift support

  qcom:
   - add msm8994 apcs and sdm660 hmss compatibility

  imx:
   - mark PM funcs __maybe

  pcc:
   - put acpi table before bailout

  misc:
   - replace http with https links"

* tag 'mailbox-v5.9' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: mediatek: cmdq: clear task in channel before shutdown
  mailbox: cmdq: support mt6779 gce platform definition
  mailbox: cmdq: variablize address shift in platform
  dt-binding: gce: add gce header file for mt6779
  mailbox: qcom: Add msm8994 apcs compatible
  mailbox: qcom: Add sdm660 hmss compatible
  mailbox: imx: Mark PM functions as __maybe_unused
  mailbox: pcc: Put the PCCT table for error path
  mailbox: Replace HTTP links with HTTPS ones
parents ce615f5c 88499698
...@@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to ...@@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to
mailbox.txt for generic information about mailbox device-tree bindings. mailbox.txt for generic information about mailbox device-tree bindings.
Required properties: Required properties:
- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce" - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
"mediatek,mt6779-gce".
- reg: Address range of the GCE unit - reg: Address range of the GCE unit
- interrupts: The interrupt signal from the GCE block - interrupts: The interrupt signal from the GCE block
- clock: Clocks according to the common clock binding - clock: Clocks according to the common clock binding
...@@ -34,8 +35,9 @@ Optional properties for a client device: ...@@ -34,8 +35,9 @@ Optional properties for a client device:
start_offset: the start offset of register address that GCE can access. start_offset: the start offset of register address that GCE can access.
size: the total size of register address that GCE can access. size: the total size of register address that GCE can access.
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. 'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
sub-system ids, thread priority, event ids.
Example: Example:
......
...@@ -18,10 +18,12 @@ properties: ...@@ -18,10 +18,12 @@ properties:
enum: enum:
- qcom,ipq8074-apcs-apps-global - qcom,ipq8074-apcs-apps-global
- qcom,msm8916-apcs-kpss-global - qcom,msm8916-apcs-kpss-global
- qcom,msm8994-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global - qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global - qcom,msm8998-apcs-hmss-global
- qcom,qcs404-apcs-apps-global - qcom,qcs404-apcs-apps-global
- qcom,sc7180-apss-shared - qcom,sc7180-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared - qcom,sdm845-apss-shared
- qcom,sm8150-apss-shared - qcom,sm8150-apss-shared
......
...@@ -598,7 +598,7 @@ static const struct of_device_id imx_mu_dt_ids[] = { ...@@ -598,7 +598,7 @@ static const struct of_device_id imx_mu_dt_ids[] = {
}; };
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
static int imx_mu_suspend_noirq(struct device *dev) static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
{ {
struct imx_mu_priv *priv = dev_get_drvdata(dev); struct imx_mu_priv *priv = dev_get_drvdata(dev);
...@@ -608,7 +608,7 @@ static int imx_mu_suspend_noirq(struct device *dev) ...@@ -608,7 +608,7 @@ static int imx_mu_suspend_noirq(struct device *dev)
return 0; return 0;
} }
static int imx_mu_resume_noirq(struct device *dev) static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
{ {
struct imx_mu_priv *priv = dev_get_drvdata(dev); struct imx_mu_priv *priv = dev_get_drvdata(dev);
...@@ -626,7 +626,7 @@ static int imx_mu_resume_noirq(struct device *dev) ...@@ -626,7 +626,7 @@ static int imx_mu_resume_noirq(struct device *dev)
return 0; return 0;
} }
static int imx_mu_runtime_suspend(struct device *dev) static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
{ {
struct imx_mu_priv *priv = dev_get_drvdata(dev); struct imx_mu_priv *priv = dev_get_drvdata(dev);
...@@ -635,7 +635,7 @@ static int imx_mu_runtime_suspend(struct device *dev) ...@@ -635,7 +635,7 @@ static int imx_mu_runtime_suspend(struct device *dev)
return 0; return 0;
} }
static int imx_mu_runtime_resume(struct device *dev) static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
{ {
struct imx_mu_priv *priv = dev_get_drvdata(dev); struct imx_mu_priv *priv = dev_get_drvdata(dev);
int ret; int ret;
......
...@@ -75,8 +75,22 @@ struct cmdq { ...@@ -75,8 +75,22 @@ struct cmdq {
struct cmdq_thread *thread; struct cmdq_thread *thread;
struct clk *clock; struct clk *clock;
bool suspended; bool suspended;
u8 shift_pa;
}; };
struct gce_plat {
u32 thread_nr;
u8 shift;
};
u8 cmdq_get_shift_pa(struct mbox_chan *chan)
{
struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
return cmdq->shift_pa;
}
EXPORT_SYMBOL(cmdq_get_shift_pa);
static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
{ {
u32 status; u32 status;
...@@ -183,13 +197,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task) ...@@ -183,13 +197,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
{ {
struct cmdq_thread *thread = task->thread; struct cmdq_thread *thread = task->thread;
struct cmdq_task *next_task; struct cmdq_task *next_task;
struct cmdq *cmdq = task->cmdq;
dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task); dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0); WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
next_task = list_first_entry_or_null(&thread->task_busy_list, next_task = list_first_entry_or_null(&thread->task_busy_list,
struct cmdq_task, list_entry); struct cmdq_task, list_entry);
if (next_task) if (next_task)
writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); writel(next_task->pa_base >> cmdq->shift_pa,
thread->base + CMDQ_THR_CURR_ADDR);
cmdq_thread_resume(thread); cmdq_thread_resume(thread);
} }
...@@ -219,7 +235,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, ...@@ -219,7 +235,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
else else
return; return;
curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
list_for_each_entry_safe(task, tmp, &thread->task_busy_list, list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
list_entry) { list_entry) {
...@@ -333,29 +349,39 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) ...@@ -333,29 +349,39 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
if (list_empty(&thread->task_busy_list)) { if (list_empty(&thread->task_busy_list)) {
WARN_ON(clk_enable(cmdq->clock) < 0); WARN_ON(clk_enable(cmdq->clock) < 0);
/*
* The thread reset will clear thread related register to 0,
* including pc, end, priority, irq, suspend and enable. Thus
* set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
* thread and make it running.
*/
WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); writel(task->pa_base >> cmdq->shift_pa,
writel(task->pa_base + pkt->cmd_buf_size, thread->base + CMDQ_THR_CURR_ADDR);
writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
thread->base + CMDQ_THR_END_ADDR); thread->base + CMDQ_THR_END_ADDR);
writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
} else { } else {
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
end_pa = readl(thread->base + CMDQ_THR_END_ADDR); cmdq->shift_pa;
end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
cmdq->shift_pa;
/* check boundary */ /* check boundary */
if (curr_pa == end_pa - CMDQ_INST_SIZE || if (curr_pa == end_pa - CMDQ_INST_SIZE ||
curr_pa == end_pa) { curr_pa == end_pa) {
/* set to this task directly */ /* set to this task directly */
writel(task->pa_base, writel(task->pa_base >> cmdq->shift_pa,
thread->base + CMDQ_THR_CURR_ADDR); thread->base + CMDQ_THR_CURR_ADDR);
} else { } else {
cmdq_task_insert_into_thread(task); cmdq_task_insert_into_thread(task);
smp_mb(); /* modify jump before enable thread */ smp_mb(); /* modify jump before enable thread */
} }
writel(task->pa_base + pkt->cmd_buf_size, writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
thread->base + CMDQ_THR_END_ADDR); thread->base + CMDQ_THR_END_ADDR);
cmdq_thread_resume(thread); cmdq_thread_resume(thread);
} }
...@@ -371,6 +397,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan) ...@@ -371,6 +397,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)
static void cmdq_mbox_shutdown(struct mbox_chan *chan) static void cmdq_mbox_shutdown(struct mbox_chan *chan)
{ {
struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
struct cmdq_task *task, *tmp;
unsigned long flags;
spin_lock_irqsave(&thread->chan->lock, flags);
if (list_empty(&thread->task_busy_list))
goto done;
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
/* make sure executed tasks have success callback */
cmdq_thread_irq_handler(cmdq, thread);
if (list_empty(&thread->task_busy_list))
goto done;
list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
list_entry) {
cmdq_task_exec_done(task, CMDQ_CB_ERROR);
kfree(task);
}
cmdq_thread_disable(cmdq, thread);
clk_disable(cmdq->clock);
done:
/*
* The thread->task_busy_list empty means thread already disable. The
* cmdq_mbox_send_data() always reset thread which clear disable and
* suspend statue when first pkt send to channel, so there is no need
* to do any operation here, only unlock and leave.
*/
spin_unlock_irqrestore(&thread->chan->lock, flags);
} }
static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
...@@ -453,6 +511,7 @@ static int cmdq_probe(struct platform_device *pdev) ...@@ -453,6 +511,7 @@ static int cmdq_probe(struct platform_device *pdev)
struct resource *res; struct resource *res;
struct cmdq *cmdq; struct cmdq *cmdq;
int err, i; int err, i;
struct gce_plat *plat_data;
cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
if (!cmdq) if (!cmdq)
...@@ -471,7 +530,14 @@ static int cmdq_probe(struct platform_device *pdev) ...@@ -471,7 +530,14 @@ static int cmdq_probe(struct platform_device *pdev)
return -EINVAL; return -EINVAL;
} }
cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev); plat_data = (struct gce_plat *)of_device_get_match_data(dev);
if (!plat_data) {
dev_err(dev, "failed to get match data\n");
return -EINVAL;
}
cmdq->thread_nr = plat_data->thread_nr;
cmdq->shift_pa = plat_data->shift;
cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
"mtk_cmdq", cmdq); "mtk_cmdq", cmdq);
...@@ -534,9 +600,14 @@ static const struct dev_pm_ops cmdq_pm_ops = { ...@@ -534,9 +600,14 @@ static const struct dev_pm_ops cmdq_pm_ops = {
.resume = cmdq_resume, .resume = cmdq_resume,
}; };
static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
static const struct of_device_id cmdq_of_ids[] = { static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)16}, {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
{.compatible = "mediatek,mt8183-gce", .data = (void *)24}, {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
{} {}
}; };
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* OMAP mailbox driver * OMAP mailbox driver
* *
* Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
* Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com * Copyright (C) 2013-2019 Texas Instruments Incorporated - https://www.ti.com
* *
* Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
* Suman Anna <s-anna@ti.com> * Suman Anna <s-anna@ti.com>
......
...@@ -457,14 +457,17 @@ static int __init acpi_pcc_probe(void) ...@@ -457,14 +457,17 @@ static int __init acpi_pcc_probe(void)
pr_warn("Error parsing PCC subspaces from PCCT\n"); pr_warn("Error parsing PCC subspaces from PCCT\n");
else else
pr_warn("Invalid PCCT: %d PCC subspaces\n", count); pr_warn("Invalid PCCT: %d PCC subspaces\n", count);
return -EINVAL;
rc = -EINVAL;
goto err_put_pcct;
} }
pcc_mbox_channels = kcalloc(count, sizeof(struct mbox_chan), pcc_mbox_channels = kcalloc(count, sizeof(struct mbox_chan),
GFP_KERNEL); GFP_KERNEL);
if (!pcc_mbox_channels) { if (!pcc_mbox_channels) {
pr_err("Could not allocate space for PCC mbox channels\n"); pr_err("Could not allocate space for PCC mbox channels\n");
return -ENOMEM; rc = -ENOMEM;
goto err_put_pcct;
} }
pcc_doorbell_vaddr = kcalloc(count, sizeof(void *), GFP_KERNEL); pcc_doorbell_vaddr = kcalloc(count, sizeof(void *), GFP_KERNEL);
...@@ -535,6 +538,8 @@ static int __init acpi_pcc_probe(void) ...@@ -535,6 +538,8 @@ static int __init acpi_pcc_probe(void)
kfree(pcc_doorbell_vaddr); kfree(pcc_doorbell_vaddr);
err_free_mbox: err_free_mbox:
kfree(pcc_mbox_channels); kfree(pcc_mbox_channels);
err_put_pcct:
acpi_put_table(pcct_tbl);
return rc; return rc;
} }
......
...@@ -41,6 +41,10 @@ static const struct qcom_apcs_ipc_data msm8916_apcs_data = { ...@@ -41,6 +41,10 @@ static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
.offset = 8, .clk_name = "qcom-apcs-msm8916-clk" .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
}; };
static const struct qcom_apcs_ipc_data msm8994_apcs_data = {
.offset = 8, .clk_name = NULL
};
static const struct qcom_apcs_ipc_data msm8996_apcs_data = { static const struct qcom_apcs_ipc_data msm8996_apcs_data = {
.offset = 16, .clk_name = NULL .offset = 16, .clk_name = NULL
}; };
...@@ -49,6 +53,10 @@ static const struct qcom_apcs_ipc_data msm8998_apcs_data = { ...@@ -49,6 +53,10 @@ static const struct qcom_apcs_ipc_data msm8998_apcs_data = {
.offset = 8, .clk_name = NULL .offset = 8, .clk_name = NULL
}; };
static const struct qcom_apcs_ipc_data sdm660_apcs_data = {
.offset = 8, .clk_name = NULL
};
static const struct qcom_apcs_ipc_data apps_shared_apcs_data = { static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
.offset = 12, .clk_name = NULL .offset = 12, .clk_name = NULL
}; };
...@@ -146,10 +154,12 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { ...@@ -146,10 +154,12 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8994-apcs-kpss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data }, { .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data },
{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data }, { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data },
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data },
{ .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
{} {}
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* Texas Instruments' Message Manager Driver * Texas Instruments' Message Manager Driver
* *
* Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon * Nishanth Menon
*/ */
......
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
*/
#ifndef _DT_BINDINGS_GCE_MT6779_H
#define _DT_BINDINGS_GCE_MT6779_H
#define CMDQ_NO_TIMEOUT 0xffffffff
/* GCE HW thread priority */
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_1 1
#define CMDQ_THR_PRIO_2 2
#define CMDQ_THR_PRIO_3 3
#define CMDQ_THR_PRIO_4 4
#define CMDQ_THR_PRIO_5 5
#define CMDQ_THR_PRIO_6 6
#define CMDQ_THR_PRIO_HIGHEST 7
/* GCE subsys table */
#define SUBSYS_1300XXXX 0
#define SUBSYS_1400XXXX 1
#define SUBSYS_1401XXXX 2
#define SUBSYS_1402XXXX 3
#define SUBSYS_1502XXXX 4
#define SUBSYS_1880XXXX 5
#define SUBSYS_1881XXXX 6
#define SUBSYS_1882XXXX 7
#define SUBSYS_1883XXXX 8
#define SUBSYS_1884XXXX 9
#define SUBSYS_1000XXXX 10
#define SUBSYS_1001XXXX 11
#define SUBSYS_1002XXXX 12
#define SUBSYS_1003XXXX 13
#define SUBSYS_1004XXXX 14
#define SUBSYS_1005XXXX 15
#define SUBSYS_1020XXXX 16
#define SUBSYS_1028XXXX 17
#define SUBSYS_1700XXXX 18
#define SUBSYS_1701XXXX 19
#define SUBSYS_1702XXXX 20
#define SUBSYS_1703XXXX 21
#define SUBSYS_1800XXXX 22
#define SUBSYS_1801XXXX 23
#define SUBSYS_1802XXXX 24
#define SUBSYS_1804XXXX 25
#define SUBSYS_1805XXXX 26
#define SUBSYS_1808XXXX 27
#define SUBSYS_180aXXXX 28
#define SUBSYS_180bXXXX 29
#define CMDQ_SUBSYS_OFF 32
/* GCE hardware events */
#define CMDQ_EVENT_DISP_RDMA0_SOF 0
#define CMDQ_EVENT_DISP_RDMA1_SOF 1
#define CMDQ_EVENT_MDP_RDMA0_SOF 2
#define CMDQ_EVENT_MDP_RDMA1_SOF 3
#define CMDQ_EVENT_MDP_RSZ0_SOF 4
#define CMDQ_EVENT_MDP_RSZ1_SOF 5
#define CMDQ_EVENT_MDP_TDSHP_SOF 6
#define CMDQ_EVENT_MDP_WROT0_SOF 7
#define CMDQ_EVENT_MDP_WROT1_SOF 8
#define CMDQ_EVENT_DISP_OVL0_SOF 9
#define CMDQ_EVENT_DISP_2L_OVL0_SOF 10
#define CMDQ_EVENT_DISP_2L_OVL1_SOF 11
#define CMDQ_EVENT_DISP_WDMA0_SOF 12
#define CMDQ_EVENT_DISP_COLOR0_SOF 13
#define CMDQ_EVENT_DISP_CCORR0_SOF 14
#define CMDQ_EVENT_DISP_AAL0_SOF 15
#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
#define CMDQ_EVENT_DISP_DITHER0_SOF 17
#define CMDQ_EVENT_DISP_PWM0_SOF 18
#define CMDQ_EVENT_DISP_DSI0_SOF 19
#define CMDQ_EVENT_DISP_DPI0_SOF 20
#define CMDQ_EVENT_DISP_POSTMASK0_SOF 21
#define CMDQ_EVENT_DISP_RSZ0_SOF 22
#define CMDQ_EVENT_MDP_AAL_SOF 23
#define CMDQ_EVENT_MDP_CCORR_SOF 24
#define CMDQ_EVENT_DISP_DBI0_SOF 25
#define CMDQ_EVENT_ISP_RELAY_SOF 26
#define CMDQ_EVENT_IPU_RELAY_SOF 27
#define CMDQ_EVENT_DISP_RDMA0_EOF 28
#define CMDQ_EVENT_DISP_RDMA1_EOF 29
#define CMDQ_EVENT_MDP_RDMA0_EOF 30
#define CMDQ_EVENT_MDP_RDMA1_EOF 31
#define CMDQ_EVENT_MDP_RSZ0_EOF 32
#define CMDQ_EVENT_MDP_RSZ1_EOF 33
#define CMDQ_EVENT_MDP_TDSHP_EOF 34
#define CMDQ_EVENT_MDP_WROT0_W_EOF 35
#define CMDQ_EVENT_MDP_WROT1_W_EOF 36
#define CMDQ_EVENT_DISP_OVL0_EOF 37
#define CMDQ_EVENT_DISP_2L_OVL0_EOF 38
#define CMDQ_EVENT_DISP_2L_OVL1_EOF 39
#define CMDQ_EVENT_DISP_WDMA0_EOF 40
#define CMDQ_EVENT_DISP_COLOR0_EOF 41
#define CMDQ_EVENT_DISP_CCORR0_EOF 42
#define CMDQ_EVENT_DISP_AAL0_EOF 43
#define CMDQ_EVENT_DISP_GAMMA0_EOF 44
#define CMDQ_EVENT_DISP_DITHER0_EOF 45
#define CMDQ_EVENT_DISP_DSI0_EOF 46
#define CMDQ_EVENT_DISP_DPI0_EOF 47
#define CMDQ_EVENT_DISP_RSZ0_EOF 49
#define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50
#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51
#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52
#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
#define CMDQ_EVENT_MUTEX10_STREAM_EOF 140
#define CMDQ_EVENT_MUTEX11_STREAM_EOF 141
#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142
#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143
#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144
#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145
#define CMDQ_EVENT_DSI0_TE 146
#define CMDQ_EVENT_DSI0_IRQ_EVENT 147
#define CMDQ_EVENT_DSI0_DONE_EVENT 148
#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150
#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151
#define CMDQ_EVENT_MDP_WROT0_RST_DONE 153
#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154
#define CMDQ_EVENT_DISP_OVL0_RST_DONE 155
#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156
#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157
#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
#define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276
#define CMDQ_EVENT_AMD_FRAME_DONE 277
#define CMDQ_EVENT_MFB_DONE 278
#define CMDQ_EVENT_WPE_A_EOF 279
#define CMDQ_EVENT_VENC_EOF 289
#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290
#define CMDQ_EVENT_JPEG_ENC_EOF 291
#define CMDQ_EVENT_VENC_MB_DONE 292
#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
#define CMDQ_EVENT_ISP_FRAME_DONE_C 323
#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324
#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325
#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326
#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327
#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328
#define CMDQ_EVENT_ISP_TSF_DONE 329
#define CMDQ_EVENT_SENINF_0_FIFO_FULL 330
#define CMDQ_EVENT_SENINF_1_FIFO_FULL 331
#define CMDQ_EVENT_SENINF_2_FIFO_FULL 332
#define CMDQ_EVENT_SENINF_3_FIFO_FULL 333
#define CMDQ_EVENT_SENINF_4_FIFO_FULL 334
#define CMDQ_EVENT_SENINF_5_FIFO_FULL 335
#define CMDQ_EVENT_SENINF_6_FIFO_FULL 336
#define CMDQ_EVENT_SENINF_7_FIFO_FULL 337
#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338
#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339
#define CMDQ_EVENT_TG_OVRUN_C_INT 340
#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341
#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342
#define CMDQ_EVENT_TG_GRABERR_C_INT 343
#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344
#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345
#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346
#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347
#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348
#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349
#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353
#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354
#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355
#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356
#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385
#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386
#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387
#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388
#define CMDQ_EVENT_VDEC_EVENT_0 416
#define CMDQ_EVENT_VDEC_EVENT_1 417
#define CMDQ_EVENT_VDEC_EVENT_2 418
#define CMDQ_EVENT_VDEC_EVENT_3 419
#define CMDQ_EVENT_VDEC_EVENT_4 420
#define CMDQ_EVENT_VDEC_EVENT_5 421
#define CMDQ_EVENT_VDEC_EVENT_6 422
#define CMDQ_EVENT_VDEC_EVENT_7 423
#define CMDQ_EVENT_VDEC_EVENT_8 424
#define CMDQ_EVENT_VDEC_EVENT_9 425
#define CMDQ_EVENT_VDEC_EVENT_10 426
#define CMDQ_EVENT_VDEC_EVENT_11 427
#define CMDQ_EVENT_VDEC_EVENT_12 428
#define CMDQ_EVENT_VDEC_EVENT_13 429
#define CMDQ_EVENT_VDEC_EVENT_14 430
#define CMDQ_EVENT_VDEC_EVENT_15 431
#define CMDQ_EVENT_FDVT_DONE 449
#define CMDQ_EVENT_FE_DONE 450
#define CMDQ_EVENT_RSC_EOF 451
#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452
#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453
#define CMDQ_EVENT_DSI0_TE_INFRA 898
#endif
...@@ -90,4 +90,6 @@ struct cmdq_pkt { ...@@ -90,4 +90,6 @@ struct cmdq_pkt {
void *cl; void *cl;
}; };
u8 cmdq_get_shift_pa(struct mbox_chan *chan);
#endif /* __MTK_CMDQ_MAILBOX_H__ */ #endif /* __MTK_CMDQ_MAILBOX_H__ */
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