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Commit 77ecfe8d authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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Merge commit 'gcl/next' into next

parents 8d73f102 a7e1cf0c
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arch/powerpc/boot/dts/pcm032.dts 0 → 100644
View file @ 77ecfe8d
/*
* phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
*
* Copyright (C) 2006-2009 Pengutronix
* Sascha Hauer <s.hauer@pengutronix.de>
* Juergen Beisert <j.beisert@pengutronix.de>
* Wolfram Sang <w.sang@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "phytec,pcm032";
compatible = "phytec,pcm032";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
gpio-controller;
#gpio-cells = <2>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
};
can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 17 0>;
reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 18 0>;
reg = <0x980 0x80>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
ac97@2000 { /* PSC1 is ac97 */
compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
cell-index = <0>;
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
};
/* PSC2 port is used by CAN1/2 */
serial@2400 { /* PSC3 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
cell-index = <2>;
reg = <0x2400 0x100>;
interrupts = <2 3 0>;
};
/* PSC4 is ??? */
/* PSC5 is ??? */
serial@2c00 { /* PSC6 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
cell-index = <5>;
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
};
ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
eeprom@52 {
compatible = "at24,24c32";
reg = <0x52>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
0xc000 0 0 2 &mpc5200_pic 1 1 3
0xc000 0 0 3 &mpc5200_pic 1 2 3
0xc000 0 0 4 &mpc5200_pic 1 3 3
0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
0xc800 0 0 2 &mpc5200_pic 1 2 3
0xc800 0 0 3 &mpc5200_pic 1 3 3
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
localbus {
compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xfe000000 0x02000000
1 0 0xfc000000 0x02000000
2 0 0xfbe00000 0x00200000
3 0 0xf9e00000 0x02000000
4 0 0xf7e00000 0x02000000
5 0 0xe6000000 0x02000000
6 0 0xe8000000 0x02000000
7 0 0xea000000 0x02000000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
bank-width = <4>;
#size-cells = <1>;
#address-cells = <1>;
partition@0 {
label = "ubootl";
reg = <0x00000000 0x00040000>;
};
partition@40000 {
label = "kernel";
reg = <0x00040000 0x001c0000>;
};
partition@200000 {
label = "jffs2";
reg = <0x00200000 0x01d00000>;
};
partition@1f00000 {
label = "uboot";
reg = <0x01f00000 0x00040000>;
};
partition@1f40000 {
label = "env";
reg = <0x01f40000 0x00040000>;
};
partition@1f80000 {
label = "oftree";
reg = <0x01f80000 0x00040000>;
};
partition@1fc0000 {
label = "space";
reg = <0x01fc0000 0x00040000>;
};
};
sram@2,0 {
compatible = "mtd-ram";
reg = <2 0 0x00200000>;
bank-width = <2>;
};
/*
* example snippets for FPGA
*
* fpga@3,0 {
* compatible = "fpga_driver";
* reg = <3 0 0x02000000>;
* bank-width = <4>;
* };
*
* fpga@4,0 {
* compatible = "fpga_driver";
* reg = <4 0 0x02000000>;
* bank-width = <4>;
* };
*/
/*
* example snippets for free chipselects
*
* device@5,0 {
* compatible = "custom_driver";
* reg = <5 0 0x02000000>;
* };
*
* device@6,0 {
* compatible = "custom_driver";
* reg = <6 0 0x02000000>;
* };
*
* device@7,0 {
* compatible = "custom_driver";
* reg = <7 0 0x02000000>;
* };
*/
};
};
arch/powerpc/boot/wrapper
View file @ 77ecfe8d
......@@ -214,11 +214,11 @@ simpleboot-virtex405-*)
binary=y
;;
simpleboot-virtex440-*)
platformo="$object/simpleboot.o $object/virtex.o"
platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
binary=y
;;
simpleboot-*)
platformo="$object/simpleboot.o"
platformo="$object/fixed-head.o $object/simpleboot.o"
binary=y
;;
asp834x-redboot)
......
arch/powerpc/include/asm/mpc52xx.h
View file @ 77ecfe8d
......@@ -273,6 +273,7 @@ extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
extern void mpc52xx_map_common_devices(void);
extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
extern void mpc52xx_restart(char *cmd);
/* mpc52xx_pic.c */
......
arch/powerpc/platforms/52xx/Kconfig
View file @ 77ecfe8d
......@@ -24,6 +24,7 @@ config PPC_MPC5200_SIMPLE
are:
intercontrol,digsy-mtc
phytec,pcm030
phytec,pcm032
promess,motionpro
schindler,cm5200
tqc,tqm5200
......
arch/powerpc/platforms/52xx/mpc5200_simple.c
View file @ 77ecfe8d
......@@ -51,8 +51,9 @@ static void __init mpc5200_simple_setup_arch(void)
/* list of the supported boards */
static char *board[] __initdata = {
"intercontrol,digsy-mtc",
"promess,motionpro",
"phytec,pcm030",
"phytec,pcm032",
"promess,motionpro",
"schindler,cm5200",
"tqc,tqm5200",
NULL
......
arch/powerpc/platforms/52xx/mpc52xx_common.c
View file @ 77ecfe8d
......@@ -205,6 +205,43 @@ int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
}
EXPORT_SYMBOL(mpc52xx_set_psc_clkdiv);
/**
* mpc52xx_get_xtal_freq - Get SYS_XTAL_IN frequency for a device
*
* @node: device node
*
* Returns the frequency of the external oscillator clock connected
* to the SYS_XTAL_IN pin, or 0 if it cannot be determined.
*/
unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
{
u32 val;
unsigned int freq;
if (!mpc52xx_cdm)
return 0;
freq = mpc52xx_find_ipb_freq(node);
if (!freq)
return 0;
if (in_8(&mpc52xx_cdm->ipb_clk_sel) & 0x1)
freq *= 2;
val = in_be32(&mpc52xx_cdm->rstcfg);
if (val & (1 << 5))
freq *= 8;
else
freq *= 4;
if (val & (1 << 6))
freq /= 12;
else
freq /= 16;
return freq;
}
EXPORT_SYMBOL(mpc52xx_get_xtal_freq);
/**
* mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
*/
......
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
View file @ 77ecfe8d
......@@ -335,44 +335,6 @@ static void
mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
#endif /* defined(CONFIG_GPIOLIB) */
/***********************************************************************
* SYSFS attributes
*/
#if defined(CONFIG_SYSFS)
static ssize_t mpc52xx_gpt_show_regs(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct mpc52xx_gpt_priv *gpt = dev_get_drvdata(dev);
int i, len = 0;
u32 __iomem *regs = (void __iomem *) gpt->regs;
for (i = 0; i < 4; i++)
len += sprintf(buf + len, "%.8x ", in_be32(regs + i));
len += sprintf(buf + len, "\n");
return len;
}
static struct device_attribute mpc52xx_gpt_attrib[] = {
__ATTR(regs, S_IRUGO | S_IWUSR, mpc52xx_gpt_show_regs, NULL),
};
static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *gpt)
{
int i, err = 0;
for (i = 0; i < ARRAY_SIZE(mpc52xx_gpt_attrib); i++) {
err = device_create_file(gpt->dev, &mpc52xx_gpt_attrib[i]);
if (err)
dev_err(gpt->dev, "error creating attribute %i\n", i);
}
}
#else /* defined(CONFIG_SYSFS) */
static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *) { return 0; }
#endif /* defined(CONFIG_SYSFS) */
/* ---------------------------------------------------------------------
* of_platform bus binding code
*/
......@@ -395,7 +357,6 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
dev_set_drvdata(&ofdev->dev, gpt);
mpc52xx_gpt_create_attribs(gpt);
mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
mpc52xx_gpt_irq_setup(gpt, ofdev->node);
......
drivers/spi/xilinx_spi.c
View file @ 77ecfe8d
......@@ -354,7 +354,7 @@ static int __init xilinx_spi_of_probe(struct of_device *ofdev,
if (xspi->regs == NULL) {
rc = -ENOMEM;
dev_warn(&ofdev->dev, "ioremap failure\n");
goto put_master;
goto release_mem;
}
xspi->irq = r_irq->start;
......@@ -365,7 +365,7 @@ static int __init xilinx_spi_of_probe(struct of_device *ofdev,
prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len);
if (!prop || len < sizeof(*prop)) {
dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n");
goto put_master;
goto unmap_io;
}
master->num_chipselect = *prop;
......@@ -397,6 +397,8 @@ static int __init xilinx_spi_of_probe(struct of_device *ofdev,
free_irq(xspi->irq, xspi);
unmap_io:
iounmap(xspi->regs);
release_mem:
release_mem_region(r_mem->start, resource_size(r_mem));
put_master:
spi_master_put(master);
return rc;
......@@ -406,6 +408,7 @@ static int __devexit xilinx_spi_remove(struct of_device *ofdev)
{
struct xilinx_spi *xspi;
struct spi_master *master;
struct resource r_mem;
master = platform_get_drvdata(ofdev);
xspi = spi_master_get_devdata(master);
......@@ -413,6 +416,8 @@ static int __devexit xilinx_spi_remove(struct of_device *ofdev)
spi_bitbang_stop(&xspi->bitbang);
free_irq(xspi->irq, xspi);
iounmap(xspi->regs);
if (!of_address_to_resource(ofdev->node, 0, &r_mem))
release_mem_region(r_mem.start, resource_size(&r_mem));
dev_set_drvdata(&ofdev->dev, 0);
spi_master_put(xspi->bitbang.master);
......
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