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Commit 79a94c35 authored by Russell King's avatar Russell King
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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

parents f779b7dd f1de1613
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Showing with 1101 additions and 190 deletions
arch/arm/mach-mx25/clock.c
View file @ 79a94c35
......@@ -72,7 +72,7 @@ unsigned long get_rate_arm(struct clk *clk)
unsigned long rate = get_rate_mpll();
if (cctl & (1 << 14))
rate = (rate * 3) >> 1;
rate = (rate * 3) >> 2;
return rate / ((cctl >> 30) + 1);
}
......@@ -99,7 +99,7 @@ static unsigned long get_rate_per(int per)
if (readl(CRM_BASE + 0x64) & (1 << per))
fref = get_rate_upll();
else
fref = get_rate_ipg(NULL);
fref = get_rate_ahb(NULL);
return fref / (val + 1);
}
......@@ -261,7 +261,7 @@ DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
#define _REGISTER_CLOCK(d, n, c) \
{ \
......
arch/arm/mach-mx25/devices-imx25.h
View file @ 79a94c35
......@@ -49,7 +49,6 @@ extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
#define imx25_add_esdhc0(pdata) \
imx_add_esdhc(0, MX25_ESDHC1_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC1, pdata)
#define imx25_add_esdhc1(pdata) \
imx_add_esdhc(1, MX25_ESDHC2_BASE_ADDR, SZ_16K, MX25_INT_MMC_SDHC2, pdata)
extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
#define imx25_add_esdhc(id, pdata) \
imx_add_esdhc(&imx25_esdhc_data[id], pdata)
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
View file @ 79a94c35
......@@ -116,6 +116,38 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
},
.bpp = 16,
.pcr = 0xCAD08B80,
}, {
.mode = {
.name = "DVI-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 32000,
.hsync_len = 7,
.left_margin = 100,
.right_margin = 100,
.vsync_len = 7,
.upper_margin = 7,
.lower_margin = 100,
},
.pcr = 0xFA208B80,
.bpp = 16,
}, {
.mode = {
.name = "DVI-SVGA",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.hsync_len = 7,
.left_margin = 75,
.right_margin = 75,
.vsync_len = 7,
.upper_margin = 7,
.lower_margin = 75,
},
.pcr = 0xFA208B80,
.bpp = 16,
},
};
......@@ -245,7 +277,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx25_add_flexcan1(NULL);
imx25_add_esdhc0(NULL);
imx25_add_esdhc(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
......
arch/arm/mach-mx25/mach-cpuimx25.c
View file @ 79a94c35
......@@ -40,7 +40,6 @@
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
......@@ -134,18 +133,13 @@ static void __init eukrea_cpuimx25_init(void)
ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
if (otg_mode_host)
mxc_register_device(&mxc_otg, &otg_pdata);
}
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif
if (!otg_mode_host)
else
mxc_register_device(&otg_udc_device, &otg_device_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
eukrea_mbimxsd25_baseboard_init();
#endif
......
arch/arm/mach-mx3/devices-imx35.h
View file @ 79a94c35
......@@ -46,9 +46,6 @@ extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
#define imx35_add_esdhc0(pdata) \
imx_add_esdhc(0, MX35_ESDHC1_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC1, pdata)
#define imx35_add_esdhc1(pdata) \
imx_add_esdhc(1, MX35_ESDHC2_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC2, pdata)
#define imx35_add_esdhc2(pdata) \
imx_add_esdhc(2, MX35_ESDHC3_BASE_ADDR, SZ_16K, MX35_INT_MMC_SDHC3, pdata)
extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
#define imx35_add_esdhc(id, pdata) \
imx_add_esdhc(&imx35_esdhc_data[id], pdata)
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
View file @ 79a94c35
......@@ -49,7 +49,7 @@
static const struct fb_videomode fb_modedb[] = {
{
.name = "CMO_QVGA",
.name = "CMO-QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
......@@ -64,6 +64,40 @@ static const struct fb_videomode fb_modedb[] = {
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
{
.name = "DVI-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 32000,
.left_margin = 100,
.right_margin = 100,
.upper_margin = 7,
.lower_margin = 100,
.hsync_len = 7,
.vsync_len = 7,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
{
.name = "DVI-SVGA",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.left_margin = 75,
.right_margin = 75,
.upper_margin = 7,
.lower_margin = 75,
.hsync_len = 7,
.vsync_len = 7,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
};
static struct ipu_platform_data mx3_ipu_data = {
......@@ -72,7 +106,7 @@ static struct ipu_platform_data mx3_ipu_data = {
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
.name = "CMO_QVGA",
.name = "CMO-QVGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
};
......@@ -255,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc0(NULL);
imx35_add_esdhc(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
......@@ -267,7 +301,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
gpio_request(GPIO_LCDPWR, "LCDPWR");
gpio_direction_output(GPIO_LCDPWR, 1);
gpio_free(GPIO_SWITCH1);
gpio_free(GPIO_LCDPWR);
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
......
arch/arm/mach-mx3/mach-cpuimx35.c
View file @ 79a94c35
......@@ -44,7 +44,6 @@
#include <mach/iomux-mx35.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx35.h"
#include "devices.h"
......@@ -167,18 +166,13 @@ static void __init mxc_board_init(void)
ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
if (otg_mode_host)
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
#endif
if (!otg_mode_host)
else
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
eukrea_mbimxsd35_baseboard_init();
#endif
......
arch/arm/mach-mx3/mach-mx31ads.c
View file @ 79a94c35
......@@ -22,13 +22,13 @@
#include <linux/i2c.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31ads.h>
#include <mach/iomux-mx3.h>
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
......@@ -40,10 +40,6 @@
#include "devices-imx31.h"
#include "devices.h"
/* Base address of PBC controller */
#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
/* Offsets for the PBC Controller register */
/* PBC Board interrupt status register */
#define PBC_INTSTATUS 0x000016
......@@ -67,7 +63,6 @@
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
......
arch/arm/mach-mx3/mach-pcm037_eet.c
View file @ 79a94c35
......@@ -19,6 +19,7 @@
#include "pcm037.h"
#include "devices.h"
#include "devices-imx31.h"
static unsigned int pcm037_eet_pins[] = {
/* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
......@@ -181,7 +182,7 @@ static int eet_init_devices(void)
/* SPI */
spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
imx35_add_spi_imx0(&pcm037_spi1_pdata);
imx31_add_spi_imx0(&pcm037_spi1_pdata);
#endif
platform_device_register(&pcm037_gpio_keys_device);
......
arch/arm/mach-mx3/mach-pcm043.c
View file @ 79a94c35
......@@ -395,7 +395,7 @@ static void __init mxc_board_init(void)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc0(NULL);
imx35_add_esdhc(0, NULL);
}
static void __init pcm043_timer_init(void)
......
arch/arm/mach-mx5/Kconfig
View file @ 79a94c35
......@@ -31,6 +31,8 @@ config MACH_EUKREA_CPUIMX51
bool "Support Eukrea CPUIMX51 module"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for Eukrea CPUIMX51 platform. This includes
specific configurations for the module and its peripherals.
......@@ -43,12 +45,38 @@ choice
config MACH_EUKREA_MBIMX51_BASEBOARD
prompt "Eukrea MBIMX51 development board"
bool
select IMX_HAVE_PLATFORM_ESDHC
help
This adds board specific devices that can be found on Eukrea's
MBIMX51 evaluation board.
endchoice
config MACH_EUKREA_CPUIMX51SD
bool "Support Eukrea CPUIMX51SD module"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for Eukrea CPUIMX51SD platform. This includes
specific configurations for the module and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX51SD
default MACH_EUKREA_MBIMXSD51_BASEBOARD
config MACH_EUKREA_MBIMXSD51_BASEBOARD
prompt "Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_ESDHC
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_MX51_EFIKAMX
bool "Support MX51 Genesi Efika MX nettop"
select IMX_HAVE_PLATFORM_IMX_UART
......
arch/arm/mach-mx5/Makefile
View file @ 79a94c35
......@@ -9,4 +9,6 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
arch/arm/mach-mx5/board-cpuimx51.c
View file @ 79a94c35
......@@ -146,6 +146,13 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
MX51_PAD_USBH1_STP__USBH1_STP,
};
static const struct mxc_nand_platform_data
eukrea_cpuimx51_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
......@@ -239,6 +246,8 @@ static void __init eukrea_cpuimx51_init(void)
ARRAY_SIZE(eukrea_cpuimx51_pads));
imx51_add_imx_uart(0, &uart_pdata);
imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
gpio_direction_input(CPUIMX51_QUARTA_GPIO);
gpio_free(CPUIMX51_QUARTA_GPIO);
......
arch/arm/mach-mx5/board-cpuimx51sd.c 0 → 100644
View file @ 79a94c35
/*
*
* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
*
* based on board-mx51_babbage.c which is
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#define USBH1_RST (1*32 + 28)
#define ETH_RST (1*32 + 31)
#define TSC2007_IRQGPIO (2*32 + 12)
#define CAN_IRQGPIO (0*32 + 1)
#define CAN_RST (3*32 + 15)
#define CAN_NCS (3*32 + 24)
#define CAN_RXOBF (0*32 + 4)
#define CAN_RX1BF (0*32 + 6)
#define CAN_TXORTS (0*32 + 7)
#define CAN_TX1RTS (0*32 + 8)
#define CAN_TX2RTS (0*32 + 9)
#define I2C_SCL (3*32 + 16)
#define I2C_SDA (3*32 + 17)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
#define MX51_USB_PLLDIV_12_MHZ 0x00
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_24_MHZ 0x02
#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
static struct pad_desc eukrea_cpuimx51sd_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
MX51_PAD_UART1_RTS__UART1_RTS,
MX51_PAD_UART1_CTS__UART1_CTS,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
MX51_PAD_USBH1_DIR__USBH1_DIR,
MX51_PAD_USBH1_NXT__USBH1_NXT,
MX51_PAD_USBH1_DATA0__USBH1_DATA0,
MX51_PAD_USBH1_DATA1__USBH1_DATA1,
MX51_PAD_USBH1_DATA2__USBH1_DATA2,
MX51_PAD_USBH1_DATA3__USBH1_DATA3,
MX51_PAD_USBH1_DATA4__USBH1_DATA4,
MX51_PAD_USBH1_DATA5__USBH1_DATA5,
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
MX51_PAD_USBH1_STP__USBH1_STP,
MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */
/* FEC */
MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */
/* HSI2C */
MX51_PAD_I2C1_CLK__GPIO_4_16,
MX51_PAD_I2C1_DAT__GPIO_4_17,
/* CAN */
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */
MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */
MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */
MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */
MX51_PAD_GPIO_1_6__GPIO_1_6,
MX51_PAD_GPIO_1_7__GPIO_1_7,
MX51_PAD_GPIO_1_8__GPIO_1_8,
MX51_PAD_GPIO_1_9__GPIO_1_9,
/* Touchscreen */
CPUIMX51SD_GPIO_3_12, /* IRQ */
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static int ts_get_pendown_state(void)
{
return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
}
static struct tsc2007_platform_data tsc2007_info = {
.model = 2007,
.x_plate_ohms = 180,
.get_pendown_state = ts_get_pendown_state,
};
static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
}, {
I2C_BOARD_INFO("tsc2007", 0x49),
.type = "tsc2007",
.platform_data = &tsc2007_info,
.irq = gpio_to_irq(TSC2007_IRQGPIO),
},
};
static const struct mxc_nand_platform_data
eukrea_cpuimx51sd_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
/* This function is board specific as the bit mask for the plldiv will also
be different for other Freescale SoCs, thus a common bitmask is not
possible and cannot get place in /plat-mxc/ehci.c.*/
static int initialize_otg_port(struct platform_device *pdev)
{
u32 v;
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* Set the PHY clock to 19.2MHz */
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
v |= MX51_USB_PLL_DIV_19_2_MHZ;
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
iounmap(usb_base);
return 0;
}
static int initialize_usbh1_port(struct platform_device *pdev)
{
u32 v;
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* The clock for the USBH1 ULPI port will come from the PHY. */
v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
usbother_base + MX51_USB_CTRL_1_OFFSET);
iounmap(usb_base);
return 0;
}
static struct mxc_usbh_platform_data dr_utmi_config = {
.init = initialize_otg_port,
.portsc = MXC_EHCI_UTMI_16BIT,
.flags = MXC_EHCI_INTERNAL_PHY,
};
static struct fsl_usb2_platform_data usb_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
};
static struct mxc_usbh_platform_data usbh1_config = {
.init = initialize_usbh1_port,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
};
static int otg_mode_host;
static int __init eukrea_cpuimx51sd_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
static struct i2c_gpio_platform_data pdata = {
.sda_pin = I2C_SDA,
.sda_is_open_drain = 0,
.scl_pin = I2C_SCL,
.scl_is_open_drain = 0,
.udelay = 2,
};
static struct platform_device hsi2c_gpio_device = {
.name = "i2c-gpio",
.id = 0,
.dev.platform_data = &pdata,
};
static struct mcp251x_platform_data mcp251x_info = {
.oscillator_frequency = 24E6,
};
static struct spi_board_info cpuimx51sd_spi_device[] = {
{
.modalias = "mcp2515",
.max_speed_hz = 6500000,
.bus_num = 0,
.mode = SPI_MODE_0,
.chip_select = 0,
.platform_data = &mcp251x_info,
.irq = gpio_to_irq(0 * 32 + 1)
},
};
static int cpuimx51sd_spi1_cs[] = {
CAN_NCS,
};
static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
.chipselect = cpuimx51sd_spi1_cs,
.num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
};
static struct platform_device *platform_devices[] __initdata = {
&hsi2c_gpio_device,
};
static void __init eukrea_cpuimx51sd_init(void)
{
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
ARRAY_SIZE(eukrea_cpuimx51sd_pads));
imx51_add_imx_uart(0, &uart_pdata);
imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
gpio_request(ETH_RST, "eth_rst");
gpio_set_value(ETH_RST, 1);
imx51_add_fec(NULL);
gpio_request(CAN_IRQGPIO, "can_irq");
gpio_direction_input(CAN_IRQGPIO);
gpio_free(CAN_IRQGPIO);
gpio_request(CAN_NCS, "can_ncs");
gpio_direction_output(CAN_NCS, 1);
gpio_free(CAN_NCS);
gpio_request(CAN_RST, "can_rst");
gpio_direction_output(CAN_RST, 0);
msleep(20);
gpio_set_value(CAN_RST, 1);
imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
spi_register_board_info(cpuimx51sd_spi_device,
ARRAY_SIZE(cpuimx51sd_spi_device));
gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
gpio_direction_input(TSC2007_IRQGPIO);
gpio_free(TSC2007_IRQGPIO);
i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
if (otg_mode_host)
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
else {
initialize_otg_port(NULL);
mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
}
gpio_request(USBH1_RST, "usb_rst");
gpio_direction_output(USBH1_RST, 0);
msleep(20);
gpio_set_value(USBH1_RST, 1);
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
eukrea_mbimxsd51_baseboard_init();
#endif
}
static void __init eukrea_cpuimx51sd_timer_init(void)
{
mx51_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mxc_timer = {
.init = eukrea_cpuimx51sd_timer_init,
};
MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
/* Maintainer: Eric Bénard <eric@eukrea.com> */
.phys_io = MX51_AIPS1_BASE_ADDR,
.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx51_map_io,
.init_irq = mx51_init_irq,
.init_machine = eukrea_cpuimx51sd_init,
.timer = &mxc_timer,
MACHINE_END
arch/arm/mach-mx5/clock-mx51.c
View file @ 79a94c35
......@@ -41,6 +41,36 @@ static struct clk usboh3_clk;
#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
/* calculate best pre and post dividers to get the required divider */
static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
u32 max_pre, u32 max_post)
{
if (div >= max_pre * max_post) {
*pre = max_pre;
*post = max_post;
} else if (div >= max_pre) {
u32 min_pre, temp_pre, old_err, err;
min_pre = DIV_ROUND_UP(div, max_post);
old_err = max_pre;
for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
err = div % temp_pre;
if (err == 0) {
*pre = temp_pre;
break;
}
err = temp_pre - err;
if (err < old_err) {
old_err = err;
*pre = temp_pre;
}
}
*post = DIV_ROUND_UP(div, *pre);
} else {
*pre = div;
*post = 1;
}
}
static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
{
u32 reg = __raw_readl(clk->enable_reg);
......@@ -544,35 +574,6 @@ static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
static unsigned long clk_uart_get_rate(struct clk *clk)
{
u32 reg, prediv, podf;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
reg = __raw_readl(MXC_CCM_CSCDR1);
prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
return parent_rate / (prediv * podf);
}
static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
&lp_apm_clk);
reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
return 0;
}
#define clk_nfc_set_parent NULL
static unsigned long clk_nfc_get_rate(struct clk *clk)
......@@ -631,35 +632,6 @@ static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
static unsigned long clk_usboh3_get_rate(struct clk *clk)
{
u32 reg, prediv, podf;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
reg = __raw_readl(MXC_CCM_CSCDR1);
prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
return parent_rate / (prediv * podf);
}
static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
&lp_apm_clk);
reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
return 0;
}
static unsigned long get_high_reference_clock_rate(struct clk *clk)
{
return external_high_reference;
......@@ -786,18 +758,6 @@ static struct clk ipg_perclk = {
.set_parent = _clk_ipg_per_set_parent,
};
static struct clk uart_root_clk = {
.parent = &pll2_sw_clk,
.get_rate = clk_uart_get_rate,
.set_parent = _clk_uart_set_parent,
};
static struct clk usboh3_clk = {
.parent = &pll2_sw_clk,
.get_rate = clk_usboh3_get_rate,
.set_parent = _clk_usboh3_set_parent,
};
static struct clk ahb_max_clk = {
.parent = &ahb_clk,
.enable_reg = MXC_CCM_CCGR0,
......@@ -842,7 +802,7 @@ static struct clk emi_slow_clk = {
.get_rate = clk_emi_slow_get_rate,
};
#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s) \
#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
static struct clk name = { \
.id = i, \
.enable_reg = er, \
......@@ -857,35 +817,104 @@ static struct clk emi_slow_clk = {
.secondary = s, \
}
/* eCSPI */
static unsigned long clk_ecspi_get_rate(struct clk *clk)
{
u32 reg, pred, podf;
#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
static struct clk name = { \
.id = i, \
.enable_reg = er, \
.enable_shift = es, \
.get_rate = pfx##_get_rate, \
.set_rate = pfx##_set_rate, \
.set_parent = pfx##_set_parent, \
.enable = _clk_max_enable, \
.disable = _clk_max_disable, \
.parent = p, \
.secondary = s, \
}
reg = __raw_readl(MXC_CCM_CSCDR2);
#define CLK_GET_RATE(name, nr, bitsname) \
static unsigned long clk_##name##_get_rate(struct clk *clk) \
{ \
u32 reg, pred, podf; \
\
reg = __raw_readl(MXC_CCM_CSCDR##nr); \
pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
>> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
>> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
\
return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
(pred + 1) * (podf + 1)); \
}
pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
#define CLK_SET_PARENT(name, nr, bitsname) \
static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
{ \
u32 reg, mux; \
\
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
&pll3_sw_clk, &lp_apm_clk); \
reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
__raw_writel(reg, MXC_CCM_CSCMR##nr); \
\
return 0; \
}
return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),
(pred + 1) * (podf + 1));
#define CLK_SET_RATE(name, nr, bitsname) \
static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
{ \
u32 reg, div, parent_rate; \
u32 pre = 0, post = 0; \
\
parent_rate = clk_get_rate(clk->parent); \
div = parent_rate / rate; \
\
if ((parent_rate / div) != rate) \
return -EINVAL; \
\
__calc_pre_post_dividers(div, &pre, &post, \
(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
\
/* Set sdhc1 clock divider */ \
reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
| MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
reg |= (post - 1) << \
MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
reg |= (pre - 1) << \
MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
__raw_writel(reg, MXC_CCM_CSCDR##nr); \
\
return 0; \
}
static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
/* UART */
CLK_GET_RATE(uart, 1, UART)
CLK_SET_PARENT(uart, 1, UART)
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
&lp_apm_clk);
static struct clk uart_root_clk = {
.parent = &pll2_sw_clk,
.get_rate = clk_uart_get_rate,
.set_parent = clk_uart_set_parent,
};
reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
/* USBOH3 */
CLK_GET_RATE(usboh3, 1, USBOH3)
CLK_SET_PARENT(usboh3, 1, USBOH3)
return 0;
}
static struct clk usboh3_clk = {
.parent = &pll2_sw_clk,
.get_rate = clk_usboh3_get_rate,
.set_parent = clk_usboh3_set_parent,
};
/* eCSPI */
CLK_GET_RATE(ecspi, 2, CSPI)
CLK_SET_PARENT(ecspi, 1, CSPI)
static struct clk ecspi_main_clk = {
.parent = &pll3_sw_clk,
......@@ -893,6 +922,15 @@ static struct clk ecspi_main_clk = {
.set_parent = clk_ecspi_set_parent,
};
/* eSDHC */
CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
static struct clk name = { \
.id = i, \
......@@ -946,7 +984,7 @@ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
NULL, NULL, &ipg_clk, NULL);
/* NFC */
DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
clk_nfc, &emi_slow_clk, NULL);
/* SSI */
......@@ -981,6 +1019,16 @@ DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
NULL, NULL, &ahb_clk, NULL);
/* eSDHC */
DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
......@@ -1014,6 +1062,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
_REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
};
static void clk_tree_init(void)
......@@ -1057,6 +1107,14 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
/* set the usboh3_clk parent to pll2_sw_clk */
clk_set_parent(&usboh3_clk, &pll2_sw_clk);
/* Set SDHC parents to be PLL2 */
clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
/* set SDHC root clock as 166.25MHZ*/
clk_set_rate(&esdhc1_clk, 166250000);
clk_set_rate(&esdhc2_clk, 166250000);
/* System timer */
mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
MX51_MXC_INT_GPT);
......
arch/arm/mach-mx5/devices-imx51.h
View file @ 79a94c35
......@@ -36,3 +36,7 @@ extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
#define imx51_add_esdhc(id, pdata) \
imx_add_esdhc(&imx51_esdhc_data[id], pdata)
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View file @ 79a94c35
......@@ -113,6 +113,22 @@ static struct pad_desc mbimx51_pads[] = {
MX51_PAD_KEY_COL1__KEY_COL1,
MX51_PAD_KEY_COL2__KEY_COL2,
MX51_PAD_KEY_COL3__KEY_COL3,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD1_CLK__SD1_CLK,
MX51_PAD_SD1_DATA0__SD1_DATA0,
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
MX51_PAD_SD2_CLK__SD2_CLK,
MX51_PAD_SD2_DATA0__SD2_DATA0,
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
......@@ -159,9 +175,11 @@ struct tsc2007_platform_data tsc2007_data = {
static struct i2c_board_info mbimx51_i2c_devices[] = {
{
I2C_BOARD_INFO("tsc2007", 0x48),
I2C_BOARD_INFO("tsc2007", 0x49),
.irq = MBIMX51_TSC2007_IRQ,
.platform_data = &tsc2007_data,
}, {
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
......@@ -198,4 +216,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
i2c_register_board_info(1, mbimx51_i2c_devices,
ARRAY_SIZE(mbimx51_i2c_devices));
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
}
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c 0 → 100644
View file @ 79a94c35
/*
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <mach/audmux.h>
#include "devices-imx51.h"
#include "devices.h"
#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
static struct pad_desc eukrea_mbimxsd_pads[] = {
/* LED */
MX51_PAD_NANDF_D10__GPIO_3_30,
/* SWITCH */
MBIMXSD_GPIO_3_31,
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
/* UART 3 */
MX51_PAD_UART3_RXD__UART3_RXD,
MX51_PAD_UART3_TXD__UART3_TXD,
MX51_PAD_KEY_COL4__UART3_RTS,
MX51_PAD_KEY_COL5__UART3_CTS,
/* SD */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD1_CLK__SD1_CLK,
MX51_PAD_SD1_DATA0__SD1_DATA0,
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
};
#define GPIO_LED1 (2 * 32 + 30)
#define GPIO_SWITCH1 (2 * 32 + 31)
static struct gpio_led eukrea_mbimxsd_leds[] = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = GPIO_LED1,
},
};
static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
.leds = eukrea_mbimxsd_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
};
static struct platform_device eukrea_mbimxsd_leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &eukrea_mbimxsd_led_info,
},
};
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
.code = BTN_0,
.desc = "BP1",
.active_low = 1,
.wakeup = 1,
},
};
static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device eukrea_mbimxsd_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &eukrea_mbimxsd_button_data,
}
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_button_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
/*
* system init for baseboard usage. Will be called by cpuimx51sd init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimxsd51_baseboard_init(void)
{
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
ARRAY_SIZE(eukrea_mbimxsd_pads)))
printk(KERN_ERR "error setting mbimxsd pads !\n");
imx51_add_imx_uart(1, NULL);
imx51_add_imx_uart(2, &uart_pdata);
imx51_add_esdhc(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
gpio_free(GPIO_LED1);
gpio_request(GPIO_SWITCH1, "SWITCH1");
gpio_direction_input(GPIO_SWITCH1);
gpio_free(GPIO_SWITCH1);
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
arch/arm/plat-mxc/Kconfig
View file @ 79a94c35
......@@ -122,4 +122,8 @@ config ARCH_MXC_AUDMUX_V1
config ARCH_MXC_AUDMUX_V2
bool
config IRAM_ALLOC
bool
select GENERIC_ALLOCATOR
endif
arch/arm/plat-mxc/Makefile
View file @ 79a94c35
......@@ -10,6 +10,7 @@ obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
obj-$(CONFIG_MXC_PWM) += pwm.o
obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
obj-$(CONFIG_MXC_ULPI) += ulpi.o
......
arch/arm/plat-mxc/devices/platform-esdhc.c
View file @ 79a94c35
......@@ -6,26 +6,66 @@
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#include <mach/esdhc.h>
struct platform_device *__init imx_add_esdhc(int id,
resource_size_t iobase, resource_size_t iosize,
resource_size_t irq,
#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
{ \
.id = _id, \
.iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
.irq = soc ## _INT_ESDHC ## hwid, \
}
#define imx_esdhc_imx_data_entry(soc, id, hwid) \
[id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
#ifdef CONFIG_ARCH_MX25
const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
#define imx25_esdhc_data_entry(_id, _hwid) \
imx_esdhc_imx_data_entry(MX25, _id, _hwid)
imx25_esdhc_data_entry(0, 1),
imx25_esdhc_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX25 */
#ifdef CONFIG_ARCH_MX35
const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
#define imx35_esdhc_data_entry(_id, _hwid) \
imx_esdhc_imx_data_entry(MX35, _id, _hwid)
imx35_esdhc_data_entry(0, 1),
imx35_esdhc_data_entry(1, 2),
imx35_esdhc_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
#define imx51_esdhc_data_entry(_id, _hwid) \
imx_esdhc_imx_data_entry(MX51, _id, _hwid)
imx51_esdhc_data_entry(0, 1),
imx51_esdhc_data_entry(1, 2),
imx51_esdhc_data_entry(2, 3),
imx51_esdhc_data_entry(3, 4),
};
#endif /* ifdef CONFIG_ARCH_MX51 */
struct platform_device *__init imx_add_esdhc(
const struct imx_esdhc_imx_data *data,
const struct esdhc_platform_data *pdata)
{
struct resource res[] = {
{
.start = iobase,
.end = iobase + iosize - 1,
.start = data->iobase,
.end = data->iobase + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = irq,
.end = irq,
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("sdhci-esdhc-imx", id, res,
return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
arch/arm/plat-mxc/devices/platform-imx-i2c.c
View file @ 79a94c35
......@@ -65,6 +65,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
imx35_imx_i2c_data_entry(0, 1),
imx35_imx_i2c_data_entry(1, 2),
imx35_imx_i2c_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
......
arch/arm/plat-mxc/include/mach/board-mx31ads.h 0 → 100644
View file @ 79a94c35
/*
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#include <mach/hardware.h>
/*
* These symbols are used by drivers/net/cs89x0.c.
* This is ugly as hell, but we have to provide them until
* someone fixed the driver.
*/
/* Base address of PBC controller */
#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
/* Offsets for the PBC Controller register */
/* Ethernet Controller IO base address */
#define PBC_CS8900A_IOBASE 0x020000
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
arch/arm/plat-mxc/include/mach/devices-common.h
View file @ 79a94c35
......@@ -108,7 +108,11 @@ struct platform_device *__init imx_add_spi_imx(
const struct spi_imx_master *pdata);
#include <mach/esdhc.h>
struct platform_device *__init imx_add_esdhc(int id,
resource_size_t iobase, resource_size_t iosize,
resource_size_t irq,
struct imx_esdhc_imx_data {
int id;
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_esdhc(
const struct imx_esdhc_imx_data *data,
const struct esdhc_platform_data *pdata);
arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
View file @ 79a94c35
......@@ -28,19 +28,22 @@
* its own devices, it calls baseboard's init function.
* TODO: Add your own baseboard init function and call it from
* inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
* eukrea_cpuimx35_init() or eukrea_cpuimx51_init().
* eukrea_cpuimx35_init() eukrea_cpuimx51_init()
* or eukrea_cpuimx51sd_init().
*
* This example here is for the development board. Refer
* mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
* mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
* mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
* mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
* mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
*/
extern void eukrea_mbimxsd25_baseboard_init(void);
extern void eukrea_mbimx27_baseboard_init(void);
extern void eukrea_mbimxsd35_baseboard_init(void);
extern void eukrea_mbimx51_baseboard_init(void);
extern void eukrea_mbimxsd51_baseboard_init(void);
#endif
......
arch/arm/plat-mxc/include/mach/iomux-mx51.h
View file @ 79a94c35
......@@ -47,6 +47,9 @@ typedef enum iomux_config {
PAD_CTL_SRE_FAST)
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
PAD_CTL_SRE_FAST)
#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
PAD_CTL_DVS)
#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
......@@ -333,38 +336,50 @@ typedef enum iomux_config {
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
0x9b8, 3, MX51_I2C_PAD_CTRL)
#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
0x9bc, 3, MX51_I2C_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#endif /* __MACH_IOMUX_MX51_H__ */
arch/arm/plat-mxc/include/mach/iram.h 0 → 100644
View file @ 79a94c35
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/errno.h>
#ifdef CONFIG_IRAM_ALLOC
int __init iram_init(unsigned long base, unsigned long size);
void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
void iram_free(unsigned long dma_addr, unsigned int size);
#else
static inline int __init iram_init(unsigned long base, unsigned long size)
{
return -ENOMEM;
}
static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
{
return NULL;
}
static inline void iram_free(unsigned long base, unsigned long size) {}
#endif
arch/arm/plat-mxc/include/mach/mx25.h
View file @ 79a94c35
......@@ -54,6 +54,7 @@
#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
#define MX25_LCDC_BASE_ADDR 0x53fbc000
#define MX25_KPP_BASE_ADDR 0x43fa8000
#define MX25_SDMA_BASE_ADDR 0x53fd4000
#define MX25_OTG_BASE_ADDR 0x53ff4000
#define MX25_CSI_BASE_ADDR 0x53ff8000
......@@ -61,8 +62,8 @@
#define MX25_INT_I2C1 3
#define MX25_INT_I2C2 4
#define MX25_INT_UART4 5
#define MX25_INT_MMC_SDHC2 8
#define MX25_INT_MMC_SDHC1 9
#define MX25_INT_ESDHC2 8
#define MX25_INT_ESDHC1 9
#define MX25_INT_I2C3 10
#define MX25_INT_SSI2 11
#define MX25_INT_SSI1 12
......@@ -74,6 +75,7 @@
#define MX25_INT_DRYICE 25
#define MX25_INT_UART2 32
#define MX25_INT_NFC 33
#define MX25_INT_SDMA 34
#define MX25_INT_LCDC 39
#define MX25_INT_UART5 40
#define MX25_INT_CAN1 43
......
arch/arm/plat-mxc/include/mach/mx35.h
View file @ 79a94c35
......@@ -128,9 +128,9 @@
#define MX35_INT_I2C3 3
#define MX35_INT_I2C2 4
#define MX35_INT_RTIC 6
#define MX35_INT_MMC_SDHC1 7
#define MX35_INT_MMC_SDHC2 8
#define MX35_INT_MMC_SDHC3 9
#define MX35_INT_ESDHC1 7
#define MX35_INT_ESDHC2 8
#define MX35_INT_ESDHC3 9
#define MX35_INT_I2C1 10
#define MX35_INT_SSI1 11
#define MX35_INT_SSI2 12
......
arch/arm/plat-mxc/include/mach/mx51.h
View file @ 79a94c35
......@@ -64,13 +64,13 @@
#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
#define MX51_SPBA0_SIZE SZ_1M
#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
......@@ -280,10 +280,10 @@
*/
#define MX51_MXC_INT_BASE 0
#define MX51_MXC_INT_RESV0 0
#define MX51_MXC_INT_MMC_SDHC1 1
#define MX51_MXC_INT_MMC_SDHC2 2
#define MX51_MXC_INT_MMC_SDHC3 3
#define MX51_MXC_INT_MMC_SDHC4 4
#define MX51_INT_ESDHC1 1
#define MX51_INT_ESDHC2 2
#define MX51_INT_ESDHC3 3
#define MX51_INT_ESDHC4 4
#define MX51_MXC_INT_RESV5 5
#define MX51_INT_SDMA 6
#define MX51_MXC_INT_IOMUX 7
......
arch/arm/plat-mxc/include/mach/system.h
View file @ 79a94c35
/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -28,8 +28,34 @@ static inline void arch_idle(void)
mxc91231_prepare_idle();
}
#endif
cpu_do_idle();
/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
if (cpu_is_mx31() || cpu_is_mx35()) {
unsigned long reg = 0;
__asm__ __volatile__(
/* disable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
"bic %0, %0, #0x00001000\n"
"bic %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
/* invalidate I cache */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c5, 0\n"
/* clear and invalidate D cache */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c14, 0\n"
/* WFI */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c0, 4\n"
"nop\n" "nop\n" "nop\n" "nop\n"
"nop\n" "nop\n" "nop\n"
/* enable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
"orr %0, %0, #0x00001000\n"
"orr %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
: "=r" (reg));
} else
cpu_do_idle();
}
void arch_reset(char mode, const char *cmd);
......
arch/arm/plat-mxc/include/mach/uncompress.h
View file @ 79a94c35
......@@ -99,6 +99,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
uart_base = MX3X_UART2_BASE_ADDR;
break;
case MACH_TYPE_MX51_BABBAGE:
case MACH_TYPE_EUKREA_CPUIMX51SD:
uart_base = MX51_UART1_BASE_ADDR;
break;
default:
......
arch/arm/plat-mxc/iram_alloc.c 0 → 100644
View file @ 79a94c35
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/genalloc.h>
#include <mach/iram.h>
static unsigned long iram_phys_base;
static void __iomem *iram_virt_base;
static struct gen_pool *iram_pool;
static inline void __iomem *iram_phys_to_virt(unsigned long p)
{
return iram_virt_base + (p - iram_phys_base);
}
void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
{
if (!iram_pool)
return NULL;
*dma_addr = gen_pool_alloc(iram_pool, size);
pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr);
if (!*dma_addr)
return NULL;
return iram_phys_to_virt(*dma_addr);
}
EXPORT_SYMBOL(iram_alloc);
void iram_free(unsigned long addr, unsigned int size)
{
if (!iram_pool)
return;
gen_pool_free(iram_pool, addr, size);
}
EXPORT_SYMBOL(iram_free);
int __init iram_init(unsigned long base, unsigned long size)
{
iram_phys_base = base;
iram_pool = gen_pool_create(PAGE_SHIFT, -1);
if (!iram_pool)
return -ENOMEM;
gen_pool_add(iram_pool, base, size, -1);
iram_virt_base = ioremap(iram_phys_base, size);
if (!iram_virt_base)
return -EIO;
pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base);
return 0;
}
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