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Commit 7c2b6c1e authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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media: atomisp: remove several duplicated files 

Those files have identical contents, but are located at
different parts of the driver. As their contents are identical,
we can simply remove them.
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent c8b1a84e
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Showing with 9 additions and 6605 deletions
drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c
View file @ 7c2b6c1e
......@@ -58,7 +58,7 @@
#include "ia_css_types.h"
#include "ia_css_stream.h"
#include "error_support.h"
#include "hrt/bits.h"
#include "bits.h"
/* We should never need to run the flash for more than 2 frames.
* At 15fps this means 133ms. We set the timeout a bit longer.
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifdef IA_CSS_INCLUDE_CONFIGURATIONS
#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h"
#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h"
#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h"
#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h"
#include "isp/kernels/output/output_1.0/ia_css_output.host.h"
#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h"
#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h"
/* ISP2401 */
#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h"
#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h"
#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h"
#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_CONFIG_H
#define _IA_CSS_ISP_CONFIG_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_configuration_ids {
IA_CSS_ITERATOR_CONFIG_ID,
IA_CSS_COPY_OUTPUT_CONFIG_ID,
IA_CSS_CROP_CONFIG_ID,
IA_CSS_FPN_CONFIG_ID,
IA_CSS_DVS_CONFIG_ID,
IA_CSS_QPLANE_CONFIG_ID,
IA_CSS_OUTPUT0_CONFIG_ID,
IA_CSS_OUTPUT1_CONFIG_ID,
IA_CSS_OUTPUT_CONFIG_ID,
IA_CSS_RAW_CONFIG_ID,
IA_CSS_TNR_CONFIG_ID,
IA_CSS_REF_CONFIG_ID,
IA_CSS_VF_CONFIG_ID,
/* ISP2401 */
IA_CSS_SC_CONFIG_ID,
IA_CSS_NUM_CONFIGURATION_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_config_memory_offsets {
struct {
struct ia_css_isp_parameter iterator;
struct ia_css_isp_parameter copy_output;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter dvs;
struct ia_css_isp_parameter qplane;
struct ia_css_isp_parameter output0;
struct ia_css_isp_parameter output1;
struct ia_css_isp_parameter output;
/* ISP2401 */
struct ia_css_isp_parameter sc;
struct ia_css_isp_parameter raw;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
struct ia_css_isp_parameter vf;
} dmem;
};
#if defined(IA_CSS_INCLUDE_CONFIGURATIONS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_iterator(
const struct ia_css_binary *binary,
const struct ia_css_iterator_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_copy_output(
const struct ia_css_binary *binary,
const struct ia_css_copy_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_crop(
const struct ia_css_binary *binary,
const struct ia_css_crop_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_fpn(
const struct ia_css_binary *binary,
const struct ia_css_fpn_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_dvs(
const struct ia_css_binary *binary,
const struct ia_css_dvs_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_qplane(
const struct ia_css_binary *binary,
const struct ia_css_qplane_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output0(
const struct ia_css_binary *binary,
const struct ia_css_output0_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output1(
const struct ia_css_binary *binary,
const struct ia_css_output1_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output(
const struct ia_css_binary *binary,
const struct ia_css_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
/* ISP2401 */
void
ia_css_configure_sc(
const struct ia_css_binary *binary,
const struct ia_css_sc_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_raw(
const struct ia_css_binary *binary,
const struct ia_css_raw_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_tnr(
const struct ia_css_binary *binary,
const struct ia_css_tnr_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_ref(
const struct ia_css_binary *binary,
const struct ia_css_ref_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_vf(
const struct ia_css_binary *binary,
const struct ia_css_vf_configuration *config_dmem);
#endif /* IA_CSS_INCLUDE_CONFIGURATION */
#endif /* _IA_CSS_ISP_CONFIG_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_PARAM_H
#define _IA_CSS_ISP_PARAM_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_parameter_ids {
IA_CSS_AA_ID,
IA_CSS_ANR_ID,
IA_CSS_ANR2_ID,
IA_CSS_BH_ID,
IA_CSS_CNR_ID,
IA_CSS_CROP_ID,
IA_CSS_CSC_ID,
IA_CSS_DP_ID,
IA_CSS_BNR_ID,
IA_CSS_DE_ID,
IA_CSS_ECD_ID,
IA_CSS_FORMATS_ID,
IA_CSS_FPN_ID,
IA_CSS_GC_ID,
IA_CSS_CE_ID,
IA_CSS_YUV2RGB_ID,
IA_CSS_RGB2YUV_ID,
IA_CSS_R_GAMMA_ID,
IA_CSS_G_GAMMA_ID,
IA_CSS_B_GAMMA_ID,
IA_CSS_UDS_ID,
IA_CSS_RAA_ID,
IA_CSS_S3A_ID,
IA_CSS_OB_ID,
IA_CSS_OUTPUT_ID,
IA_CSS_SC_ID,
IA_CSS_BDS_ID,
IA_CSS_TNR_ID,
IA_CSS_MACC_ID,
IA_CSS_SDIS_HORICOEF_ID,
IA_CSS_SDIS_VERTCOEF_ID,
IA_CSS_SDIS_HORIPROJ_ID,
IA_CSS_SDIS_VERTPROJ_ID,
IA_CSS_SDIS2_HORICOEF_ID,
IA_CSS_SDIS2_VERTCOEF_ID,
IA_CSS_SDIS2_HORIPROJ_ID,
IA_CSS_SDIS2_VERTPROJ_ID,
IA_CSS_WB_ID,
IA_CSS_NR_ID,
IA_CSS_YEE_ID,
IA_CSS_YNR_ID,
IA_CSS_FC_ID,
IA_CSS_CTC_ID,
IA_CSS_XNR_TABLE_ID,
IA_CSS_XNR_ID,
IA_CSS_XNR3_ID,
IA_CSS_NUM_PARAMETER_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter anr;
struct ia_css_isp_parameter bh;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter csc;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter bnr;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ecd;
struct ia_css_isp_parameter formats;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter gc;
struct ia_css_isp_parameter ce;
struct ia_css_isp_parameter yuv2rgb;
struct ia_css_isp_parameter rgb2yuv;
struct ia_css_isp_parameter uds;
struct ia_css_isp_parameter raa;
struct ia_css_isp_parameter s3a;
struct ia_css_isp_parameter ob;
struct ia_css_isp_parameter output;
struct ia_css_isp_parameter sc;
struct ia_css_isp_parameter bds;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter macc;
struct ia_css_isp_parameter sdis_horiproj;
struct ia_css_isp_parameter sdis_vertproj;
struct ia_css_isp_parameter sdis2_horiproj;
struct ia_css_isp_parameter sdis2_vertproj;
struct ia_css_isp_parameter wb;
struct ia_css_isp_parameter nr;
struct ia_css_isp_parameter yee;
struct ia_css_isp_parameter ynr;
struct ia_css_isp_parameter fc;
struct ia_css_isp_parameter ctc;
struct ia_css_isp_parameter xnr;
struct ia_css_isp_parameter xnr3;
struct ia_css_isp_parameter get;
struct ia_css_isp_parameter put;
} dmem;
struct {
struct ia_css_isp_parameter anr2;
struct ia_css_isp_parameter ob;
struct ia_css_isp_parameter sdis_horicoef;
struct ia_css_isp_parameter sdis_vertcoef;
struct ia_css_isp_parameter sdis2_horicoef;
struct ia_css_isp_parameter sdis2_vertcoef;
/* ISP2401 */
struct ia_css_isp_parameter xnr3;
} vmem;
struct {
struct ia_css_isp_parameter bh;
} hmem0;
struct {
struct ia_css_isp_parameter gc;
struct ia_css_isp_parameter g_gamma;
struct ia_css_isp_parameter xnr_table;
} vamem1;
struct {
struct ia_css_isp_parameter r_gamma;
struct ia_css_isp_parameter ctc;
} vamem0;
struct {
struct ia_css_isp_parameter b_gamma;
} vamem2;
};
#if defined(IA_CSS_INCLUDE_PARAMETERS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/gencode.c:gen_param_process_table() */
struct ia_css_pipeline_stage; /* forward declaration */
extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_dp_config(struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_wb_config(struct ia_css_isp_parameters *params,
const struct ia_css_wb_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_tnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ob_config(struct ia_css_isp_parameters *params,
const struct ia_css_ob_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_de_config(struct ia_css_isp_parameters *params,
const struct ia_css_de_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_anr_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_thres *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ce_config(struct ia_css_isp_parameters *params,
const struct ia_css_ce_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
const struct ia_css_ecd_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ynr_config(struct ia_css_isp_parameters *params,
const struct ia_css_ynr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_fc_config(struct ia_css_isp_parameters *params,
const struct ia_css_fc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_cnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_cnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_macc_config(struct ia_css_isp_parameters *params,
const struct ia_css_macc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ctc_config(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_aa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_csc_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_gc_config(struct ia_css_isp_parameters *params,
const struct ia_css_gc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_formats_config(struct ia_css_isp_parameters *params,
const struct ia_css_formats_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr3_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr3_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_s3a_config(struct ia_css_isp_parameters *params,
const struct ia_css_3a_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_output_config(struct ia_css_isp_parameters *params,
const struct ia_css_output_config *config);
/* Code generated by genparam/gencode.c:gen_global_access_function() */
void
ia_css_get_configs(struct ia_css_isp_parameters *params,
const struct ia_css_isp_config *config)
;
/* Code generated by genparam/gencode.c:gen_global_access_function() */
void
ia_css_set_configs(struct ia_css_isp_parameters *params,
const struct ia_css_isp_config *config)
;
#endif /* IA_CSS_INCLUDE_PARAMETER */
#endif /* _IA_CSS_ISP_PARAM_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#define IA_CSS_INCLUDE_STATES
#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h"
#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h"
#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h"
#include "isp/kernels/de/de_1.0/ia_css_de.host.h"
#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h"
#include "isp/kernels/dpc2/ia_css_dpc2.host.h"
#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h"
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_STATE_H
#define _IA_CSS_ISP_STATE_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_state_ids {
IA_CSS_AA_STATE_ID,
IA_CSS_CNR_STATE_ID,
IA_CSS_CNR2_STATE_ID,
IA_CSS_DP_STATE_ID,
IA_CSS_DE_STATE_ID,
IA_CSS_TNR_STATE_ID,
IA_CSS_REF_STATE_ID,
IA_CSS_YNR_STATE_ID,
IA_CSS_NUM_STATE_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_state_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter cnr2;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ynr;
} vmem;
struct {
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
} dmem;
};
#if defined(IA_CSS_INCLUDE_STATES)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genstate.c:gen_state_init_table() */
extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(
const struct ia_css_binary *binary);
#endif /* IA_CSS_INCLUDE_STATE */
#endif /* _IA_CSS_ISP_STATE_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h
View file @ 7c2b6c1e
......@@ -28,7 +28,7 @@
#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
/* This interface is deprecated */
#include "hrt/hive_types.h"
#include "hive_types.h"
/*
* Cell specific address maps
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_BITS_H
#define _HRT_BITS_H
#include "defs.h"
#define _hrt_ones(n) HRTCAT(_hrt_ones_, n)
#define _hrt_ones_0x0 0x00000000U
#define _hrt_ones_0x1 0x00000001U
#define _hrt_ones_0x2 0x00000003U
#define _hrt_ones_0x3 0x00000007U
#define _hrt_ones_0x4 0x0000000FU
#define _hrt_ones_0x5 0x0000001FU
#define _hrt_ones_0x6 0x0000003FU
#define _hrt_ones_0x7 0x0000007FU
#define _hrt_ones_0x8 0x000000FFU
#define _hrt_ones_0x9 0x000001FFU
#define _hrt_ones_0xA 0x000003FFU
#define _hrt_ones_0xB 0x000007FFU
#define _hrt_ones_0xC 0x00000FFFU
#define _hrt_ones_0xD 0x00001FFFU
#define _hrt_ones_0xE 0x00003FFFU
#define _hrt_ones_0xF 0x00007FFFU
#define _hrt_ones_0x10 0x0000FFFFU
#define _hrt_ones_0x11 0x0001FFFFU
#define _hrt_ones_0x12 0x0003FFFFU
#define _hrt_ones_0x13 0x0007FFFFU
#define _hrt_ones_0x14 0x000FFFFFU
#define _hrt_ones_0x15 0x001FFFFFU
#define _hrt_ones_0x16 0x003FFFFFU
#define _hrt_ones_0x17 0x007FFFFFU
#define _hrt_ones_0x18 0x00FFFFFFU
#define _hrt_ones_0x19 0x01FFFFFFU
#define _hrt_ones_0x1A 0x03FFFFFFU
#define _hrt_ones_0x1B 0x07FFFFFFU
#define _hrt_ones_0x1C 0x0FFFFFFFU
#define _hrt_ones_0x1D 0x1FFFFFFFU
#define _hrt_ones_0x1E 0x3FFFFFFFU
#define _hrt_ones_0x1F 0x7FFFFFFFU
#define _hrt_ones_0x20 0xFFFFFFFFU
#define _hrt_ones_0 _hrt_ones_0x0
#define _hrt_ones_1 _hrt_ones_0x1
#define _hrt_ones_2 _hrt_ones_0x2
#define _hrt_ones_3 _hrt_ones_0x3
#define _hrt_ones_4 _hrt_ones_0x4
#define _hrt_ones_5 _hrt_ones_0x5
#define _hrt_ones_6 _hrt_ones_0x6
#define _hrt_ones_7 _hrt_ones_0x7
#define _hrt_ones_8 _hrt_ones_0x8
#define _hrt_ones_9 _hrt_ones_0x9
#define _hrt_ones_10 _hrt_ones_0xA
#define _hrt_ones_11 _hrt_ones_0xB
#define _hrt_ones_12 _hrt_ones_0xC
#define _hrt_ones_13 _hrt_ones_0xD
#define _hrt_ones_14 _hrt_ones_0xE
#define _hrt_ones_15 _hrt_ones_0xF
#define _hrt_ones_16 _hrt_ones_0x10
#define _hrt_ones_17 _hrt_ones_0x11
#define _hrt_ones_18 _hrt_ones_0x12
#define _hrt_ones_19 _hrt_ones_0x13
#define _hrt_ones_20 _hrt_ones_0x14
#define _hrt_ones_21 _hrt_ones_0x15
#define _hrt_ones_22 _hrt_ones_0x16
#define _hrt_ones_23 _hrt_ones_0x17
#define _hrt_ones_24 _hrt_ones_0x18
#define _hrt_ones_25 _hrt_ones_0x19
#define _hrt_ones_26 _hrt_ones_0x1A
#define _hrt_ones_27 _hrt_ones_0x1B
#define _hrt_ones_28 _hrt_ones_0x1C
#define _hrt_ones_29 _hrt_ones_0x1D
#define _hrt_ones_30 _hrt_ones_0x1E
#define _hrt_ones_31 _hrt_ones_0x1F
#define _hrt_ones_32 _hrt_ones_0x20
#define _hrt_mask(b, n) \
(_hrt_ones(n) << (b))
#define _hrt_get_bits(w, b, n) \
(((w) >> (b)) & _hrt_ones(n))
#define _hrt_set_bits(w, b, n, v) \
(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
(((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
_hrt_set_bits(w, 16, 16, v)
#endif /* _HRT_BITS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _cell_params_h
#define _cell_params_h
#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/
#define SP_ICACHE_TAG_BITS 4 /*size of tag*/
#define SP_ICACHE_SET_BITS 8 /* 256 sets*/
#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
(SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_2_DEPTH 0
#define SP_FIFO_3_DEPTH 0
#define SP_FIFO_4_DEPTH 0
#define SP_FIFO_5_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_common_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _css_receiver_2400_common_defs_h_
#define _css_receiver_2400_common_defs_h_
#ifndef _mipi_backend_common_defs_h_
#define _mipi_backend_common_defs_h_
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
/* Definition of format_types at the interface CSS --> input_selector*/
/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1
#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22
#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2
#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16
#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6
#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
/* Pixel Extractor config */
#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
#endif /* _css_receiver_2400_common_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _css_receiver_2400_defs_h_
#define _css_receiver_2400_defs_h_
#include "css_receiver_2400_common_defs.h"
#define CSS_RECEIVER_DATA_WIDTH 8
#define CSS_RECEIVER_RX_TRIG 4
#define CSS_RECEIVER_RF_WORD 32
#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10
#define CSS_RECEIVER_CSI_RF_ADDR 4
#define CSS_RECEIVER_DATA_OUT 12
#define CSS_RECEIVER_CHN_NO 2
#define CSS_RECEIVER_DWORD_CNT 11
#define CSS_RECEIVER_FORMAT_TYP 5
#define CSS_RECEIVER_HRESPONSE 2
#define CSS_RECEIVER_STATE_WIDTH 3
#define CSS_RECEIVER_FIFO_DAT 32
#define CSS_RECEIVER_CNT_VAL 2
#define CSS_RECEIVER_PRED10_VAL 10
#define CSS_RECEIVER_PRED12_VAL 12
#define CSS_RECEIVER_CNT_WIDTH 8
#define CSS_RECEIVER_WORD_CNT 16
#define CSS_RECEIVER_PIXEL_LEN 6
#define CSS_RECEIVER_PIXEL_CNT 5
#define CSS_RECEIVER_COMP_8_BIT 8
#define CSS_RECEIVER_COMP_7_BIT 7
#define CSS_RECEIVER_COMP_6_BIT 6
#define CSI_CONFIG_WIDTH 4
/* division of gen_short data, ch_id and fmt_type over streaming data interface */
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1)
#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4
#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4
#define hrt_css_receiver_2400_4_lane_port_offset 0x100
#define hrt_css_receiver_2400_1_lane_port_offset 0x200
#define hrt_css_receiver_2400_2_lane_port_offset 0x300
#define hrt_css_receiver_2400_backend_port_offset 0x100
#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0
#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1
#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2
#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3
#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4
#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7
#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8
#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9
#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10
#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11
#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12
#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16
#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25
#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26
#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27
#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28
/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0
#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13
#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16
#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun"
#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved"
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry"
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data"
#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync"
/* Bits for CSI2_DEVICE_READY register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
/* Bits for INIT_COUNT register */
#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0
#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16
/* Bits for COUNT registers */
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8
/* Bits for RAW116_18_DATAID register */
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6
/* Bits for COMP_FORMAT register, this selects the compression data format */
#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8
#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS)
#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8
/* Bits for COMP_PREDICT register, this selects the predictor algorithm */
#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0
#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1
#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2
/* Number of bits used for the delay registers */
#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8
/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2
#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1
#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16)
#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1)
// SH Backend Register IDs
#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1
#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9
#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10
#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11
#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12
#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13
#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */
#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28
#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0
#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1
#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2
#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3
#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4
#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5
#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6
#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7
#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8
#endif /* _css_receiver_2400_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_DEFS_H_
#define _HRT_DEFS_H_
#ifndef HRTCAT
#define _HRTCAT(m, n) m##n
#define HRTCAT(m, n) _HRTCAT(m, n)
#endif
#ifndef HRTSTR
#define _HRTSTR(x) #x
#define HRTSTR(x) _HRTSTR(x)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#endif /* _HRT_DEFS_H_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _dma_v2_defs_h
#define _dma_v2_defs_h
#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels
#define _DMA_V2_CONNECTIONS_ID Connections
#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths
#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth
#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat
#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass
#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst
#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept
#define _DMA_V2_DEV_SRMD_ID DevSRMD
#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters
#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth
#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth
#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat
#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass
#define _DMA_V2_NO_PACK_ID has_no_pack
#define _DMA_V2_REG_ALIGN 4
#define _DMA_V2_REG_ADDR_BITS 2
/* Command word */
#define _DMA_V2_CMD_IDX 0
#define _DMA_V2_CMD_BITS 6
#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS)
#define _DMA_V2_CHANNEL_BITS 5
/* The command to set a parameter contains the PARAM field next */
#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_PARAM_BITS 4
/* Commands to read, write or init specific blocks contain these
three values */
#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_SPEC_DEV_A_XB_BITS 8
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_CMD_CTRL_BITS 4
/* Packing setup word */
#define _DMA_V2_CONNECTION_IDX 0
#define _DMA_V2_CONNECTION_BITS 4
#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS)
#define _DMA_V2_EXTENSION_BITS 1
/* Elements packing word */
#define _DMA_V2_ELEMENTS_IDX 0
#define _DMA_V2_ELEMENTS_BITS 8
#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS)
#define _DMA_V2_LEFT_CROPPING_BITS 8
#define _DMA_V2_WIDTH_IDX 0
#define _DMA_V2_WIDTH_BITS 16
#define _DMA_V2_HEIGHT_IDX 0
#define _DMA_V2_HEIGHT_BITS 16
#define _DMA_V2_STRIDE_IDX 0
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_SIGN_EXTEND 1
/* SLAVE address map */
#define _DMA_V2_SEL_FSM_CMD 0
#define _DMA_V2_SEL_CH_REG 1
#define _DMA_V2_SEL_CONN_GROUP 2
#define _DMA_V2_SEL_DEV_INTERF 3
#define _DMA_V2_ADDR_SEL_COMP_IDX 12
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1
#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2
#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0
#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1
#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2
#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3
#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5
#endif /* _dma_v2_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_GDC_v2_defs_h_
#define HRT_GDC_v2_defs_h_
#define HRT_GDC_IS_V2
#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
// There are just two commands possible for the GDC block:
// 1 - Configure reg
// 0 - Data token
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
// Value - Value to store to the addressed register, maximum of 24 bits
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_REG_ID_POS 25
#define HRT_GDC_REG_ID_BITS 5
#define HRT_GDC_DATA_POS 0
#define HRT_GDC_DATA_BITS 25
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_PERF_1_1_pix 0
#define HRT_GDC_PERF_2_1_pix 1
#define HRT_GDC_PERF_1_2_pix 2
#define HRT_GDC_PERF_2_2_pix 3
#define HRT_GDC_NND_MODE 0
#define HRT_GDC_BLI_MODE 1
#define HRT_GDC_BCI_MODE 2
#define HRT_GDC_LUT_MODE 3
#define HRT_GDC_SCAN_STB 0
#define HRT_GDC_SCAN_STR 1
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
#define HRT_GDC_CE_OPY_LEN 14
#define HRT_GDC_CE_OPX_POS 16
#define HRT_GDC_CE_OPX_LEN 16
// CHK_ENGINE register bit-map:
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_BPP_IDX 3
#define HRT_GDC_FRYIPXFRX_IDX 4
#define HRT_GDC_OXDIM_IDX 5
#define HRT_GDC_OYDIM_IDX 6
#define HRT_GDC_SRC_ADDR_IDX 7
#define HRT_GDC_SRC_END_ADDR_IDX 8
#define HRT_GDC_SRC_WRAP_ADDR_IDX 9
#define HRT_GDC_SRC_STRIDE_IDX 10
#define HRT_GDC_DST_ADDR_IDX 11
#define HRT_GDC_DST_STRIDE_IDX 12
#define HRT_GDC_DX_IDX 13
#define HRT_GDC_DY_IDX 14
#define HRT_GDC_P0X_IDX 15
#define HRT_GDC_P0Y_IDX 16
#define HRT_GDC_P1X_IDX 17
#define HRT_GDC_P1Y_IDX 18
#define HRT_GDC_P2X_IDX 19
#define HRT_GDC_P2Y_IDX 20
#define HRT_GDC_P3X_IDX 21
#define HRT_GDC_P3Y_IDX 22
#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc
#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT
#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right)
#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon
#define HRT_GDC_LUT_IDX 32
#endif /* HRT_GDC_v2_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gp_timer_defs_h
#define _gp_timer_defs_h
#define _HRT_GP_TIMER_REG_ALIGN 4
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
#endif /* _gp_timer_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gpio_block_defs_h_
#define _gpio_block_defs_h_
#define _HRT_GPIO_BLOCK_REG_ALIGN 4
/* R/W registers */
#define _gpio_block_reg_do_e 0
#define _gpio_block_reg_do_select 1
#define _gpio_block_reg_do_0 2
#define _gpio_block_reg_do_1 3
#define _gpio_block_reg_do_pwm_cnt_0 4
#define _gpio_block_reg_do_pwm_cnt_1 5
#define _gpio_block_reg_do_pwm_cnt_2 6
#define _gpio_block_reg_do_pwm_cnt_3 7
#define _gpio_block_reg_do_pwm_main_cnt 8
#define _gpio_block_reg_do_pwm_enable 9
#define _gpio_block_reg_di_debounce_sel 10
#define _gpio_block_reg_di_debounce_cnt_0 11
#define _gpio_block_reg_di_debounce_cnt_1 12
#define _gpio_block_reg_di_debounce_cnt_2 13
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
/* read-only registers */
#define _gpio_block_reg_di 16
#endif /* _gpio_block_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_
#define _hive_isp_css_streaming_to_mipi_types_hrt_h_
#include <streaming_to_mipi_defs.h>
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_HIVE_TYPES_H
#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
#define _HRTCAT3(m, n, o) m##n##o
#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
#define _HRTCAT4(m, n, o, p) m##n##o##p
#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
typedef unsigned int hive_bool;
#define hive_false 0
#define hive_true 1
typedef char hive_int8;
typedef short hive_int16;
typedef int hive_int32;
typedef long long hive_int64;
typedef unsigned char hive_uint8;
typedef unsigned short hive_uint16;
typedef unsigned int hive_uint32;
typedef unsigned long long hive_uint64;
/* by default assume 32 bit master port (both data and address) */
#ifndef HRT_DATA_WIDTH
#define HRT_DATA_WIDTH 32
#endif
#ifndef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 32
#endif
#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#elif HRT_DATA_WIDTH == 32
typedef hive_uint32 hrt_data;
#else
#error data width not supported
#endif
#if HRT_ADDRESS_WIDTH == 64
typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
#error adddres width not supported
#endif
/* The SP side representation of an HMM virtual address */
typedef hive_uint32 hrt_vaddress;
/* use 64 bit addresses in simulation, where possible */
typedef hive_uint64 hive_sim_address;
/* below is for csim, not for hrt, rename and move this elsewhere */
typedef unsigned int hive_uint;
typedef hive_uint32 hive_address;
typedef hive_address hive_slave_address;
typedef hive_address hive_mem_address;
/* MMIO devices */
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_hier_id;
typedef hive_hier_id hive_device_id;
typedef hive_device_id hive_proc_id;
typedef hive_device_id hive_cell_id;
typedef hive_device_id hive_host_id;
typedef hive_device_id hive_bus_id;
typedef hive_device_id hive_bridge_id;
typedef hive_device_id hive_fifo_adapter_id;
typedef hive_device_id hive_custom_device_id;
typedef hive_uint hive_slot_id;
typedef hive_uint hive_fu_id;
typedef hive_uint hive_reg_file_id;
typedef hive_uint hive_reg_id;
/* Streaming devices */
typedef hive_uint hive_outport_id;
typedef hive_uint hive_inport_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
typedef char *hive_program;
typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IF_DEFS_H
#define _IF_DEFS_H
#define HIVE_IF_FRAME_REQUEST 0xA000
#define HIVE_IF_LINES_REQUEST 0xB000
#define HIVE_IF_VECTORS_REQUEST 0xC000
#endif /* _IF_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _if_subsystem_defs_h__
#define _if_subsystem_defs_h__
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10
#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0
/* order of the input bits for the ifmt irq controller */
#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0
#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1
#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2
#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3
#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4
/* order of the input bits for the ifmt Soft reset register */
#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0
#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1
#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2
#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3
/* order of the input bits for the ifmt Soft reset register */
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3
#endif /* _if_subsystem_defs_h__ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_selector_defs_h
#define _input_selector_defs_h
#ifndef HIVE_ISP_ISEL_SEL_BITS
#define HIVE_ISP_ISEL_SEL_BITS 2
#endif
#ifndef HIVE_ISP_CH_ID_BITS
#define HIVE_ISP_CH_ID_BITS 2
#endif
#ifndef HIVE_ISP_FMT_TYPE_BITS
#define HIVE_ISP_FMT_TYPE_BITS 5
#endif
/* gp_register register id's -- Outputs */
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
#define HIVE_ISEL_GP_REGS_SOF_IDX 8
#define HIVE_ISEL_GP_REGS_EOF_IDX 9
#define HIVE_ISEL_GP_REGS_SOL_IDX 10
#define HIVE_ISEL_GP_REGS_EOL_IDX 11
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31
#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32
#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33
#define HIVE_ISEL_GP_REGS_SRST_IDX 37
#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0
#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1
#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2
#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3
/* gp_register register id's -- Inputs */
#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34
#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35
#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36
/* irq sources isel irq controller */
#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0
#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1
#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2
#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3
#define HIVE_ISEL_IRQ_NUM_IRQS 4
#endif /* _input_selector_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3
#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4
#endif /* _input_switch_2400_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_system_ctrl_defs_h
#define _input_system_ctrl_defs_h
#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */
/* --------------------------------------------------*/
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
// Number of registers
#define ISYS_CTRL_NOF_REGS 23
// Register id's of MMIO slave accesible registers
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8
#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11
#define ISYS_CTRL_INIT_REG_ID 12
#define ISYS_CTRL_LAST_COMMAND_REG_ID 13
#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16
#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22
/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_INIT_REG_RSTVAL 0
#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
/* register width value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1
/* bit definitions */
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
/*
InpSysCaptFramesAcq 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
CaptA-'b0000
CaptB-'b0001
CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt 2/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
2/1 [31:0] - external capture address
InpSysAcqFrame 2/0 [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
2/1 [31:0] - external memory read start address
InpSysOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysOverruleCmd 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
2/1 [31:0] - command token value for port opid
acknowledge tokens:
InpSysAckCFA 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
CaptA-'b0000
CaptB- 'b0001
CaptC-'b0010
[31:16] - NOF_frames
InpSysAckCFE 1/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
InpSysAckAF 1/0 [3:0] - 'b0010
InpSysAckOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysAckOverrule 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
2/1 [31:0] - acknowledge token value from port opid
*/
/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */
#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */
#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */
#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */
#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */
#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0
#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1
#define ISYS_CTRL_ACK_AF_TOKEN_ID 2
#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3
#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4
#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5
#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6
#define ISYS_CTRL_TOKEN_ID_MSB 3
#define ISYS_CTRL_TOKEN_ID_LSB 0
#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7
#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4
#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31
#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16
#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31
#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8
#define ISYS_CTRL_TOKEN_ID_IDX 0
#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */
#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */
#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */
#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */
#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */
#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */
#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_CAPT_ACK 16
#endif /* _input_system_ctrl_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_system_defs_h
#define _input_system_defs_h
/* csi controller modes */
#define HIVE_CSI_CONFIG_MAIN 0
#define HIVE_CSI_CONFIG_STEREO1 4
#define HIVE_CSI_CONFIG_STEREO2 8
/* general purpose register IDs */
/* Stream Multicast select modes */
#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0
#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1
#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2
/* Stream Mux select modes */
#define HIVE_ISYS_GPREG_MUX_IDX 3
/* streaming monitor status and control */
#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4
#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5
#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6
#define HIVE_ISYS_GPREG_SRST_IDX 7
#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8
#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9
#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10
/* Bit numbers of the soft reset register */
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2
#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3
#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4
#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5
#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6
#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7
#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8
#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9
/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14
/* -- */
#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15
#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16
#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17
#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv
#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23
#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2
#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3
#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4
#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5
/* streaming monitor port id's */
#define HIVE_ISYS_STR_MON_PORT_CAPA 0
#define HIVE_ISYS_STR_MON_PORT_CAPB 1
#define HIVE_ISYS_STR_MON_PORT_CAPC 2
#define HIVE_ISYS_STR_MON_PORT_ACQ 3
#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4
#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5
#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6
#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7
#define HIVE_ISYS_STR_MON_PORT_PIXA 8
#define HIVE_ISYS_STR_MON_PORT_PIXB 9
/* interrupt bit ID's */
#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0
#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1
#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2
#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3
#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4
#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5
#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6
#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7
/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/
#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8
#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9
/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/
#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10
#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11
/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/
#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12
/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/
#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13
#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14
#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15
#define HIVE_ISYS_IRQ_CIO2AHB 16
#define HIVE_ISYS_IRQ_DMA_BIT_ID 17
#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18
#define HIVE_ISYS_IRQ_NUM_BITS 19
/* DMA */
#define HIVE_ISYS_DMA_CHANNEL 0
#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0
#define HIVE_ISYS_DMA_HEIGHT 1
#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */
#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */
#define HIVE_ISYS_DMA_CROP 0 /* no cropping */
#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */
#endif /* _input_system_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _irq_controller_defs_h
#define _irq_controller_defs_h
#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0
#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1
#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2
#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3
#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4
#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5
#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
#endif /* _irq_controller_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp2400_support_h
#define _isp2400_support_h
#ifndef ISP2400_VECTOR_TYPES
/* This typedef is to be able to include hive header files
in the host code which is useful in crun */
typedef char *tmemvectors, *tmemvectoru, *tvector;
#endif
#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val)
#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val)
#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem)
#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem)
#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell))
#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell))
#if ISP_HAS_HIST
#define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram)
#define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell))
#endif
#endif /* _isp2400_support_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp_acquisition_defs_h
#define _isp_acquisition_defs_h
#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
/* --------------------------------------------------*/
#define NOF_ACQ_IRQS 1
/* --------------------------------------------------*/
/* FSM */
/* --------------------------------------------------*/
#define MEM2STREAM_FSM_STATE_BITS 2
#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
#define NOF_ACQ_REGS 12
// Register id's of MMIO slave accesible registers
#define ACQ_START_ADDR_REG_ID 0
#define ACQ_MEM_REGION_SIZE_REG_ID 1
#define ACQ_NUM_MEM_REGIONS_REG_ID 2
#define ACQ_INIT_REG_ID 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5
#define ACQ_LAST_COMMAND_REG_ID 6
#define ACQ_NEXT_COMMAND_REG_ID 7
#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9
#define ACQ_FSM_STATE_INFO_REG_ID 10
#define ACQ_INT_CNTR_INFO_REG_ID 11
// Register width
#define ACQ_START_ADDR_REG_WIDTH 9
#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ACQ_INIT_REG_WIDTH 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define ACQ_LAST_COMMAND_REG_WIDTH 32
#define ACQ_NEXT_COMMAND_REG_WIDTH 32
#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH 32
/* register reset value */
#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define ACQ_LAST_COMMAND_REG_RSTVAL 0
#define ACQ_NEXT_COMMAND_REG_RSTVAL 0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
/* bit definitions */
#define ACQ_INIT_RST_REG_BIT 0
#define ACQ_INIT_RESYNC_BIT 2
#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT
#define ACQ_INIT_RST_BITS 1
#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT
#define ACQ_INIT_RESYNC_BITS 1
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB 0
#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4
#define ACQ_TOKEN_ID_IDX 0
#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH
#define ACQ_INIT_CMD_INIT_IDX 4
#define ACQ_INIT_CMD_INIT_BITS 3
#define ACQ_CMD_START_ADDR_IDX 4
#define ACQ_CMD_START_ADDR_BITS 9
#define ACQ_CMD_NOFWORDS_IDX 13
#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_MEM_REGION_ID_IDX 22
#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_PACKET_LENGTH_TOKEN_MSB 21
#define ACQ_PACKET_LENGTH_TOKEN_LSB 13
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4
#define ACQ_PACKET_CH_ID_TOKEN_MSB 11
#define ACQ_PACKET_CH_ID_TOKEN_LSB 10
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */
/* Command tokens IDs */
#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b
#define ACQ_READ_REGION_TOKEN_ID 1 //0001b
#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_INIT_TOKEN_ID 8 //1000b
/* Acknowledge token IDs */
#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b
#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b
#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b
#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b
#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b
#define ACQ_TOKEN_MEMREGIONID_MSB 30
#define ACQ_TOKEN_MEMREGIONID_LSB 22
#define ACQ_TOKEN_NOFWORDS_MSB 21
#define ACQ_TOKEN_NOFWORDS_LSB 13
#define ACQ_TOKEN_STARTADDR_MSB 12
#define ACQ_TOKEN_STARTADDR_LSB 4
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define WORD_COUNT_WIDTH 16
#define PKT_CODE_WIDTH 6
#define CHN_NO_WIDTH 2
#define ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
#define EOF_CODE 1
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define ACQ_START_OF_FRAME 0
#define ACQ_END_OF_FRAME 1
#define ACQ_START_OF_LINE 2
#define ACQ_END_OF_LINE 3
#define ACQ_LINE_PAYLOAD 4
#define ACQ_GEN_SH_PKT 5
/* bit definition */
#define ACQ_PKT_TYPE_IDX 16
#define ACQ_PKT_TYPE_BITS 6
#define ACQ_PKT_SOP_IDX 32
#define ACQ_WORD_CNT_IDX 0
#define ACQ_WORD_CNT_BITS 16
#define ACQ_PKT_INFO_IDX 16
#define ACQ_PKT_INFO_BITS 8
#define ACQ_HEADER_DATA_IDX 0
#define ACQ_HEADER_DATA_BITS 16
#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX
#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS
#define ACQ_ACK_NOFWORDS_IDX 13
#define ACQ_ACK_NOFWORDS_BITS 9
#define ACQ_ACK_PKT_LEN_IDX 4
#define ACQ_ACK_PKT_LEN_BITS 16
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */
#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
#define ACQ_SOL_DATA 2 /* 00 0010 line start */
#define ACQ_EOL_DATA 3 /* 00 0011 line end */
#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RESERVED_DATA_TYPE_MIN 56
#define ACQ_RESERVED_DATA_TYPE_MAX 63
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23
#define ACQ_YUV_RESERVED_DATA_TYPE 27
#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37
#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39
#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46
#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47
/* --------------------------------------------------*/
#endif /* _isp_acquisition_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp_capture_defs_h
#define _isp_capture_defs_h
#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */
#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8)
#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
/* --------------------------------------------------*/
#define NOF_IRQS 2
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
// Number of registers
#define CAPT_NOF_REGS 16
// Register id's of MMIO slave accesible registers
#define CAPT_START_MODE_REG_ID 0
#define CAPT_START_ADDR_REG_ID 1
#define CAPT_MEM_REGION_SIZE_REG_ID 2
#define CAPT_NUM_MEM_REGIONS_REG_ID 3
#define CAPT_INIT_REG_ID 4
#define CAPT_START_REG_ID 5
#define CAPT_STOP_REG_ID 6
#define CAPT_PACKET_LENGTH_REG_ID 7
#define CAPT_RECEIVED_LENGTH_REG_ID 8
#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_NEXT_COMMAND_REG_ID 12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14
#define CAPT_FSM_STATE_INFO_REG_ID 15
// Register width
#define CAPT_START_MODE_REG_WIDTH 1
#define CAPT_START_REG_WIDTH 1
#define CAPT_STOP_REG_WIDTH 1
/* --------------------------------------------------*/
/* FSM */
/* --------------------------------------------------*/
#define CAPT_WRITE2MEM_FSM_STATE_BITS 2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3
#define CAPT_PACKET_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define CAPT_LAST_COMMAND_REG_WIDTH 32
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))
/* register reset value */
#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_ADDR_REG_RSTVAL 0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128
#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_INIT_REG_RSTVAL 0
#define CAPT_START_REG_RSTVAL 0
#define CAPT_STOP_REG_RSTVAL 0
#define CAPT_PACKET_LENGTH_REG_RSTVAL 0
#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0
#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define CAPT_LAST_COMMAND_REG_RSTVAL 0
#define CAPT_NEXT_COMMAND_REG_RSTVAL 0
#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0
#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0
/* bit definitions */
#define CAPT_INIT_RST_REG_BIT 0
#define CAPT_INIT_FLUSH_BIT 1
#define CAPT_INIT_RESYNC_BIT 2
#define CAPT_INIT_RESTART_BIT 3
#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4
#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS 1
#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT
#define CAPT_INIT_FLUSH_BITS 1
#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT
#define CAPT_INIT_RESYNC_BITS 1
#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT
#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define CAPT_TOKEN_ID_LSB 0
#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */
/* Command tokens IDs */
#define CAPT_START_TOKEN_ID 0 /* 0000b */
#define CAPT_STOP_TOKEN_ID 1 /* 0001b */
#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */
#define CAPT_INIT_TOKEN_ID 8 /* 1000b */
#define CAPT_START_TOKEN_BIT 0
#define CAPT_STOP_TOKEN_BIT 0
#define CAPT_FREEZE_TOKEN_BIT 0
#define CAPT_RESUME_TOKEN_BIT 0
#define CAPT_INIT_TOKEN_BIT 0
/* Acknowledge token IDs */
#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */
#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */
#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */
#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */
#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */
#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */
#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */
#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */
#define CAPT_PACKET_LENGTH_TOKEN_MSB 19
#define CAPT_PACKET_LENGTH_TOKEN_LSB 4
#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20
#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20
#define CAPT_PACKET_CH_ID_TOKEN_MSB 27
#define CAPT_PACKET_CH_ID_TOKEN_LSB 26
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
/* bit definition */
#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB
#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1)
#define CAPT_SOP_IDX 32
#define CAPT_SOP_BITS 1
#define CAPT_PKT_INFO_IDX 16
#define CAPT_PKT_INFO_BITS 8
#define CAPT_PKT_TYPE_IDX 0
#define CAPT_PKT_TYPE_BITS 6
#define CAPT_HEADER_DATA_IDX 0
#define CAPT_HEADER_DATA_BITS 16
#define CAPT_PKT_DATA_IDX 0
#define CAPT_PKT_DATA_BITS 32
#define CAPT_WORD_CNT_IDX 0
#define CAPT_WORD_CNT_BITS 16
#define CAPT_ACK_TOKEN_ID_IDX 0
#define CAPT_ACK_TOKEN_ID_BITS 4
//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB
//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1)
//#define CAPT_ACK_PKT_INFO_IDX 20
//#define CAPT_ACK_PKT_INFO_BITS 8
//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */
//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */
#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB
#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1)
#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB
#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1)
#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB
#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1)
#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB
#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1)
#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB
#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1)
#define CAPT_INIT_TOKEN_INIT_IDX 4
#define CAPT_INIT_TOKEN_INIT_BITS 22
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define CAPT_WORD_COUNT_WIDTH 16
#define CAPT_PKT_CODE_WIDTH 6
#define CAPT_CHN_NO_WIDTH 2
#define CAPT_ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define CAPT_START_OF_FRAME 0
#define CAPT_END_OF_FRAME 1
#define CAPT_START_OF_LINE 2
#define CAPT_END_OF_LINE 3
#define CAPT_LINE_PAYLOAD 4
#define CAPT_GEN_SH_PKT 5
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */
#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
#define CAPT_SOL_DATA 2 /* 00 0010 line start */
#define CAPT_EOL_DATA 3 /* 00 0011 line end */
#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RESERVED_DATA_TYPE_MIN 56
#define CAPT_RESERVED_DATA_TYPE_MAX 63
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23
#define CAPT_YUV_RESERVED_DATA_TYPE 27
#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37
#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39
#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46
#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47
/* --------------------------------------------------*/
/* Capture Unit State */
/* --------------------------------------------------*/
#define CAPT_FREE_RUN 0
#define CAPT_NO_SYNC 1
#define CAPT_SYNC_SWP 2
#define CAPT_SYNC_MWP 3
#define CAPT_SYNC_WAIT 4
#define CAPT_FREEZE 5
#define CAPT_RUN 6
/* --------------------------------------------------*/
#endif /* _isp_capture_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _mmu_defs_h
#define _mmu_defs_h
#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0
#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1
#define _HRT_MMU_REG_ALIGN 4
#endif /* _mmu_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _scalar_processor_2400_params_h
#define _scalar_processor_2400_params_h
#include "cell_params.h"
#endif /* _scalar_processor_2400_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _ST2MEM_DEFS_H
#define _ST2MEM_DEFS_H
#define _STR2MEM_CRUN_BIT 0x100000
#define _STR2MEM_CMD_BITS 0x0F0000
#define _STR2MEM_COUNT_BITS 0x00FFFF
#define _STR2MEM_BLOCKS_CMD 0xA0000
#define _STR2MEM_PACKETS_CMD 0xB0000
#define _STR2MEM_BYTES_CMD 0xC0000
#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
#define _STR2MEM_SOFT_RESET_REG_ID 0
#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1
#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2
#define _STR2MEM_BIT_SWAPPING_REG_ID 3
#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4
#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5
#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6
#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7
#define _STR2MEM_EN_STAT_UPDATE_ID 8
#define _STR2MEM_REG_ALIGN 4
#endif /* _ST2MEM_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _streaming_to_mipi_defs_h
#define _streaming_to_mipi_defs_h
#define HIVE_STR_TO_MIPI_VALID_A_BIT 0
#define HIVE_STR_TO_MIPI_VALID_B_BIT 1
#define HIVE_STR_TO_MIPI_SOL_BIT 2
#define HIVE_STR_TO_MIPI_EOL_BIT 3
#define HIVE_STR_TO_MIPI_SOF_BIT 4
#define HIVE_STR_TO_MIPI_EOF_BIT 5
#define HIVE_STR_TO_MIPI_CH_ID_LSB 6
#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1)
#endif /* _streaming_to_mipi_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _timed_controller_defs_h
#define _timed_controller_defs_h
#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
#endif /* _timed_controller_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_VERSION_H
#define HRT_VERSION_H
#define HRT_VERSION_MAJOR 1
#define HRT_VERSION_MINOR 4
#define HRT_VERSION 1_4
#endif
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifdef IA_CSS_INCLUDE_CONFIGURATIONS
#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h"
#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h"
#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h"
#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h"
#include "isp/kernels/output/output_1.0/ia_css_output.host.h"
#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h"
#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h"
/* ISP2401 */
#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h"
#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h"
#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h"
#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_CONFIG_H
#define _IA_CSS_ISP_CONFIG_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_configuration_ids {
IA_CSS_ITERATOR_CONFIG_ID,
IA_CSS_COPY_OUTPUT_CONFIG_ID,
IA_CSS_CROP_CONFIG_ID,
IA_CSS_FPN_CONFIG_ID,
IA_CSS_DVS_CONFIG_ID,
IA_CSS_QPLANE_CONFIG_ID,
IA_CSS_OUTPUT0_CONFIG_ID,
IA_CSS_OUTPUT1_CONFIG_ID,
IA_CSS_OUTPUT_CONFIG_ID,
IA_CSS_RAW_CONFIG_ID,
IA_CSS_TNR_CONFIG_ID,
IA_CSS_REF_CONFIG_ID,
IA_CSS_VF_CONFIG_ID,
/* ISP2401 */
IA_CSS_SC_CONFIG_ID,
IA_CSS_NUM_CONFIGURATION_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_config_memory_offsets {
struct {
struct ia_css_isp_parameter iterator;
struct ia_css_isp_parameter copy_output;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter dvs;
struct ia_css_isp_parameter qplane;
struct ia_css_isp_parameter output0;
struct ia_css_isp_parameter output1;
struct ia_css_isp_parameter output;
#ifdef ISP2401
struct ia_css_isp_parameter sc;
#endif
struct ia_css_isp_parameter raw;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
struct ia_css_isp_parameter vf;
} dmem;
};
#if defined(IA_CSS_INCLUDE_CONFIGURATIONS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_iterator(
const struct ia_css_binary *binary,
const struct ia_css_iterator_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_copy_output(
const struct ia_css_binary *binary,
const struct ia_css_copy_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_crop(
const struct ia_css_binary *binary,
const struct ia_css_crop_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_fpn(
const struct ia_css_binary *binary,
const struct ia_css_fpn_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_dvs(
const struct ia_css_binary *binary,
const struct ia_css_dvs_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_qplane(
const struct ia_css_binary *binary,
const struct ia_css_qplane_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output0(
const struct ia_css_binary *binary,
const struct ia_css_output0_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output1(
const struct ia_css_binary *binary,
const struct ia_css_output1_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output(
const struct ia_css_binary *binary,
const struct ia_css_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
/* ISP2401 */
void
ia_css_configure_sc(
const struct ia_css_binary *binary,
const struct ia_css_sc_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_raw(
const struct ia_css_binary *binary,
const struct ia_css_raw_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_tnr(
const struct ia_css_binary *binary,
const struct ia_css_tnr_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_ref(
const struct ia_css_binary *binary,
const struct ia_css_ref_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_vf(
const struct ia_css_binary *binary,
const struct ia_css_vf_configuration *config_dmem);
#endif /* IA_CSS_INCLUDE_CONFIGURATION */
#endif /* _IA_CSS_ISP_CONFIG_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_PARAM_H
#define _IA_CSS_ISP_PARAM_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_parameter_ids {
IA_CSS_AA_ID,
IA_CSS_ANR_ID,
IA_CSS_ANR2_ID,
IA_CSS_BH_ID,
IA_CSS_CNR_ID,
IA_CSS_CROP_ID,
IA_CSS_CSC_ID,
IA_CSS_DP_ID,
IA_CSS_BNR_ID,
IA_CSS_DE_ID,
IA_CSS_ECD_ID,
IA_CSS_FORMATS_ID,
IA_CSS_FPN_ID,
IA_CSS_GC_ID,
IA_CSS_CE_ID,
IA_CSS_YUV2RGB_ID,
IA_CSS_RGB2YUV_ID,
IA_CSS_R_GAMMA_ID,
IA_CSS_G_GAMMA_ID,
IA_CSS_B_GAMMA_ID,
IA_CSS_UDS_ID,
IA_CSS_RAA_ID,
IA_CSS_S3A_ID,
IA_CSS_OB_ID,
IA_CSS_OUTPUT_ID,
IA_CSS_SC_ID,
IA_CSS_BDS_ID,
IA_CSS_TNR_ID,
IA_CSS_MACC_ID,
IA_CSS_SDIS_HORICOEF_ID,
IA_CSS_SDIS_VERTCOEF_ID,
IA_CSS_SDIS_HORIPROJ_ID,
IA_CSS_SDIS_VERTPROJ_ID,
IA_CSS_SDIS2_HORICOEF_ID,
IA_CSS_SDIS2_VERTCOEF_ID,
IA_CSS_SDIS2_HORIPROJ_ID,
IA_CSS_SDIS2_VERTPROJ_ID,
IA_CSS_WB_ID,
IA_CSS_NR_ID,
IA_CSS_YEE_ID,
IA_CSS_YNR_ID,
IA_CSS_FC_ID,
IA_CSS_CTC_ID,
IA_CSS_XNR_TABLE_ID,
IA_CSS_XNR_ID,
IA_CSS_XNR3_ID,
IA_CSS_NUM_PARAMETER_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter anr;
struct ia_css_isp_parameter bh;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter csc;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter bnr;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ecd;
struct ia_css_isp_parameter formats;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter gc;
struct ia_css_isp_parameter ce;
struct ia_css_isp_parameter yuv2rgb;
struct ia_css_isp_parameter rgb2yuv;
struct ia_css_isp_parameter uds;
struct ia_css_isp_parameter raa;
struct ia_css_isp_parameter s3a;
struct ia_css_isp_parameter ob;
struct ia_css_isp_parameter output;
struct ia_css_isp_parameter sc;
struct ia_css_isp_parameter bds;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter macc;
struct ia_css_isp_parameter sdis_horiproj;
struct ia_css_isp_parameter sdis_vertproj;
struct ia_css_isp_parameter sdis2_horiproj;
struct ia_css_isp_parameter sdis2_vertproj;
struct ia_css_isp_parameter wb;
struct ia_css_isp_parameter nr;
struct ia_css_isp_parameter yee;
struct ia_css_isp_parameter ynr;
struct ia_css_isp_parameter fc;
struct ia_css_isp_parameter ctc;
struct ia_css_isp_parameter xnr;
struct ia_css_isp_parameter xnr3;
struct ia_css_isp_parameter get;
struct ia_css_isp_parameter put;
} dmem;
struct {
struct ia_css_isp_parameter anr2;
struct ia_css_isp_parameter ob;
struct ia_css_isp_parameter sdis_horicoef;
struct ia_css_isp_parameter sdis_vertcoef;
struct ia_css_isp_parameter sdis2_horicoef;
struct ia_css_isp_parameter sdis2_vertcoef;
/* ISP2401 */
struct ia_css_isp_parameter xnr3;
} vmem;
struct {
struct ia_css_isp_parameter bh;
} hmem0;
struct {
struct ia_css_isp_parameter gc;
struct ia_css_isp_parameter g_gamma;
struct ia_css_isp_parameter xnr_table;
} vamem1;
struct {
struct ia_css_isp_parameter r_gamma;
struct ia_css_isp_parameter ctc;
} vamem0;
struct {
struct ia_css_isp_parameter b_gamma;
} vamem2;
};
#if defined(IA_CSS_INCLUDE_PARAMETERS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/gencode.c:gen_param_process_table() */
struct ia_css_pipeline_stage; /* forward declaration */
extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_dp_config(struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_wb_config(struct ia_css_isp_parameters *params,
const struct ia_css_wb_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_tnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ob_config(struct ia_css_isp_parameters *params,
const struct ia_css_ob_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_de_config(struct ia_css_isp_parameters *params,
const struct ia_css_de_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_anr_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_thres *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ce_config(struct ia_css_isp_parameters *params,
const struct ia_css_ce_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
const struct ia_css_ecd_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ynr_config(struct ia_css_isp_parameters *params,
const struct ia_css_ynr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_fc_config(struct ia_css_isp_parameters *params,
const struct ia_css_fc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_cnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_cnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_macc_config(struct ia_css_isp_parameters *params,
const struct ia_css_macc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ctc_config(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_aa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_csc_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_gc_config(struct ia_css_isp_parameters *params,
const struct ia_css_gc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_formats_config(struct ia_css_isp_parameters *params,
const struct ia_css_formats_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr3_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr3_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_s3a_config(struct ia_css_isp_parameters *params,
const struct ia_css_3a_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_output_config(struct ia_css_isp_parameters *params,
const struct ia_css_output_config *config);
/* Code generated by genparam/gencode.c:gen_global_access_function() */
void
ia_css_get_configs(struct ia_css_isp_parameters *params,
const struct ia_css_isp_config *config)
;
/* Code generated by genparam/gencode.c:gen_global_access_function() */
void
ia_css_set_configs(struct ia_css_isp_parameters *params,
const struct ia_css_isp_config *config)
;
#endif /* IA_CSS_INCLUDE_PARAMETER */
#endif /* _IA_CSS_ISP_PARAM_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#define IA_CSS_INCLUDE_STATES
#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h"
#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h"
#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h"
#include "isp/kernels/de/de_1.0/ia_css_de.host.h"
#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h"
#include "isp/kernels/dpc2/ia_css_dpc2.host.h"
#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h"
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_STATE_H
#define _IA_CSS_ISP_STATE_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_state_ids {
IA_CSS_AA_STATE_ID,
IA_CSS_CNR_STATE_ID,
IA_CSS_CNR2_STATE_ID,
IA_CSS_DP_STATE_ID,
IA_CSS_DE_STATE_ID,
IA_CSS_TNR_STATE_ID,
IA_CSS_REF_STATE_ID,
IA_CSS_YNR_STATE_ID,
IA_CSS_NUM_STATE_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_state_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter cnr2;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ynr;
} vmem;
struct {
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
} dmem;
};
#if defined(IA_CSS_INCLUDE_STATES)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genstate.c:gen_state_init_table() */
extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(
const struct ia_css_binary *binary);
#endif /* IA_CSS_INCLUDE_STATE */
#endif /* _IA_CSS_ISP_STATE_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/bits.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_BITS_H
#define _HRT_BITS_H
#include "defs.h"
#define _hrt_ones(n) HRTCAT(_hrt_ones_, n)
#define _hrt_ones_0x0 0x00000000U
#define _hrt_ones_0x1 0x00000001U
#define _hrt_ones_0x2 0x00000003U
#define _hrt_ones_0x3 0x00000007U
#define _hrt_ones_0x4 0x0000000FU
#define _hrt_ones_0x5 0x0000001FU
#define _hrt_ones_0x6 0x0000003FU
#define _hrt_ones_0x7 0x0000007FU
#define _hrt_ones_0x8 0x000000FFU
#define _hrt_ones_0x9 0x000001FFU
#define _hrt_ones_0xA 0x000003FFU
#define _hrt_ones_0xB 0x000007FFU
#define _hrt_ones_0xC 0x00000FFFU
#define _hrt_ones_0xD 0x00001FFFU
#define _hrt_ones_0xE 0x00003FFFU
#define _hrt_ones_0xF 0x00007FFFU
#define _hrt_ones_0x10 0x0000FFFFU
#define _hrt_ones_0x11 0x0001FFFFU
#define _hrt_ones_0x12 0x0003FFFFU
#define _hrt_ones_0x13 0x0007FFFFU
#define _hrt_ones_0x14 0x000FFFFFU
#define _hrt_ones_0x15 0x001FFFFFU
#define _hrt_ones_0x16 0x003FFFFFU
#define _hrt_ones_0x17 0x007FFFFFU
#define _hrt_ones_0x18 0x00FFFFFFU
#define _hrt_ones_0x19 0x01FFFFFFU
#define _hrt_ones_0x1A 0x03FFFFFFU
#define _hrt_ones_0x1B 0x07FFFFFFU
#define _hrt_ones_0x1C 0x0FFFFFFFU
#define _hrt_ones_0x1D 0x1FFFFFFFU
#define _hrt_ones_0x1E 0x3FFFFFFFU
#define _hrt_ones_0x1F 0x7FFFFFFFU
#define _hrt_ones_0x20 0xFFFFFFFFU
#define _hrt_ones_0 _hrt_ones_0x0
#define _hrt_ones_1 _hrt_ones_0x1
#define _hrt_ones_2 _hrt_ones_0x2
#define _hrt_ones_3 _hrt_ones_0x3
#define _hrt_ones_4 _hrt_ones_0x4
#define _hrt_ones_5 _hrt_ones_0x5
#define _hrt_ones_6 _hrt_ones_0x6
#define _hrt_ones_7 _hrt_ones_0x7
#define _hrt_ones_8 _hrt_ones_0x8
#define _hrt_ones_9 _hrt_ones_0x9
#define _hrt_ones_10 _hrt_ones_0xA
#define _hrt_ones_11 _hrt_ones_0xB
#define _hrt_ones_12 _hrt_ones_0xC
#define _hrt_ones_13 _hrt_ones_0xD
#define _hrt_ones_14 _hrt_ones_0xE
#define _hrt_ones_15 _hrt_ones_0xF
#define _hrt_ones_16 _hrt_ones_0x10
#define _hrt_ones_17 _hrt_ones_0x11
#define _hrt_ones_18 _hrt_ones_0x12
#define _hrt_ones_19 _hrt_ones_0x13
#define _hrt_ones_20 _hrt_ones_0x14
#define _hrt_ones_21 _hrt_ones_0x15
#define _hrt_ones_22 _hrt_ones_0x16
#define _hrt_ones_23 _hrt_ones_0x17
#define _hrt_ones_24 _hrt_ones_0x18
#define _hrt_ones_25 _hrt_ones_0x19
#define _hrt_ones_26 _hrt_ones_0x1A
#define _hrt_ones_27 _hrt_ones_0x1B
#define _hrt_ones_28 _hrt_ones_0x1C
#define _hrt_ones_29 _hrt_ones_0x1D
#define _hrt_ones_30 _hrt_ones_0x1E
#define _hrt_ones_31 _hrt_ones_0x1F
#define _hrt_ones_32 _hrt_ones_0x20
#define _hrt_mask(b, n) \
(_hrt_ones(n) << (b))
#define _hrt_get_bits(w, b, n) \
(((w) >> (b)) & _hrt_ones(n))
#define _hrt_set_bits(w, b, n, v) \
(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
(((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
_hrt_set_bits(w, 16, 16, v)
#endif /* _HRT_BITS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/cell_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _cell_params_h
#define _cell_params_h
#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/
#define SP_ICACHE_TAG_BITS 4 /*size of tag*/
#define SP_ICACHE_SET_BITS 8 /* 256 sets*/
#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
(SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_2_DEPTH 0
#define SP_FIFO_3_DEPTH 0
#define SP_FIFO_4_DEPTH 0
#define SP_FIFO_5_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/css_receiver_2400_common_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _css_receiver_2400_common_defs_h_
#define _css_receiver_2400_common_defs_h_
#ifndef _mipi_backend_common_defs_h_
#define _mipi_backend_common_defs_h_
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
/* Definition of format_types at the interface CSS --> input_selector*/
/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1
#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22
#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2
#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16
#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6
#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
/* Pixel Extractor config */
#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
#endif /* _css_receiver_2400_common_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/css_receiver_2400_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _css_receiver_2400_defs_h_
#define _css_receiver_2400_defs_h_
#include "css_receiver_2400_common_defs.h"
#define CSS_RECEIVER_DATA_WIDTH 8
#define CSS_RECEIVER_RX_TRIG 4
#define CSS_RECEIVER_RF_WORD 32
#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10
#define CSS_RECEIVER_CSI_RF_ADDR 4
#define CSS_RECEIVER_DATA_OUT 12
#define CSS_RECEIVER_CHN_NO 2
#define CSS_RECEIVER_DWORD_CNT 11
#define CSS_RECEIVER_FORMAT_TYP 5
#define CSS_RECEIVER_HRESPONSE 2
#define CSS_RECEIVER_STATE_WIDTH 3
#define CSS_RECEIVER_FIFO_DAT 32
#define CSS_RECEIVER_CNT_VAL 2
#define CSS_RECEIVER_PRED10_VAL 10
#define CSS_RECEIVER_PRED12_VAL 12
#define CSS_RECEIVER_CNT_WIDTH 8
#define CSS_RECEIVER_WORD_CNT 16
#define CSS_RECEIVER_PIXEL_LEN 6
#define CSS_RECEIVER_PIXEL_CNT 5
#define CSS_RECEIVER_COMP_8_BIT 8
#define CSS_RECEIVER_COMP_7_BIT 7
#define CSS_RECEIVER_COMP_6_BIT 6
#define CSI_CONFIG_WIDTH 4
/* division of gen_short data, ch_id and fmt_type over streaming data interface */
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1)
#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4
#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4
#define hrt_css_receiver_2400_4_lane_port_offset 0x100
#define hrt_css_receiver_2400_1_lane_port_offset 0x200
#define hrt_css_receiver_2400_2_lane_port_offset 0x300
#define hrt_css_receiver_2400_backend_port_offset 0x100
#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0
#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1
#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2
#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3
#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4
#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7
#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8
#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9
#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10
#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11
#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12
#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16
#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25
#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26
#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27
#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28
/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0
#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13
#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16
#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun"
#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved"
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry"
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data"
#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync"
/* Bits for CSI2_DEVICE_READY register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
/* Bits for INIT_COUNT register */
#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0
#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16
/* Bits for COUNT registers */
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8
/* Bits for RAW116_18_DATAID register */
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6
/* Bits for COMP_FORMAT register, this selects the compression data format */
#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8
#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS)
#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8
/* Bits for COMP_PREDICT register, this selects the predictor algorithm */
#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0
#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1
#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2
/* Number of bits used for the delay registers */
#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8
/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2
#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1
#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16)
#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1)
// SH Backend Register IDs
#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1
#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9
#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10
#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11
#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12
#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13
#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */
#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28
#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0
#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1
#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2
#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3
#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4
#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5
#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6
#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7
#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8
#endif /* _css_receiver_2400_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_DEFS_H_
#define _HRT_DEFS_H_
#ifndef HRTCAT
#define _HRTCAT(m, n) m##n
#define HRTCAT(m, n) _HRTCAT(m, n)
#endif
#ifndef HRTSTR
#define _HRTSTR(x) #x
#define HRTSTR(x) _HRTSTR(x)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#endif /* _HRT_DEFS_H_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/dma_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _dma_v2_defs_h
#define _dma_v2_defs_h
#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels
#define _DMA_V2_CONNECTIONS_ID Connections
#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths
#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth
#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat
#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass
#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst
#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept
#define _DMA_V2_DEV_SRMD_ID DevSRMD
#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters
#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth
#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth
#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat
#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass
#define _DMA_V2_NO_PACK_ID has_no_pack
#define _DMA_V2_REG_ALIGN 4
#define _DMA_V2_REG_ADDR_BITS 2
/* Command word */
#define _DMA_V2_CMD_IDX 0
#define _DMA_V2_CMD_BITS 6
#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS)
#define _DMA_V2_CHANNEL_BITS 5
/* The command to set a parameter contains the PARAM field next */
#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_PARAM_BITS 4
/* Commands to read, write or init specific blocks contain these
three values */
#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_SPEC_DEV_A_XB_BITS 8
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_CMD_CTRL_BITS 4
/* Packing setup word */
#define _DMA_V2_CONNECTION_IDX 0
#define _DMA_V2_CONNECTION_BITS 4
#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS)
#define _DMA_V2_EXTENSION_BITS 1
/* Elements packing word */
#define _DMA_V2_ELEMENTS_IDX 0
#define _DMA_V2_ELEMENTS_BITS 8
#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS)
#define _DMA_V2_LEFT_CROPPING_BITS 8
#define _DMA_V2_WIDTH_IDX 0
#define _DMA_V2_WIDTH_BITS 16
#define _DMA_V2_HEIGHT_IDX 0
#define _DMA_V2_HEIGHT_BITS 16
#define _DMA_V2_STRIDE_IDX 0
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_SIGN_EXTEND 1
/* SLAVE address map */
#define _DMA_V2_SEL_FSM_CMD 0
#define _DMA_V2_SEL_CH_REG 1
#define _DMA_V2_SEL_CONN_GROUP 2
#define _DMA_V2_SEL_DEV_INTERF 3
#define _DMA_V2_ADDR_SEL_COMP_IDX 12
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1
#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2
#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0
#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1
#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2
#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3
#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5
#endif /* _dma_v2_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gdc_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_GDC_v2_defs_h_
#define HRT_GDC_v2_defs_h_
#define HRT_GDC_IS_V2
#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
// There are just two commands possible for the GDC block:
// 1 - Configure reg
// 0 - Data token
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
// Value - Value to store to the addressed register, maximum of 24 bits
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_REG_ID_POS 25
#define HRT_GDC_REG_ID_BITS 5
#define HRT_GDC_DATA_POS 0
#define HRT_GDC_DATA_BITS 25
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_PERF_1_1_pix 0
#define HRT_GDC_PERF_2_1_pix 1
#define HRT_GDC_PERF_1_2_pix 2
#define HRT_GDC_PERF_2_2_pix 3
#define HRT_GDC_NND_MODE 0
#define HRT_GDC_BLI_MODE 1
#define HRT_GDC_BCI_MODE 2
#define HRT_GDC_LUT_MODE 3
#define HRT_GDC_SCAN_STB 0
#define HRT_GDC_SCAN_STR 1
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
#define HRT_GDC_CE_OPY_LEN 14
#define HRT_GDC_CE_OPX_POS 16
#define HRT_GDC_CE_OPX_LEN 16
// CHK_ENGINE register bit-map:
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_BPP_IDX 3
#define HRT_GDC_FRYIPXFRX_IDX 4
#define HRT_GDC_OXDIM_IDX 5
#define HRT_GDC_OYDIM_IDX 6
#define HRT_GDC_SRC_ADDR_IDX 7
#define HRT_GDC_SRC_END_ADDR_IDX 8
#define HRT_GDC_SRC_WRAP_ADDR_IDX 9
#define HRT_GDC_SRC_STRIDE_IDX 10
#define HRT_GDC_DST_ADDR_IDX 11
#define HRT_GDC_DST_STRIDE_IDX 12
#define HRT_GDC_DX_IDX 13
#define HRT_GDC_DY_IDX 14
#define HRT_GDC_P0X_IDX 15
#define HRT_GDC_P0Y_IDX 16
#define HRT_GDC_P1X_IDX 17
#define HRT_GDC_P1Y_IDX 18
#define HRT_GDC_P2X_IDX 19
#define HRT_GDC_P2Y_IDX 20
#define HRT_GDC_P3X_IDX 21
#define HRT_GDC_P3Y_IDX 22
#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc
#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT
#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right)
#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon
#define HRT_GDC_LUT_IDX 32
#endif /* HRT_GDC_v2_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_timer_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gp_timer_defs_h
#define _gp_timer_defs_h
#define _HRT_GP_TIMER_REG_ALIGN 4
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
#endif /* _gp_timer_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gpio_block_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gpio_block_defs_h_
#define _gpio_block_defs_h_
#define _HRT_GPIO_BLOCK_REG_ALIGN 4
/* R/W registers */
#define _gpio_block_reg_do_e 0
#define _gpio_block_reg_do_select 1
#define _gpio_block_reg_do_0 2
#define _gpio_block_reg_do_1 3
#define _gpio_block_reg_do_pwm_cnt_0 4
#define _gpio_block_reg_do_pwm_cnt_1 5
#define _gpio_block_reg_do_pwm_cnt_2 6
#define _gpio_block_reg_do_pwm_cnt_3 7
#define _gpio_block_reg_do_pwm_main_cnt 8
#define _gpio_block_reg_do_pwm_enable 9
#define _gpio_block_reg_di_debounce_sel 10
#define _gpio_block_reg_di_debounce_cnt_0 11
#define _gpio_block_reg_di_debounce_cnt_1 12
#define _gpio_block_reg_di_debounce_cnt_2 13
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
/* read-only registers */
#define _gpio_block_reg_di 16
#endif /* _gpio_block_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_
#define _hive_isp_css_streaming_to_mipi_types_hrt_h_
#include <streaming_to_mipi_defs.h>
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_types.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_HIVE_TYPES_H
#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
#define _HRTCAT3(m, n, o) m##n##o
#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
#define _HRTCAT4(m, n, o, p) m##n##o##p
#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
typedef unsigned int hive_bool;
#define hive_false 0
#define hive_true 1
typedef char hive_int8;
typedef short hive_int16;
typedef int hive_int32;
typedef long long hive_int64;
typedef unsigned char hive_uint8;
typedef unsigned short hive_uint16;
typedef unsigned int hive_uint32;
typedef unsigned long long hive_uint64;
/* by default assume 32 bit master port (both data and address) */
#ifndef HRT_DATA_WIDTH
#define HRT_DATA_WIDTH 32
#endif
#ifndef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 32
#endif
#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#elif HRT_DATA_WIDTH == 32
typedef hive_uint32 hrt_data;
#else
#error data width not supported
#endif
#if HRT_ADDRESS_WIDTH == 64
typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
#error adddres width not supported
#endif
/* The SP side representation of an HMM virtual address */
typedef hive_uint32 hrt_vaddress;
/* use 64 bit addresses in simulation, where possible */
typedef hive_uint64 hive_sim_address;
/* below is for csim, not for hrt, rename and move this elsewhere */
typedef unsigned int hive_uint;
typedef hive_uint32 hive_address;
typedef hive_address hive_slave_address;
typedef hive_address hive_mem_address;
/* MMIO devices */
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_hier_id;
typedef hive_hier_id hive_device_id;
typedef hive_device_id hive_proc_id;
typedef hive_device_id hive_cell_id;
typedef hive_device_id hive_host_id;
typedef hive_device_id hive_bus_id;
typedef hive_device_id hive_bridge_id;
typedef hive_device_id hive_fifo_adapter_id;
typedef hive_device_id hive_custom_device_id;
typedef hive_uint hive_slot_id;
typedef hive_uint hive_fu_id;
typedef hive_uint hive_reg_file_id;
typedef hive_uint hive_reg_id;
/* Streaming devices */
typedef hive_uint hive_outport_id;
typedef hive_uint hive_inport_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
typedef char *hive_program;
typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/if_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IF_DEFS_H
#define _IF_DEFS_H
#define HIVE_IF_FRAME_REQUEST 0xA000
#define HIVE_IF_LINES_REQUEST 0xB000
#define HIVE_IF_VECTORS_REQUEST 0xC000
#endif /* _IF_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_formatter_subsystem_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _if_subsystem_defs_h__
#define _if_subsystem_defs_h__
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10
#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0
/* order of the input bits for the ifmt irq controller */
#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0
#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1
#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2
#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3
#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4
/* order of the input bits for the ifmt Soft reset register */
#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0
#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1
#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2
#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3
/* order of the input bits for the ifmt Soft reset register */
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3
#endif /* _if_subsystem_defs_h__ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_selector_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_selector_defs_h
#define _input_selector_defs_h
#ifndef HIVE_ISP_ISEL_SEL_BITS
#define HIVE_ISP_ISEL_SEL_BITS 2
#endif
#ifndef HIVE_ISP_CH_ID_BITS
#define HIVE_ISP_CH_ID_BITS 2
#endif
#ifndef HIVE_ISP_FMT_TYPE_BITS
#define HIVE_ISP_FMT_TYPE_BITS 5
#endif
/* gp_register register id's -- Outputs */
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
#define HIVE_ISEL_GP_REGS_SOF_IDX 8
#define HIVE_ISEL_GP_REGS_EOF_IDX 9
#define HIVE_ISEL_GP_REGS_SOL_IDX 10
#define HIVE_ISEL_GP_REGS_EOL_IDX 11
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31
#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32
#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33
#define HIVE_ISEL_GP_REGS_SRST_IDX 37
#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0
#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1
#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2
#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3
/* gp_register register id's -- Inputs */
#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34
#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35
#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36
/* irq sources isel irq controller */
#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0
#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1
#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2
#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3
#define HIVE_ISEL_IRQ_NUM_IRQS 4
#endif /* _input_selector_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_switch_2400_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3
#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4
#endif /* _input_switch_2400_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_ctrl_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_system_ctrl_defs_h
#define _input_system_ctrl_defs_h
#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */
/* --------------------------------------------------*/
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
// Number of registers
#define ISYS_CTRL_NOF_REGS 23
// Register id's of MMIO slave accesible registers
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8
#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11
#define ISYS_CTRL_INIT_REG_ID 12
#define ISYS_CTRL_LAST_COMMAND_REG_ID 13
#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16
#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22
/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_INIT_REG_RSTVAL 0
#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
/* register width value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1
/* bit definitions */
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
/*
InpSysCaptFramesAcq 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
CaptA-'b0000
CaptB-'b0001
CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt 2/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
2/1 [31:0] - external capture address
InpSysAcqFrame 2/0 [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
2/1 [31:0] - external memory read start address
InpSysOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysOverruleCmd 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
2/1 [31:0] - command token value for port opid
acknowledge tokens:
InpSysAckCFA 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
CaptA-'b0000
CaptB- 'b0001
CaptC-'b0010
[31:16] - NOF_frames
InpSysAckCFE 1/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
InpSysAckAF 1/0 [3:0] - 'b0010
InpSysAckOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysAckOverrule 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
2/1 [31:0] - acknowledge token value from port opid
*/
/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */
#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */
#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */
#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */
#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */
#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0
#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1
#define ISYS_CTRL_ACK_AF_TOKEN_ID 2
#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3
#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4
#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5
#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6
#define ISYS_CTRL_TOKEN_ID_MSB 3
#define ISYS_CTRL_TOKEN_ID_LSB 0
#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7
#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4
#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31
#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16
#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31
#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8
#define ISYS_CTRL_TOKEN_ID_IDX 0
#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */
#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */
#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */
#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */
#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */
#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */
#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */
#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_CAPT_ACK 16
#endif /* _input_system_ctrl_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_system_defs_h
#define _input_system_defs_h
/* csi controller modes */
#define HIVE_CSI_CONFIG_MAIN 0
#define HIVE_CSI_CONFIG_STEREO1 4
#define HIVE_CSI_CONFIG_STEREO2 8
/* general purpose register IDs */
/* Stream Multicast select modes */
#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0
#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1
#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2
/* Stream Mux select modes */
#define HIVE_ISYS_GPREG_MUX_IDX 3
/* streaming monitor status and control */
#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4
#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5
#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6
#define HIVE_ISYS_GPREG_SRST_IDX 7
#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8
#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9
#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10
/* Bit numbers of the soft reset register */
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2
#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3
#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4
#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5
#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6
#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7
#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8
#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9
/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14
/* -- */
#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15
#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16
#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17
#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv
#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23
#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2
#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3
#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4
#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5
/* streaming monitor port id's */
#define HIVE_ISYS_STR_MON_PORT_CAPA 0
#define HIVE_ISYS_STR_MON_PORT_CAPB 1
#define HIVE_ISYS_STR_MON_PORT_CAPC 2
#define HIVE_ISYS_STR_MON_PORT_ACQ 3
#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4
#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5
#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6
#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7
#define HIVE_ISYS_STR_MON_PORT_PIXA 8
#define HIVE_ISYS_STR_MON_PORT_PIXB 9
/* interrupt bit ID's */
#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0
#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1
#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2
#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3
#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4
#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5
#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6
#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7
/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/
#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8
#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9
/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/
#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10
#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11
/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/
#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12
/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/
#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13
#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14
#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15
#define HIVE_ISYS_IRQ_CIO2AHB 16
#define HIVE_ISYS_IRQ_DMA_BIT_ID 17
#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18
#define HIVE_ISYS_IRQ_NUM_BITS 19
/* DMA */
#define HIVE_ISYS_DMA_CHANNEL 0
#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0
#define HIVE_ISYS_DMA_HEIGHT 1
#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */
#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */
#define HIVE_ISYS_DMA_CROP 0 /* no cropping */
#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */
#endif /* _input_system_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/irq_controller_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _irq_controller_defs_h
#define _irq_controller_defs_h
#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0
#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1
#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2
#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3
#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4
#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5
#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
#endif /* _irq_controller_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2400_support.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp2400_support_h
#define _isp2400_support_h
#ifndef ISP2400_VECTOR_TYPES
/* This typedef is to be able to include hive header files
in the host code which is useful in crun */
typedef char *tmemvectors, *tmemvectoru, *tvector;
#endif
#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val)
#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val)
#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem)
#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem)
#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell))
#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell))
#if ISP_HAS_HIST
#define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram)
#define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell))
#endif
#endif /* _isp2400_support_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2401_mamoiada_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/* Version */
#define RTL_VERSION
/* Cell name */
#define ISP_CELL_TYPE isp2401_mamoiada
#define ISP_VMEM simd_vmem
#define _HRT_ISP_VMEM isp2401_mamoiada_simd_vmem
/* instruction pipeline depth */
#define ISP_BRANCHDELAY 5
/* bus */
#define ISP_BUS_WIDTH 32
#define ISP_BUS_ADDR_WIDTH 32
#define ISP_BUS_BURST_SIZE 1
/* data-path */
#define ISP_SCALAR_WIDTH 32
#define ISP_SLICE_NELEMS 4
#define ISP_VEC_NELEMS 64
#define ISP_VEC_ELEMBITS 14
#define ISP_VEC_ELEM8BITS 16
#define ISP_CLONE_DATAPATH_IS_16 1
/* memories */
#define ISP_DMEM_DEPTH 4096
#define ISP_DMEM_BSEL_DOWNSAMPLE 8
#define ISP_VMEM_DEPTH 3072
#define ISP_VMEM_BSEL_DOWNSAMPLE 8
#define ISP_VMEM_ELEMBITS 14
#define ISP_VMEM_ELEM_PRECISION 14
#define ISP_VMEM_IS_BAMEM 1
#if ISP_VMEM_IS_BAMEM
#define ISP_VMEM_BAMEM_MAX_BOI_HEIGHT 8
#define ISP_VMEM_BAMEM_LATENCY 5
#define ISP_VMEM_BAMEM_BANK_NARROWING_FACTOR 2
#define ISP_VMEM_BAMEM_NR_DATA_PLANES 8
#define ISP_VMEM_BAMEM_NR_CFG_REGISTERS 16
#define ISP_VMEM_BAMEM_LININT 0
#define ISP_VMEM_BAMEM_DAP_BITS 3
#define ISP_VMEM_BAMEM_LININT_FRAC_BITS 0
#define ISP_VMEM_BAMEM_PID_BITS 3
#define ISP_VMEM_BAMEM_OFFSET_BITS 19
#define ISP_VMEM_BAMEM_ADDRESS_BITS 25
#define ISP_VMEM_BAMEM_RID_BITS 4
#define ISP_VMEM_BAMEM_TRANSPOSITION 1
#define ISP_VMEM_BAMEM_VEC_PLUS_SLICE 1
#define ISP_VMEM_BAMEM_ARB_SERVICE_CYCLE_BITS 1
#define ISP_VMEM_BAMEM_LUT_ELEMS 16
#define ISP_VMEM_BAMEM_LUT_ADDR_WIDTH 14
#define ISP_VMEM_BAMEM_HALF_BLOCK_WRITE 1
#define ISP_VMEM_BAMEM_SMART_FETCH 1
#define ISP_VMEM_BAMEM_BIG_ENDIANNESS 0
#endif /* ISP_VMEM_IS_BAMEM */
#define ISP_PMEM_DEPTH 2048
#define ISP_PMEM_WIDTH 640
#define ISP_VAMEM_ADDRESS_BITS 12
#define ISP_VAMEM_ELEMBITS 12
#define ISP_VAMEM_DEPTH 2048
#define ISP_VAMEM_ALIGNMENT 2
#define ISP_VA_ADDRESS_WIDTH 896
#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS
#define ISP_HIST_ADDRESS_BITS 12
#define ISP_HIST_ALIGNMENT 4
#define ISP_HIST_COMP_IN_PREC 12
#define ISP_HIST_DEPTH 1024
#define ISP_HIST_WIDTH 24
#define ISP_HIST_COMPONENTS 4
/* program counter */
#define ISP_PC_WIDTH 13
/* Template switches */
#define ISP_SHIELD_INPUT_DMEM 0
#define ISP_SHIELD_OUTPUT_DMEM 1
#define ISP_SHIELD_INPUT_VMEM 0
#define ISP_SHIELD_OUTPUT_VMEM 0
#define ISP_SHIELD_INPUT_PMEM 1
#define ISP_SHIELD_OUTPUT_PMEM 1
#define ISP_SHIELD_INPUT_HIST 1
#define ISP_SHIELD_OUTPUT_HIST 1
/* When LUT is select the shielding is always on */
#define ISP_SHIELD_INPUT_VAMEM 1
#define ISP_SHIELD_OUTPUT_VAMEM 1
#define ISP_HAS_IRQ 1
#define ISP_HAS_SOFT_RESET 1
#define ISP_HAS_VEC_DIV 0
#define ISP_HAS_VFU_W_2O 1
#define ISP_HAS_DEINT3 1
#define ISP_HAS_LUT 1
#define ISP_HAS_HIST 1
#define ISP_HAS_VALSU 1
#define ISP_HAS_3rdVALSU 1
#define ISP_VRF1_HAS_2P 1
#define ISP_SRU_GUARDING 1
#define ISP_VLSU_GUARDING 1
#define ISP_VRF_RAM 1
#define ISP_SRF_RAM 1
#define ISP_SPLIT_VMUL_VADD_IS 0
#define ISP_RFSPLIT_FPGA 0
/* RSN or Bus pipelining */
#define ISP_RSN_PIPE 1
#define ISP_VSF_BUS_PIPE 0
/* extra slave port to vmem */
#define ISP_IF_VMEM 0
#define ISP_GDC_VMEM 0
/* Streaming ports */
#define ISP_IF 1
#define ISP_IF_B 1
#define ISP_GDC 1
#define ISP_SCL 1
#define ISP_GPFIFO 1
#define ISP_SP 1
/* Removing Issue Slot(s) */
#define ISP_HAS_NOT_SIMD_IS2 0
#define ISP_HAS_NOT_SIMD_IS3 0
#define ISP_HAS_NOT_SIMD_IS4 0
#define ISP_HAS_NOT_SIMD_IS4_VADD 0
#define ISP_HAS_NOT_SIMD_IS5 0
#define ISP_HAS_NOT_SIMD_IS6 0
#define ISP_HAS_NOT_SIMD_IS7 0
#define ISP_HAS_NOT_SIMD_IS8 0
/* ICache */
#define ISP_ICACHE 1
#define ISP_ICACHE_ONLY 0
#define ISP_ICACHE_PREFETCH 1
#define ISP_ICACHE_INDEX_BITS 8
#define ISP_ICACHE_SET_BITS 5
#define ISP_ICACHE_BLOCKS_PER_SET_BITS 1
/* Experimental Flags */
#define ISP_EXP_1 0
#define ISP_EXP_2 0
#define ISP_EXP_3 0
#define ISP_EXP_4 0
#define ISP_EXP_5 0
#define ISP_EXP_6 0
/* Derived values */
#define ISP_LOG2_PMEM_WIDTH 10
#define ISP_VEC_WIDTH 896
#define ISP_SLICE_WIDTH 56
#define ISP_VMEM_WIDTH 896
#define ISP_VMEM_ALIGN 128
#if ISP_VMEM_IS_BAMEM
#define ISP_VMEM_ALIGN_ELEM 2
#endif /* ISP_VMEM_IS_BAMEM */
#define ISP_SIMDLSU 1
#define ISP_LSU_IMM_BITS 12
/* convenient shortcuts for software*/
#define ISP_NWAY ISP_VEC_NELEMS
#define NBITS ISP_VEC_ELEMBITS
#define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b))
#define ISP_VEC_ALIGN ISP_VMEM_ALIGN
/* HRT specific vector support */
#define isp2401_mamoiada_vector_alignment ISP_VEC_ALIGN
#define isp2401_mamoiada_vector_elem_bits ISP_VMEM_ELEMBITS
#define isp2401_mamoiada_vector_elem_precision ISP_VMEM_ELEM_PRECISION
#define isp2401_mamoiada_vector_num_elems ISP_VEC_NELEMS
/* register file sizes */
#define ISP_RF0_SIZE 64
#define ISP_RF1_SIZE 16
#define ISP_RF2_SIZE 64
#define ISP_RF3_SIZE 4
#define ISP_RF4_SIZE 64
#define ISP_RF5_SIZE 16
#define ISP_RF6_SIZE 16
#define ISP_RF7_SIZE 16
#define ISP_RF8_SIZE 16
#define ISP_RF9_SIZE 16
#define ISP_RF10_SIZE 16
#define ISP_RF11_SIZE 16
#define ISP_VRF1_SIZE 32
#define ISP_VRF2_SIZE 32
#define ISP_VRF3_SIZE 32
#define ISP_VRF4_SIZE 32
#define ISP_VRF5_SIZE 32
#define ISP_VRF6_SIZE 32
#define ISP_VRF7_SIZE 32
#define ISP_VRF8_SIZE 32
#define ISP_SRF1_SIZE 4
#define ISP_SRF2_SIZE 64
#define ISP_SRF3_SIZE 64
#define ISP_SRF4_SIZE 32
#define ISP_SRF5_SIZE 64
#define ISP_FRF0_SIZE 16
#define ISP_FRF1_SIZE 4
#define ISP_FRF2_SIZE 16
#define ISP_FRF3_SIZE 4
#define ISP_FRF4_SIZE 4
#define ISP_FRF5_SIZE 8
#define ISP_FRF6_SIZE 4
/* register file read latency */
#define ISP_VRF1_READ_LAT 1
#define ISP_VRF2_READ_LAT 1
#define ISP_VRF3_READ_LAT 1
#define ISP_VRF4_READ_LAT 1
#define ISP_VRF5_READ_LAT 1
#define ISP_VRF6_READ_LAT 1
#define ISP_VRF7_READ_LAT 1
#define ISP_VRF8_READ_LAT 1
#define ISP_SRF1_READ_LAT 1
#define ISP_SRF2_READ_LAT 1
#define ISP_SRF3_READ_LAT 1
#define ISP_SRF4_READ_LAT 1
#define ISP_SRF5_READ_LAT 1
#define ISP_SRF5_READ_LAT 1
/* immediate sizes */
#define ISP_IS1_IMM_BITS 14
#define ISP_IS2_IMM_BITS 13
#define ISP_IS3_IMM_BITS 14
#define ISP_IS4_IMM_BITS 14
#define ISP_IS5_IMM_BITS 9
#define ISP_IS6_IMM_BITS 16
#define ISP_IS7_IMM_BITS 9
#define ISP_IS8_IMM_BITS 16
#define ISP_IS9_IMM_BITS 11
/* fifo depths */
#define ISP_IF_FIFO_DEPTH 0
#define ISP_IF_B_FIFO_DEPTH 0
#define ISP_DMA_FIFO_DEPTH 0
#define ISP_OF_FIFO_DEPTH 0
#define ISP_GDC_FIFO_DEPTH 0
#define ISP_SCL_FIFO_DEPTH 0
#define ISP_GPFIFO_FIFO_DEPTH 0
#define ISP_SP_FIFO_DEPTH 0
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_acquisition_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp_acquisition_defs_h
#define _isp_acquisition_defs_h
#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
/* --------------------------------------------------*/
#define NOF_ACQ_IRQS 1
/* --------------------------------------------------*/
/* FSM */
/* --------------------------------------------------*/
#define MEM2STREAM_FSM_STATE_BITS 2
#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
#define NOF_ACQ_REGS 12
// Register id's of MMIO slave accesible registers
#define ACQ_START_ADDR_REG_ID 0
#define ACQ_MEM_REGION_SIZE_REG_ID 1
#define ACQ_NUM_MEM_REGIONS_REG_ID 2
#define ACQ_INIT_REG_ID 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5
#define ACQ_LAST_COMMAND_REG_ID 6
#define ACQ_NEXT_COMMAND_REG_ID 7
#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9
#define ACQ_FSM_STATE_INFO_REG_ID 10
#define ACQ_INT_CNTR_INFO_REG_ID 11
// Register width
#define ACQ_START_ADDR_REG_WIDTH 9
#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ACQ_INIT_REG_WIDTH 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define ACQ_LAST_COMMAND_REG_WIDTH 32
#define ACQ_NEXT_COMMAND_REG_WIDTH 32
#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH 32
/* register reset value */
#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define ACQ_LAST_COMMAND_REG_RSTVAL 0
#define ACQ_NEXT_COMMAND_REG_RSTVAL 0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
/* bit definitions */
#define ACQ_INIT_RST_REG_BIT 0
#define ACQ_INIT_RESYNC_BIT 2
#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT
#define ACQ_INIT_RST_BITS 1
#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT
#define ACQ_INIT_RESYNC_BITS 1
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB 0
#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4
#define ACQ_TOKEN_ID_IDX 0
#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH
#define ACQ_INIT_CMD_INIT_IDX 4
#define ACQ_INIT_CMD_INIT_BITS 3
#define ACQ_CMD_START_ADDR_IDX 4
#define ACQ_CMD_START_ADDR_BITS 9
#define ACQ_CMD_NOFWORDS_IDX 13
#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_MEM_REGION_ID_IDX 22
#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_PACKET_LENGTH_TOKEN_MSB 21
#define ACQ_PACKET_LENGTH_TOKEN_LSB 13
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4
#define ACQ_PACKET_CH_ID_TOKEN_MSB 11
#define ACQ_PACKET_CH_ID_TOKEN_LSB 10
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */
/* Command tokens IDs */
#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b
#define ACQ_READ_REGION_TOKEN_ID 1 //0001b
#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_INIT_TOKEN_ID 8 //1000b
/* Acknowledge token IDs */
#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b
#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b
#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b
#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b
#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b
#define ACQ_TOKEN_MEMREGIONID_MSB 30
#define ACQ_TOKEN_MEMREGIONID_LSB 22
#define ACQ_TOKEN_NOFWORDS_MSB 21
#define ACQ_TOKEN_NOFWORDS_LSB 13
#define ACQ_TOKEN_STARTADDR_MSB 12
#define ACQ_TOKEN_STARTADDR_LSB 4
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define WORD_COUNT_WIDTH 16
#define PKT_CODE_WIDTH 6
#define CHN_NO_WIDTH 2
#define ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
#define EOF_CODE 1
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define ACQ_START_OF_FRAME 0
#define ACQ_END_OF_FRAME 1
#define ACQ_START_OF_LINE 2
#define ACQ_END_OF_LINE 3
#define ACQ_LINE_PAYLOAD 4
#define ACQ_GEN_SH_PKT 5
/* bit definition */
#define ACQ_PKT_TYPE_IDX 16
#define ACQ_PKT_TYPE_BITS 6
#define ACQ_PKT_SOP_IDX 32
#define ACQ_WORD_CNT_IDX 0
#define ACQ_WORD_CNT_BITS 16
#define ACQ_PKT_INFO_IDX 16
#define ACQ_PKT_INFO_BITS 8
#define ACQ_HEADER_DATA_IDX 0
#define ACQ_HEADER_DATA_BITS 16
#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX
#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS
#define ACQ_ACK_NOFWORDS_IDX 13
#define ACQ_ACK_NOFWORDS_BITS 9
#define ACQ_ACK_PKT_LEN_IDX 4
#define ACQ_ACK_PKT_LEN_BITS 16
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */
#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
#define ACQ_SOL_DATA 2 /* 00 0010 line start */
#define ACQ_EOL_DATA 3 /* 00 0011 line end */
#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RESERVED_DATA_TYPE_MIN 56
#define ACQ_RESERVED_DATA_TYPE_MAX 63
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23
#define ACQ_YUV_RESERVED_DATA_TYPE 27
#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37
#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39
#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46
#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47
/* --------------------------------------------------*/
#endif /* _isp_acquisition_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_capture_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp_capture_defs_h
#define _isp_capture_defs_h
#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */
#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8)
#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
/* --------------------------------------------------*/
#define NOF_IRQS 2
/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/
// Number of registers
#define CAPT_NOF_REGS 16
// Register id's of MMIO slave accesible registers
#define CAPT_START_MODE_REG_ID 0
#define CAPT_START_ADDR_REG_ID 1
#define CAPT_MEM_REGION_SIZE_REG_ID 2
#define CAPT_NUM_MEM_REGIONS_REG_ID 3
#define CAPT_INIT_REG_ID 4
#define CAPT_START_REG_ID 5
#define CAPT_STOP_REG_ID 6
#define CAPT_PACKET_LENGTH_REG_ID 7
#define CAPT_RECEIVED_LENGTH_REG_ID 8
#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_NEXT_COMMAND_REG_ID 12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14
#define CAPT_FSM_STATE_INFO_REG_ID 15
// Register width
#define CAPT_START_MODE_REG_WIDTH 1
#define CAPT_START_REG_WIDTH 1
#define CAPT_STOP_REG_WIDTH 1
/* --------------------------------------------------*/
/* FSM */
/* --------------------------------------------------*/
#define CAPT_WRITE2MEM_FSM_STATE_BITS 2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3
#define CAPT_PACKET_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define CAPT_LAST_COMMAND_REG_WIDTH 32
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))
/* register reset value */
#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_ADDR_REG_RSTVAL 0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128
#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_INIT_REG_RSTVAL 0
#define CAPT_START_REG_RSTVAL 0
#define CAPT_STOP_REG_RSTVAL 0
#define CAPT_PACKET_LENGTH_REG_RSTVAL 0
#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0
#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define CAPT_LAST_COMMAND_REG_RSTVAL 0
#define CAPT_NEXT_COMMAND_REG_RSTVAL 0
#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0
#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0
/* bit definitions */
#define CAPT_INIT_RST_REG_BIT 0
#define CAPT_INIT_FLUSH_BIT 1
#define CAPT_INIT_RESYNC_BIT 2
#define CAPT_INIT_RESTART_BIT 3
#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4
#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS 1
#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT
#define CAPT_INIT_FLUSH_BITS 1
#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT
#define CAPT_INIT_RESYNC_BITS 1
#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT
#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define CAPT_TOKEN_ID_LSB 0
#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */
/* Command tokens IDs */
#define CAPT_START_TOKEN_ID 0 /* 0000b */
#define CAPT_STOP_TOKEN_ID 1 /* 0001b */
#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */
#define CAPT_INIT_TOKEN_ID 8 /* 1000b */
#define CAPT_START_TOKEN_BIT 0
#define CAPT_STOP_TOKEN_BIT 0
#define CAPT_FREEZE_TOKEN_BIT 0
#define CAPT_RESUME_TOKEN_BIT 0
#define CAPT_INIT_TOKEN_BIT 0
/* Acknowledge token IDs */
#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */
#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */
#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */
#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */
#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */
#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */
#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */
#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */
#define CAPT_PACKET_LENGTH_TOKEN_MSB 19
#define CAPT_PACKET_LENGTH_TOKEN_LSB 4
#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20
#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20
#define CAPT_PACKET_CH_ID_TOKEN_MSB 27
#define CAPT_PACKET_CH_ID_TOKEN_LSB 26
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
/* bit definition */
#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB
#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1)
#define CAPT_SOP_IDX 32
#define CAPT_SOP_BITS 1
#define CAPT_PKT_INFO_IDX 16
#define CAPT_PKT_INFO_BITS 8
#define CAPT_PKT_TYPE_IDX 0
#define CAPT_PKT_TYPE_BITS 6
#define CAPT_HEADER_DATA_IDX 0
#define CAPT_HEADER_DATA_BITS 16
#define CAPT_PKT_DATA_IDX 0
#define CAPT_PKT_DATA_BITS 32
#define CAPT_WORD_CNT_IDX 0
#define CAPT_WORD_CNT_BITS 16
#define CAPT_ACK_TOKEN_ID_IDX 0
#define CAPT_ACK_TOKEN_ID_BITS 4
//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB
//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1)
//#define CAPT_ACK_PKT_INFO_IDX 20
//#define CAPT_ACK_PKT_INFO_BITS 8
//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */
//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */
#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB
#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1)
#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB
#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1)
#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB
#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1)
#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB
#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1)
#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB
#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1)
#define CAPT_INIT_TOKEN_INIT_IDX 4
#define CAPT_INIT_TOKEN_INIT_BITS 22
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define CAPT_WORD_COUNT_WIDTH 16
#define CAPT_PKT_CODE_WIDTH 6
#define CAPT_CHN_NO_WIDTH 2
#define CAPT_ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
#define CAPT_START_OF_FRAME 0
#define CAPT_END_OF_FRAME 1
#define CAPT_START_OF_LINE 2
#define CAPT_END_OF_LINE 3
#define CAPT_LINE_PAYLOAD 4
#define CAPT_GEN_SH_PKT 5
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */
#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
#define CAPT_SOL_DATA 2 /* 00 0010 line start */
#define CAPT_EOL_DATA 3 /* 00 0011 line end */
#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RESERVED_DATA_TYPE_MIN 56
#define CAPT_RESERVED_DATA_TYPE_MAX 63
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23
#define CAPT_YUV_RESERVED_DATA_TYPE 27
#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37
#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39
#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46
#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47
/* --------------------------------------------------*/
/* Capture Unit State */
/* --------------------------------------------------*/
#define CAPT_FREE_RUN 0
#define CAPT_NO_SYNC 1
#define CAPT_SYNC_SWP 2
#define CAPT_SYNC_MWP 3
#define CAPT_SYNC_WAIT 4
#define CAPT_FREEZE 5
#define CAPT_RUN 6
/* --------------------------------------------------*/
#endif /* _isp_capture_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/mmu_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _mmu_defs_h
#define _mmu_defs_h
#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0
#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1
#define _HRT_MMU_REG_ALIGN 4
#endif /* _mmu_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/scalar_processor_2400_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _scalar_processor_2400_params_h
#define _scalar_processor_2400_params_h
#include "cell_params.h"
#endif /* _scalar_processor_2400_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/str2mem_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _ST2MEM_DEFS_H
#define _ST2MEM_DEFS_H
#define _STR2MEM_CRUN_BIT 0x100000
#define _STR2MEM_CMD_BITS 0x0F0000
#define _STR2MEM_COUNT_BITS 0x00FFFF
#define _STR2MEM_BLOCKS_CMD 0xA0000
#define _STR2MEM_PACKETS_CMD 0xB0000
#define _STR2MEM_BYTES_CMD 0xC0000
#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
#define _STR2MEM_SOFT_RESET_REG_ID 0
#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1
#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2
#define _STR2MEM_BIT_SWAPPING_REG_ID 3
#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4
#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5
#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6
#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7
#define _STR2MEM_EN_STAT_UPDATE_ID 8
#define _STR2MEM_REG_ALIGN 4
#endif /* _ST2MEM_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/streaming_to_mipi_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _streaming_to_mipi_defs_h
#define _streaming_to_mipi_defs_h
#define HIVE_STR_TO_MIPI_VALID_A_BIT 0
#define HIVE_STR_TO_MIPI_VALID_B_BIT 1
#define HIVE_STR_TO_MIPI_SOL_BIT 2
#define HIVE_STR_TO_MIPI_EOL_BIT 3
#define HIVE_STR_TO_MIPI_SOF_BIT 4
#define HIVE_STR_TO_MIPI_EOF_BIT 5
#define HIVE_STR_TO_MIPI_CH_ID_LSB 6
#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1)
#endif /* _streaming_to_mipi_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/timed_controller_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _timed_controller_defs_h
#define _timed_controller_defs_h
#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
#endif /* _timed_controller_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/version.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_VERSION_H
#define HRT_VERSION_H
#define HRT_VERSION_MAJOR 1
#define HRT_VERSION_MINOR 4
#define HRT_VERSION 1_4
#endif
drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_local.h
View file @ 7c2b6c1e
......@@ -18,8 +18,8 @@
#include <type_support.h>
#include "dma_global.h"
#include <hrt/defs.h> /* HRTCAT() */
#include <hrt/bits.h> /* _hrt_get_bits() */
#include <defs.h> /* HRTCAT() */
#include <bits.h> /* _hrt_get_bits() */
#include <hive_isp_css_defs.h> /* HIVE_DMA_NUM_CHANNELS */
#include <dma_v2_defs.h>
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_private.h
View file @ 7c2b6c1e
......@@ -21,7 +21,7 @@
#include "assert_support.h"
#include <hrt/bits.h> /* _hrt_get_bits() */
#include <bits.h> /* _hrt_get_bits() */
STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID)
{
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor.c
View file @ 7c2b6c1e
......@@ -17,7 +17,7 @@
#include <type_support.h>
#include "device_access.h"
#include <hrt/bits.h>
#include <bits.h>
#include "gp_device.h"
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/system_local.h
View file @ 7c2b6c1e
......@@ -25,12 +25,12 @@
#include "system_global.h"
/* HRT assumes 32 by default (see Linux/include/hrt/hive_types.h), overrule it in case it is different */
/* HRT assumes 32 by default (see Linux/include/hive_types.h), overrule it in case it is different */
#undef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
/* This interface is deprecated */
#include "hrt/hive_types.h"
#include "hive_types.h"
/*
* Cell specific address maps
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/timed_ctrl_global.h
View file @ 7c2b6c1e
......@@ -17,7 +17,7 @@
#define IS_TIMED_CTRL_VERSION_1
#include <timed_controller_defs.h>
#include "timed_controller_defs.h"
/**
* Order of the input bits for the timed controller taken from
......
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