Commit 7c786065 authored by Nithin Sujir's avatar Nithin Sujir Committed by David S. Miller

tg3: Add flag to disable 1G Half Duplex advertisement

Some link partners have issues if the non-standard 1G half duplex is
advertised. This patch adds support for an nvram setting to disable the
advertisement.
Signed-off-by: default avatarNithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ec99f76d
...@@ -4403,9 +4403,12 @@ static void tg3_phy_copper_begin(struct tg3 *tp) ...@@ -4403,9 +4403,12 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
if (tg3_flag(tp, WOL_SPEED_100MB)) if (tg3_flag(tp, WOL_SPEED_100MB))
adv |= ADVERTISED_100baseT_Half | adv |= ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full; ADVERTISED_100baseT_Full;
if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
adv |= ADVERTISED_1000baseT_Half | if (!(tp->phy_flags &
ADVERTISED_1000baseT_Full; TG3_PHYFLG_DISABLE_1G_HD_ADV))
adv |= ADVERTISED_1000baseT_Half;
adv |= ADVERTISED_1000baseT_Full;
}
fc = FLOW_CTRL_TX | FLOW_CTRL_RX; fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
} else { } else {
...@@ -14917,7 +14920,8 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) ...@@ -14917,7 +14920,8 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
if (val == NIC_SRAM_DATA_SIG_MAGIC) { if (val == NIC_SRAM_DATA_SIG_MAGIC) {
u32 nic_cfg, led_cfg; u32 nic_cfg, led_cfg;
u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
u32 nic_phy_id, ver, eeprom_phy_id;
int eeprom_phy_serdes = 0; int eeprom_phy_serdes = 0;
tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
...@@ -14934,6 +14938,11 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) ...@@ -14934,6 +14938,11 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
if (tg3_asic_rev(tp) == ASIC_REV_5785) if (tg3_asic_rev(tp) == ASIC_REV_5785)
tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719 ||
tg3_asic_rev(tp) == ASIC_REV_5720)
tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
eeprom_phy_serdes = 1; eeprom_phy_serdes = 1;
...@@ -15086,6 +15095,9 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) ...@@ -15086,6 +15095,9 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
} }
done: done:
if (tg3_flag(tp, WOL_CAP)) if (tg3_flag(tp, WOL_CAP))
...@@ -15181,9 +15193,11 @@ static void tg3_phy_init_link_config(struct tg3 *tp) ...@@ -15181,9 +15193,11 @@ static void tg3_phy_init_link_config(struct tg3 *tp)
{ {
u32 adv = ADVERTISED_Autoneg; u32 adv = ADVERTISED_Autoneg;
if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
adv |= ADVERTISED_1000baseT_Half | if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
ADVERTISED_1000baseT_Full; adv |= ADVERTISED_1000baseT_Half;
adv |= ADVERTISED_1000baseT_Full;
}
if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
adv |= ADVERTISED_100baseT_Half | adv |= ADVERTISED_100baseT_Half |
......
...@@ -2226,6 +2226,9 @@ ...@@ -2226,6 +2226,9 @@
#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c #define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff #define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
#define NIC_SRAM_DATA_CFG_5 0x00000e0c
#define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
...@@ -3325,6 +3328,7 @@ struct tg3 { ...@@ -3325,6 +3328,7 @@ struct tg3 {
#define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000 #define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000
#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000 #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000
#define TG3_PHYFLG_MDIX_STATE 0x00200000 #define TG3_PHYFLG_MDIX_STATE 0x00200000
#define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000
u32 led_ctrl; u32 led_ctrl;
u32 phy_otp; u32 phy_otp;
......
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