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Commit 7f0ff702 authored by Ben Dooks's avatar Ben Dooks
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ARM: Merge next-samsung-s3c64xx-platdeletion 

Merge branch 'next-samsung-s3c64xx-platdeletion' into next-samsung

Conflicts:

	arch/arm/mach-s3c64xx/Makefile (fixed)
parents d35b7a82 110d85ac
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Showing with 587 additions and 857 deletions
arch/arm/Kconfig
View file @ 7f0ff702
......@@ -627,9 +627,24 @@ config ARCH_S3C2410
config ARCH_S3C64XX
bool "Samsung S3C64XX"
select PLAT_S3C
select CPU_V6
select GENERIC_GPIO
select ARM_VIC
select HAVE_CLK
select NO_IOPORT
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
select SAMSUNG_IRQ_UART
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
select SAMSUNG_GPIOLIB_4BIT
help
Samsung S3C64XX series based systems
......@@ -784,7 +799,6 @@ source "arch/arm/mach-dove/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-s5pc1xx/Kconfig"
......@@ -798,8 +812,7 @@ source "arch/arm/mach-s3c2443/Kconfig"
endif
if ARCH_S3C64XX
source "arch/arm/mach-s3c6400/Kconfig"
source "arch/arm/mach-s3c6410/Kconfig"
source "arch/arm/mach-s3c64xx/Kconfig"
endif
source "arch/arm/mach-s5p6440/Kconfig"
......
arch/arm/Makefile
View file @ 7f0ff702
......@@ -160,7 +160,7 @@ machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P6440) := s5p6440
machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100
machine-$(CONFIG_ARCH_SA1100) := sa1100
......@@ -183,7 +183,7 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik
plat-$(CONFIG_PLAT_ORION) := orion
plat-$(CONFIG_PLAT_PXA) := pxa
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung
plat-$(CONFIG_ARCH_S3C64XX) := s3c samsung
plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung
plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c
plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
......
arch/arm/mach-s3c2410/dma.c
View file @ 7f0ff702
......@@ -21,7 +21,7 @@
#include <mach/dma.h>
#include <plat/cpu.h>
#include <plat/dma-plat.h>
#include <plat/dma-s3c24xx.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
......
arch/arm/plat-s3c24xx/include/plat/pm-core.h → arch/arm/mach-s3c2410/include/mach/pm-core.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
/* linux/arch/arm/mach-s3c2410/include/pm-core.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
......
arch/arm/mach-s3c2412/dma.c
View file @ 7f0ff702
......@@ -20,7 +20,7 @@
#include <mach/dma.h>
#include <plat/dma-plat.h>
#include <plat/dma-s3c24xx.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
......
arch/arm/mach-s3c2440/dma.c
View file @ 7f0ff702
......@@ -20,7 +20,7 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <plat/dma-plat.h>
#include <plat/dma-s3c24xx.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
......
arch/arm/mach-s3c2443/dma.c
View file @ 7f0ff702
......@@ -20,7 +20,7 @@
#include <mach/dma.h>
#include <plat/dma-plat.h>
#include <plat/dma-s3c24xx.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
......
arch/arm/mach-s3c6400/Kconfig deleted 100644 → 0
View file @ d35b7a82
# Copyright 2008 Openmoko, Inc.
# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
#
# Licensed under GPLv2
# Configuration options for the S3C6410 CPU
config CPU_S3C6400
bool
select CPU_S3C6400_INIT
select CPU_S3C6400_CLOCK
help
Enable S3C6400 CPU support
config S3C6400_SETUP_SDHCI
bool
help
Internal configuration for default SDHCI
setup for S3C6400.
# S36400 Macchine support
config MACH_SMDK6400
bool "SMDK6400"
select CPU_S3C6400
select S3C_DEV_HSMMC
select S3C_DEV_NAND
select S3C6400_SETUP_SDHCI
help
Machine support for the Samsung SMDK6400
arch/arm/mach-s3c6400/Makefile deleted 100644 → 0
View file @ d35b7a82
# arch/arm/mach-s3c6400/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S3C6400 system
obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
# setup support
obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
# Machine support
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
arch/arm/mach-s3c6400/include/mach/dma.h deleted 100644 → 0
View file @ d35b7a82
/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - DMA support
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
#define S3C_DMA_CHANNELS (16)
/* see mach-s3c2410/dma.h for notes on dma channel numbers */
/* Note, for the S3C64XX architecture we keep the DMACH_
* defines in the order they are allocated to [S]DMA0/[S]DMA1
* so that is easy to do DHACH_ -> DMA controller conversion
*/
enum dma_ch {
/* DMA0/SDMA0 */
DMACH_UART0 = 0,
DMACH_UART0_SRC2,
DMACH_UART1,
DMACH_UART1_SRC2,
DMACH_UART2,
DMACH_UART2_SRC2,
DMACH_UART3,
DMACH_UART3_SRC2,
DMACH_PCM0_TX,
DMACH_PCM0_RX,
DMACH_I2S0_OUT,
DMACH_I2S0_IN,
DMACH_SPI0_TX,
DMACH_SPI0_RX,
DMACH_HSI_I2SV40_TX,
DMACH_HSI_I2SV40_RX,
/* DMA1/SDMA1 */
DMACH_PCM1_TX = 16,
DMACH_PCM1_RX,
DMACH_I2S1_OUT,
DMACH_I2S1_IN,
DMACH_SPI1_TX,
DMACH_SPI1_RX,
DMACH_AC97_PCMOUT,
DMACH_AC97_PCMIN,
DMACH_AC97_MICIN,
DMACH_PWM,
DMACH_IRDA,
DMACH_EXTERNAL,
DMACH_RES1,
DMACH_RES2,
DMACH_SECURITY_RX, /* SDMA1 only */
DMACH_SECURITY_TX, /* SDMA1 only */
DMACH_MAX /* the end */
};
static __inline__ bool s3c_dma_has_circular(void)
{
return true;
}
#define S3C2410_DMAF_CIRCULAR (1 << 0)
#include <plat/dma.h>
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/irqs.h deleted 100644 → 0
View file @ d35b7a82
/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - IRQ definitions
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/regs-clock.h deleted 100644 → 0
View file @ d35b7a82
/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - clock register compatibility with s3c24xx
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/regs-clock.h>
arch/arm/mach-s3c6410/Makefile deleted 100644 → 0
View file @ d35b7a82
# arch/arm/plat-s3c6410/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S3C6410 system
obj-$(CONFIG_CPU_S3C6410) += cpu.o
# Helper and device support
obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
# machine support
obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
obj-$(CONFIG_MACH_HMT) += mach-hmt.o
arch/arm/mach-s3c6410/setup-sdhci.c deleted 100644 → 0
View file @ d35b7a82
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s3c6410_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not successfully used yet */
};
void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything acording to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
arch/arm/mach-s3c6410/Kconfig → arch/arm/mach-s3c64xx/Kconfig
View file @ 7f0ff702
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
#
# Licensed under GPLv2
# temporary until we can eliminate all drivers using it.
config PLAT_S3C64XX
bool
depends on ARCH_S3C64XX
default y
help
Base platform code for any Samsung S3C64XX device
# Configuration options for the S3C6410 CPU
config CPU_S3C6400
bool
help
Enable S3C6400 CPU support
config CPU_S3C6410
bool
select CPU_S3C6400_INIT
select CPU_S3C6400_CLOCK
help
Enable S3C6410 CPU support
config S3C6410_SETUP_SDHCI
bool
config S3C64XX_DMA
bool "S3C64XX DMA"
select S3C_DMA
config S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_SDHCI_GPIO
bool
help
Internal configuration for default SDHCI setup for S3C6400 and
S3C6410 SoCs.
# platform specific device setup
config S3C64XX_SETUP_I2C0
bool
default y
help
Common setup code for i2c bus 0.
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S3C64XX_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S3C64XX_SETUP_FB_24BPP
bool
help
Internal helper functions for S3C6410 based SDHCI systems
Common setup code for S3C64XX with an 24bpp RGB display helper.
config S3C64XX_SETUP_SDHCI_GPIO
bool
help
Common setup code for S3C64XX SDHCI GPIO configurations
# S36400 Macchine support
config MACH_SMDK6400
bool "SMDK6400"
select CPU_S3C6400
select S3C_DEV_HSMMC
select S3C_DEV_NAND
select S3C64XX_SETUP_SDHCI
help
Machine support for the Samsung SMDK6400
# S3C6410 machine support
config MACH_ANW6410
bool "A&W6410"
......@@ -35,7 +91,7 @@ config MACH_SMDK6410
select S3C_DEV_FB
select S3C_DEV_USB_HOST
select S3C_DEV_USB_HSOTG
select S3C6410_SETUP_SDHCI
select S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_FB_24BPP
help
......
arch/arm/plat-s3c64xx/Makefile → arch/arm/mach-s3c64xx/Makefile
View file @ 7f0ff702
# arch/arm/plat-s3c64xx/Makefile
# arch/arm/mach-s3c64xx/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
......@@ -7,49 +7,56 @@
obj-y :=
obj-m :=
obj-n := dummy.o
obj-n :=
obj- :=
# Core files
obj-y += dev-uart.o
obj-y += dev-rtc.o
obj-y += cpu.o
obj-y += irq.o
obj-y += irq-eint.o
obj-y += clock.o
obj-y += gpiolib.o
# CPU support
# Core support for S3C6400 system
obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
obj-y += irq.o
obj-y += irq-eint.o
# PM support
# CPU frequency scaling
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
# DMA support
obj-$(CONFIG_S3C64XX_DMA) += dma.o
# ADC support
obj-$(CONFIG_S3C_ADC) += dev-adc.o
# SPI support
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
# Device support
obj-y += dev-audio.o
# Device setup
obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# PM
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_PM) += irq-pm.o
# Machine support
obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
obj-$(CONFIG_MACH_HMT) += mach-hmt.o
# device support
obj-y += dev-uart.o
obj-y += dev-rtc.o
obj-$(CONFIG_S3C_ADC) += dev-adc.o
obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
arch/arm/plat-s3c64xx/s3c6400-clock.c → arch/arm/mach-s3c64xx/clock.c
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
/* linux/arch/arm/plat-s3c64xx/clock.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 based common clock support
* S3C64XX Base clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -14,24 +14,24 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/cpu-freq.h>
#include <mach/regs-sys.h>
#include <mach/regs-clock.h>
#include <mach/pll.h>
#include <plat/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu.h>
#include <plat/pll.h>
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
......@@ -49,6 +49,251 @@ static struct clk clk_ext_xtal_mux = {
#define clk_fout_mpll clk_mpll
#define clk_fout_epll clk_epll
struct clk clk_h2 = {
.name = "hclk2",
.id = -1,
.rate = 0,
};
struct clk clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S3C64XX_OTHERS);
if (enable)
val |= S3C64XX_OTHERS_USBMASK;
else
val &= ~S3C64XX_OTHERS_USBMASK;
__raw_writel(val, S3C64XX_OTHERS);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
static int inline s3c64xx_gate(void __iomem *reg,
struct clk *clk,
int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
}
static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
}
int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "iis",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, {
.name = "48m",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
.id = 2,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
.name = "dma0",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, {
.name = "dma1",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
},
};
static struct clk init_clocks[] = {
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}
};
static struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
......@@ -492,7 +737,7 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
s3c_set_clksrc(&clksrcs[ptr], true);
}
static struct clk *clks[] __initdata = {
static struct clk *clks1[] __initdata = {
&clk_ext_xtal_mux,
&clk_iis_cd0,
&clk_iis_cd1,
......@@ -503,19 +748,29 @@ static struct clk *clks[] __initdata = {
&clk_arm,
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
&clk_h2,
};
/**
* s3c6400_register_clocks - register clocks for s3c6400 and above
* @armclk_divlimit: Divisor mask for ARMCLK
* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
* @xtal: The rate for the clock crystal feeding the PLLs.
* @armclk_divlimit: Divisor mask for ARMCLK.
*
* Register the clocks for the S3C6400 and above SoC range, such
* as ARMCLK and the clocks which have divider chains attached.
* Register the clocks for the S3C6400 and S3C6410 SoC range, such
* as ARMCLK as well as the necessary parent clocks.
*
* This call does not setup the clocks, which is left to the
* s3c6400_setup_clocks() call which may be needed by the cpufreq
* or resume code to re-set the clocks if the bootloader has changed
* them.
*/
void __init s3c6400_register_clocks(unsigned armclk_divlimit)
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
struct clk *clkp;
int ret;
......@@ -523,14 +778,24 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
armclk_mask = armclk_divlimit;
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
clkp = clks[ptr];
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_pwmclk_init();
}
arch/arm/plat-s3c64xx/cpu.c → arch/arm/mach-s3c64xx/cpu.c
View file @ 7f0ff702
......@@ -33,8 +33,8 @@
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
#include <mach/s3c6400.h>
#include <mach/s3c6410.h>
/* table of supported CPUs */
......@@ -129,6 +129,12 @@ static struct sys_device s3c64xx_sysdev = {
.cls = &s3c64xx_sysclass,
};
/* uart registration process */
void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}
/* read cpu identification code */
......
arch/arm/plat-s3c64xx/dev-audio.c → arch/arm/mach-s3c64xx/dev-audio.c
View file @ 7f0ff702
......@@ -19,12 +19,13 @@
#include <plat/devs.h>
#include <plat/audio.h>
#include <plat/gpio-bank-c.h>
#include <plat/gpio-bank-d.h>
#include <plat/gpio-bank-e.h>
#include <plat/gpio-bank-h.h>
#include <plat/gpio-cfg.h>
#include <mach/gpio-bank-c.h>
#include <mach/gpio-bank-d.h>
#include <mach/gpio-bank-e.h>
#include <mach/gpio-bank-h.h>
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
......
arch/arm/plat-s3c64xx/dev-spi.c → arch/arm/mach-s3c64xx/dev-spi.c
View file @ 7f0ff702
......@@ -16,11 +16,10 @@
#include <mach/dma.h>
#include <mach/map.h>
#include <mach/gpio.h>
#include <plat/spi-clocks.h>
#include <mach/gpio-bank-c.h>
#include <mach/spi-clocks.h>
#include <plat/s3c64xx-spi.h>
#include <plat/gpio-bank-c.h>
#include <plat/gpio-cfg.h>
#include <plat/irqs.h>
......
arch/arm/plat-s3c64xx/dma.c → arch/arm/mach-s3c64xx/dma.c
View file @ 7f0ff702
......@@ -27,8 +27,7 @@
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/dma-plat.h>
#include <plat/regs-sys.h>
#include <mach/regs-sys.h>
#include <asm/hardware/pl080.h>
......
arch/arm/plat-s3c64xx/gpiolib.c → arch/arm/mach-s3c64xx/gpiolib.c
View file @ 7f0ff702
......@@ -22,7 +22,7 @@
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <plat/regs-gpio.h>
#include <mach/regs-gpio.h>
/* GPIO bank summary:
*
......
arch/arm/plat-s3c64xx/include/plat/dma-plat.h → arch/arm/mach-s3c64xx/include/mach/dma.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
*
* Copyright 2009 Openmoko, Inc.
* Copyright 2009 Simtec Electronics
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX DMA core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
* S3C6400 - DMA support
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
#define S3C_DMA_CHANNELS (16)
/* see mach-s3c2410/dma.h for notes on dma channel numbers */
/* Note, for the S3C64XX architecture we keep the DMACH_
* defines in the order they are allocated to [S]DMA0/[S]DMA1
* so that is easy to do DHACH_ -> DMA controller conversion
*/
enum dma_ch {
/* DMA0/SDMA0 */
DMACH_UART0 = 0,
DMACH_UART0_SRC2,
DMACH_UART1,
DMACH_UART1_SRC2,
DMACH_UART2,
DMACH_UART2_SRC2,
DMACH_UART3,
DMACH_UART3_SRC2,
DMACH_PCM0_TX,
DMACH_PCM0_RX,
DMACH_I2S0_OUT,
DMACH_I2S0_IN,
DMACH_SPI0_TX,
DMACH_SPI0_RX,
DMACH_HSI_I2SV40_TX,
DMACH_HSI_I2SV40_RX,
/* DMA1/SDMA1 */
DMACH_PCM1_TX = 16,
DMACH_PCM1_RX,
DMACH_I2S1_OUT,
DMACH_I2S1_IN,
DMACH_SPI1_TX,
DMACH_SPI1_RX,
DMACH_AC97_PCMOUT,
DMACH_AC97_PCMIN,
DMACH_AC97_MICIN,
DMACH_PWM,
DMACH_IRDA,
DMACH_EXTERNAL,
DMACH_RES1,
DMACH_RES2,
DMACH_SECURITY_RX, /* SDMA1 only */
DMACH_SECURITY_TX, /* SDMA1 only */
DMACH_MAX /* the end */
};
static __inline__ bool s3c_dma_has_circular(void)
{
return true;
}
#define S3C2410_DMAF_CIRCULAR (1 << 0)
#include <plat/dma.h>
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
......@@ -68,3 +123,5 @@ struct s3c2410_dma_chan {
};
#include <plat/dma-core.h>
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/entry-macro.S → arch/arm/mach-s3c64xx/include/mach/entry-macro.S
View file @ 7f0ff702
......@@ -13,6 +13,6 @@
*/
#include <mach/map.h>
#include <plat/irqs.h>
#include <mach/irqs.h>
#include <asm/entry-macro-vic2.S>
arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h → arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/irqs.h → arch/arm/mach-s3c64xx/include/mach/irqs.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - Common IRQ support
* S3C64XX - IRQ support
*/
#ifndef __ASM_PLAT_S3C64XX_IRQS_H
#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
#ifndef __ASM_MACH_S3C64XX_IRQS_H
#define __ASM_MACH_S3C64XX_IRQS_H __FILE__
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
......@@ -210,5 +210,5 @@
#define NR_IRQS (IRQ_BOARD_END + 1)
#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
#endif /* __ASM_MACH_S3C64XX_IRQS_H */
arch/arm/plat-s3c64xx/include/plat/pm-core.h → arch/arm/mach-s3c64xx/include/mach/pm-core.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
/* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......@@ -12,7 +12,7 @@
* published by the Free Software Foundation.
*/
#include <plat/regs-gpio.h>
#include <mach/regs-gpio.h>
static inline void s3c_pm_debug_init_uart(void)
{
......
arch/arm/plat-s3c64xx/include/plat/s3c6400.h → arch/arm/mach-s3c64xx/include/mach/s3c6400.h
View file @ 7f0ff702
/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h
/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......@@ -15,9 +15,10 @@
/* Common init code for S3C6400 related SoCs */
extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s3c6400_register_clocks(unsigned armclk_divlimit);
extern void s3c6400_setup_clocks(void);
extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
#ifdef CONFIG_CPU_S3C6400
extern int s3c6400_init(void);
......@@ -33,4 +34,3 @@ extern void s3c6400_init_clocks(int xtal);
#define s3c6400_map_io NULL
#define s3c6400_init NULL
#endif
arch/arm/plat-s3c64xx/include/plat/s3c6410.h → arch/arm/mach-s3c64xx/include/mach/s3c6410.h
View file @ 7f0ff702
/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h
/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......
arch/arm/plat-s3c64xx/include/plat/spi-clocks.h → arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
*
* Copyright (C) 2009 Samsung Electronics Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
......
arch/arm/plat-s3c64xx/irq-eint.c → arch/arm/mach-s3c64xx/irq-eint.c
View file @ 7f0ff702
......@@ -22,7 +22,7 @@
#include <asm/hardware/vic.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-gpio.h>
#include <mach/regs-gpio.h>
#include <plat/gpio-cfg.h>
#include <mach/map.h>
......
arch/arm/plat-s3c64xx/irq-pm.c → arch/arm/mach-s3c64xx/irq-pm.c
View file @ 7f0ff702
......@@ -23,7 +23,7 @@
#include <plat/regs-serial.h>
#include <plat/regs-timer.h>
#include <plat/regs-gpio.h>
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/pm.h>
......
arch/arm/mach-s3c6410/mach-anw6410.c → arch/arm/mach-s3c64xx/mach-anw6410.c
View file @ 7f0ff702
/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
/* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......@@ -45,12 +45,12 @@
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <mach/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/regs-gpio.h>
#include <plat/regs-modem.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
/* DM9000 */
#define ANW6410_PA_DM9000 (0x18000000)
......
arch/arm/mach-s3c6410/mach-hmt.c → arch/arm/mach-s3c64xx/mach-hmt.c
View file @ 7f0ff702
......@@ -38,7 +38,7 @@
#include <plat/fb.h>
#include <plat/nand.h>
#include <plat/s3c6410.h>
#include <mach/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......
arch/arm/mach-s3c6410/mach-ncp.c → arch/arm/mach-s3c64xx/mach-ncp.c
View file @ 7f0ff702
/*
* linux/arch/arm/mach-s3c6410/mach-ncp.c
* linux/arch/arm/mach-s3c64xx/mach-ncp.c
*
* Copyright (C) 2008-2009 Samsung Electronics
*
......@@ -40,7 +40,7 @@
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <mach/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......
arch/arm/mach-s3c6400/mach-smdk6400.c → arch/arm/mach-s3c64xx/mach-smdk6400.c
View file @ 7f0ff702
/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c
/* linux/arch/arm/mach-s3c64xx/mach-smdk6400.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
......@@ -31,7 +31,7 @@
#include <plat/regs-serial.h>
#include <plat/s3c6400.h>
#include <mach/s3c6400.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......
arch/arm/mach-s3c6410/mach-smdk6410.c → arch/arm/mach-s3c64xx/mach-smdk6410.c
View file @ 7f0ff702
/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......@@ -46,15 +46,15 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/regs-modem.h>
#include <plat/regs-gpio.h>
#include <plat/regs-sys.h>
#include <plat/regs-srom.h>
#include <mach/regs-modem.h>
#include <mach/regs-gpio.h>
#include <mach/regs-sys.h>
#include <mach/regs-srom.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <plat/s3c6410.h>
#include <mach/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
......
arch/arm/plat-s3c64xx/pm.c → arch/arm/mach-s3c64xx/pm.c
View file @ 7f0ff702
......@@ -20,14 +20,14 @@
#include <mach/map.h>
#include <plat/pm.h>
#include <plat/regs-sys.h>
#include <plat/regs-gpio.h>
#include <plat/regs-clock.h>
#include <plat/regs-syscon-power.h>
#include <plat/regs-gpio-memport.h>
#include <mach/regs-sys.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-syscon-power.h>
#include <mach/regs-gpio-memport.h>
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
#include <plat/gpio-bank-n.h>
#include <mach/gpio-bank-n.h>
void s3c_pm_debug_smdkled(u32 set, u32 clear)
{
......
arch/arm/mach-s3c6400/s3c6400.c → arch/arm/mach-s3c64xx/s3c6400.c
View file @ 7f0ff702
/* linux/arch/arm/mach-s3c6410/cpu.c
/* linux/arch/arm/mach-s3c64xx/cpu.c
*
* Copyright 2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
......@@ -30,14 +30,14 @@
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/regs-clock.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s3c6400.h>
#include <mach/s3c6400.h>
void __init s3c6400_map_io(void)
{
......@@ -55,10 +55,7 @@ void __init s3c6400_map_io(void)
void __init s3c6400_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
s3c6400_setup_clocks();
}
......
arch/arm/mach-s3c6410/cpu.c → arch/arm/mach-s3c64xx/s3c6410.c
View file @ 7f0ff702
/* linux/arch/arm/mach-s3c6410/cpu.c
/* linux/arch/arm/mach-s3c64xx/s3c6410.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
......@@ -31,30 +31,18 @@
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/regs-clock.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* Initial IO mappings */
static struct map_desc s3c6410_iodesc[] __initdata = {
};
/* s3c6410_map_io
*
* register the standard cpu IO areas
*/
#include <mach/s3c6400.h>
#include <mach/s3c6410.h>
void __init s3c6410_map_io(void)
{
iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
/* initialise device information early */
s3c6410_default_sdhci0();
s3c6410_default_sdhci1();
......@@ -70,9 +58,7 @@ void __init s3c6410_map_io(void)
void __init s3c6410_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
s3c6400_setup_clocks();
}
......
arch/arm/plat-s3c64xx/setup-i2c0.c → arch/arm/mach-s3c64xx/setup-i2c0.c
View file @ 7f0ff702
......@@ -18,8 +18,8 @@
struct platform_device; /* don't need the contents */
#include <mach/gpio.h>
#include <mach/gpio-bank-b.h>
#include <plat/iic.h>
#include <plat/gpio-bank-b.h>
#include <plat/gpio-cfg.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
......
arch/arm/plat-s3c64xx/setup-i2c1.c → arch/arm/mach-s3c64xx/setup-i2c1.c
View file @ 7f0ff702
......@@ -18,8 +18,8 @@
struct platform_device; /* don't need the contents */
#include <mach/gpio.h>
#include <mach/gpio-bank-b.h>
#include <plat/iic.h>
#include <plat/gpio-bank-b.h>
#include <plat/gpio-cfg.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
......
arch/arm/mach-s3c6400/setup-sdhci.c → arch/arm/mach-s3c64xx/setup-sdhci.c
View file @ 7f0ff702
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
* S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -26,7 +26,7 @@
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s3c6400_hsmmc_clksrcs[4] = {
char *s3c64xx_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
......@@ -61,3 +61,12 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
s3c6400_setup_sdhci_cfg_card(dev, r, ios, card);
}
arch/arm/plat-s3c64xx/sleep.S → arch/arm/mach-s3c64xx/sleep.S
View file @ 7f0ff702
/* linux/0arch/arm/plat-s3c64xx/sleep.S
/* linux/arch/arm/plat-s3c64xx/sleep.S
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
......@@ -19,8 +19,8 @@
#undef S3C64XX_VA_GPIO
#define S3C64XX_VA_GPIO (0x0)
#include <plat/regs-gpio.h>
#include <plat/gpio-bank-n.h>
#include <mach/regs-gpio.h>
#include <mach/gpio-bank-n.h>
#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
......
arch/arm/plat-s3c/dma.c
View file @ 7f0ff702
......@@ -20,8 +20,6 @@ struct s3c2410_dma_buf;
#include <mach/dma.h>
#include <mach/irqs.h>
#include <plat/dma-plat.h>
/* dma channel state information */
struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
......
arch/arm/plat-s3c/pm.c
View file @ 7f0ff702
......@@ -29,7 +29,7 @@
#include <asm/irq.h>
#include <plat/pm.h>
#include <plat/pm-core.h>
#include <mach/pm-core.h>
/* for external use */
......
arch/arm/plat-s3c24xx/dma.c
View file @ 7f0ff702
......@@ -33,7 +33,7 @@
#include <mach/dma.h>
#include <mach/map.h>
#include <plat/dma-plat.h>
#include <plat/dma-s3c24xx.h>
#include <plat/regs-dma.h>
/* io map for dma */
......
arch/arm/plat-s3c64xx/Kconfig deleted 100644 → 0
View file @ d35b7a82
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
# Ben Dooks <ben@simtec.co.uk>
#
# Licensed under GPLv2
config PLAT_S3C64XX
bool
depends on ARCH_S3C64XX
default y
select CPU_V6
select PLAT_S3C
select ARM_VIC
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
select SAMSUNG_IRQ_UART
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
select SAMSUNG_GPIOLIB_4BIT
help
Base platform code for any Samsung S3C64XX device
if PLAT_S3C64XX
# Configuration options shared by all S3C64XX implementations
config CPU_S3C6400_INIT
bool
help
Common initialisation code for the S3C6400 that is shared
by other CPUs in the series, such as the S3C6410.
config CPU_S3C6400_CLOCK
bool
help
Common clock support code for the S3C6400 that is shared
by other CPUs in the series, such as the S3C6410.
config S3C64XX_DMA
bool "S3C64XX DMA"
select S3C_DMA
# platform specific device setup
config S3C64XX_SETUP_I2C0
bool
default y
help
Common setup code for i2c bus 0.
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S3C64XX_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S3C64XX_SETUP_FB_24BPP
bool
help
Common setup code for S3C64XX with an 24bpp RGB display helper.
config S3C64XX_SETUP_SDHCI_GPIO
bool
help
Common setup code for S3C64XX SDHCI GPIO configurations
endif
arch/arm/plat-s3c64xx/clock.c deleted 100644 → 0
View file @ d35b7a82
/* linux/arch/arm/plat-s3c64xx/clock.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX Base clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/regs-sys.h>
#include <plat/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
struct clk clk_h2 = {
.name = "hclk2",
.id = -1,
.rate = 0,
};
struct clk clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S3C64XX_OTHERS);
if (enable)
val |= S3C64XX_OTHERS_USBMASK;
else
val &= ~S3C64XX_OTHERS_USBMASK;
__raw_writel(val, S3C64XX_OTHERS);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
static int inline s3c64xx_gate(void __iomem *reg,
struct clk *clk,
int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
}
static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
}
int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "iis",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, {
.name = "48m",
.id = 0,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
.id = 1,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
.id = 2,
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
.name = "dma0",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, {
.name = "dma1",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
},
};
static struct clk init_clocks[] = {
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
&clk_h2,
};
void __init s3c64xx_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
arch/arm/plat-s3c64xx/s3c6400-init.c deleted 100644 → 0
View file @ d35b7a82
/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - CPU initialisation (common with other S3C64XX chips)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* uart registration process */
void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}
arch/arm/plat-samsung/include/plat/clock.h
View file @ 7f0ff702
......@@ -94,7 +94,6 @@ extern void s3c_register_clocks(struct clk *clk, int nr_clks);
extern int s3c24xx_register_baseclocks(unsigned long xtal);
extern void s3c64xx_register_clocks(void);
extern void s5p_register_clocks(unsigned long xtal_freq);
extern void s3c24xx_setup_clocks(unsigned long fclk,
......
arch/arm/plat-s3c24xx/include/plat/dma-plat.h → arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
View file @ 7f0ff702
/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
*
* Copyright (C) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C24XX DMA support
* Samsung S3C24XX DMA support - per SoC functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
arch/arm/plat-samsung/include/plat/sdhci.h
View file @ 7f0ff702
......@@ -78,8 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
/* S3C6400 SDHCI setup */
#ifdef CONFIG_S3C6400_SETUP_SDHCI
extern char *s3c6400_hsmmc_clksrcs[4];
#ifdef CONFIG_S3C64XX_SETUP_SDHCI
extern char *s3c64xx_hsmmc_clksrcs[4];
#ifdef CONFIG_S3C_DEV_HSMMC
extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
......@@ -89,7 +89,7 @@ extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
static inline void s3c6400_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
}
......@@ -101,7 +101,7 @@ static inline void s3c6400_default_sdhci0(void) { }
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s3c6400_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
}
......@@ -112,7 +112,7 @@ static inline void s3c6400_default_sdhci1(void) { }
#ifdef CONFIG_S3C_DEV_HSMMC2
static inline void s3c6400_default_sdhci2(void)
{
s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
}
......@@ -120,17 +120,9 @@ static inline void s3c6400_default_sdhci2(void)
static inline void s3c6400_default_sdhci2(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC2 */
#else
static inline void s3c6400_default_sdhci0(void) { }
static inline void s3c6400_default_sdhci1(void) { }
#endif /* CONFIG_S3C6400_SETUP_SDHCI */
/* S3C6410 SDHCI setup */
#ifdef CONFIG_S3C6410_SETUP_SDHCI
extern char *s3c6410_hsmmc_clksrcs[4];
extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
......@@ -138,9 +130,9 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
#ifdef CONFIG_S3C_DEV_HSMMC
static inline void s3c6410_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
}
#else
static inline void s3c6410_default_sdhci0(void) { }
......@@ -149,9 +141,9 @@ static inline void s3c6410_default_sdhci0(void) { }
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s3c6410_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
}
#else
static inline void s3c6410_default_sdhci1(void) { }
......@@ -160,9 +152,9 @@ static inline void s3c6410_default_sdhci1(void) { }
#ifdef CONFIG_S3C_DEV_HSMMC2
static inline void s3c6410_default_sdhci2(void)
{
s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
}
#else
static inline void s3c6410_default_sdhci2(void) { }
......@@ -171,7 +163,10 @@ static inline void s3c6410_default_sdhci2(void) { }
#else
static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C6410_SETUP_SDHCI */
static inline void s3c6400_default_sdhci0(void) { }
static inline void s3c6400_default_sdhci1(void) { }
#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
/* S5PC100 SDHCI setup */
......
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