ASoC: mediatek: update MT2701 AFE documentation to adapt mfd device

As the new MFD parent is in place, modify MT2701 AFE documentation to
adapt it. Also add three core clocks in example.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt

@@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
 
 Required properties:
 - compatible = "mediatek,mt2701-audio";
-- reg: register location and size
 - interrupts: should contain AFE and ASYS interrupts
 - interrupt-names: should be "afe" and "asys"
 - power-domains: should define the power domain
 - clocks: Must contain an entry for each entry in clock-names
   See ../clocks/clock-bindings.txt for details
 - clock-names: should have these clock names:
+		"infra_sys_audio_clk",
 		"top_audio_mux1_sel",
 		"top_audio_mux2_sel",
+		"top_audio_a1sys_hp",
+		"top_audio_a2sys_hp",
 		"i2s0_src_sel",
 		"i2s1_src_sel",
 		"i2s2_src_sel",
@@ -45,18 +47,27 @@ Required properties:
 - assigned-clocks-parents: parent of input clocks of assigned clocks.
 - assigned-clock-rates: list of clock frequencies of assigned clocks.
 
+Must be a subnode of MediaTek audsys device tree node.
+See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
+
 Example:
 
-	afe: mt2701-afe-pcm@11220000 {
+	audsys: audio-subsystem@11220000 {
+		compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+		...
+
+		afe: audio-controller {
 			compatible = "mediatek,mt2701-audio";
-		reg = <0 0x11220000 0 0x2000>,
-		      <0 0x112A0000 0 0x20000>;
 			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 			interrupt-names	= "afe", "asys";
 			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-		clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+
+			clocks = <&infracfg CLK_INFRA_AUDIO>,
+				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
+				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
 				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
@@ -69,26 +80,29 @@ Example:
 				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
-			 <&audiosys CLK_AUD_I2SO1>,
-			 <&audiosys CLK_AUD_I2SO2>,
-			 <&audiosys CLK_AUD_I2SO3>,
-			 <&audiosys CLK_AUD_I2SO4>,
-			 <&audiosys CLK_AUD_I2SIN1>,
-			 <&audiosys CLK_AUD_I2SIN2>,
-			 <&audiosys CLK_AUD_I2SIN3>,
-			 <&audiosys CLK_AUD_I2SIN4>,
-			 <&audiosys CLK_AUD_ASRCO1>,
-			 <&audiosys CLK_AUD_ASRCO2>,
-			 <&audiosys CLK_AUD_ASRCO3>,
-			 <&audiosys CLK_AUD_ASRCO4>,
-			 <&audiosys CLK_AUD_AFE>,
-			 <&audiosys CLK_AUD_AFE_CONN>,
-			 <&audiosys CLK_AUD_A1SYS>,
-			 <&audiosys CLK_AUD_A2SYS>,
-			 <&audiosys CLK_AUD_AFE_MRGIF>;
+				 <&audsys CLK_AUD_I2SO1>,
+				 <&audsys CLK_AUD_I2SO2>,
+				 <&audsys CLK_AUD_I2SO3>,
+				 <&audsys CLK_AUD_I2SO4>,
+				 <&audsys CLK_AUD_I2SIN1>,
+				 <&audsys CLK_AUD_I2SIN2>,
+				 <&audsys CLK_AUD_I2SIN3>,
+				 <&audsys CLK_AUD_I2SIN4>,
+				 <&audsys CLK_AUD_ASRCO1>,
+				 <&audsys CLK_AUD_ASRCO2>,
+				 <&audsys CLK_AUD_ASRCO3>,
+				 <&audsys CLK_AUD_ASRCO4>,
+				 <&audsys CLK_AUD_AFE>,
+				 <&audsys CLK_AUD_AFE_CONN>,
+				 <&audsys CLK_AUD_A1SYS>,
+				 <&audsys CLK_AUD_A2SYS>,
+				 <&audsys CLK_AUD_AFE_MRGIF>;
 
-		clock-names = "top_audio_mux1_sel",
+			clock-names = "infra_sys_audio_clk",
+				      "top_audio_mux1_sel",
 				      "top_audio_mux2_sel",
+				      "top_audio_a1sys_hp",
+				      "top_audio_a2sys_hp",
 				      "i2s0_src_sel",
 				      "i2s1_src_sel",
 				      "i2s2_src_sel",
@@ -127,3 +141,4 @@ Example:
 						 <&topckgen CLK_TOP_AUD2PLL_90M>;
 			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 		};
+	};