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Commit 7f5f518f authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/bios: remove object accessor functions 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 53003941
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Showing with 881 additions and 970 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
View file @ 7f5f518f
......@@ -178,18 +178,4 @@ nv_mo32(void *obj, u64 addr, u32 mask, u32 data)
nv_wo32(obj, addr, (temp & ~mask) | data);
return temp;
}
static inline int
nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
{
unsigned char c1, c2;
while (len--) {
c1 = nv_ro08(obj, addr++);
c2 = *(str++);
if (c1 != c2)
return c1 - c2;
}
return 0;
}
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
View file @ 7f5f518f
......@@ -27,6 +27,11 @@ nvkm_bios(void *obj)
u8 nvbios_checksum(const u8 *data, int size);
u16 nvbios_findstr(const u8 *data, int size, const char *str, int len);
int nvbios_memcmp(struct nvkm_bios *, u32 addr, const char *, u32 len);
#define nvbios_rd08(b,o) (b)->data[(o)]
#define nvbios_rd16(b,o) get_unaligned_le16(&(b)->data[(o)])
#define nvbios_rd32(b,o) get_unaligned_le32(&(b)->data[(o)])
extern struct nvkm_oclass nvkm_bios_oclass;
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
View file @ 7f5f518f
......@@ -4,8 +4,8 @@ static inline u16
bmp_version(struct nvkm_bios *bios)
{
if (bios->bmp_offset) {
return nv_ro08(bios, bios->bmp_offset + 5) << 8 |
nv_ro08(bios, bios->bmp_offset + 6);
return nvbios_rd08(bios, bios->bmp_offset + 5) << 8 |
nvbios_rd08(bios, bios->bmp_offset + 6);
}
return 0x0000;
......@@ -15,7 +15,7 @@ static inline u16
bmp_mem_init_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 24);
return nvbios_rd16(bios, bios->bmp_offset + 24);
return 0x0000;
}
......@@ -23,7 +23,7 @@ static inline u16
bmp_sdr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 26);
return nvbios_rd16(bios, bios->bmp_offset + 26);
return 0x0000;
}
......@@ -31,7 +31,7 @@ static inline u16
bmp_ddr_seq_table(struct nvkm_bios *bios)
{
if (bmp_version(bios) >= 0x0300)
return nv_ro16(bios, bios->bmp_offset + 28);
return nvbios_rd16(bios, bios->bmp_offset + 28);
return 0x0000;
}
#endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
View file @ 7f5f518f
......@@ -69,13 +69,13 @@ dp_set_link_config(struct dp_state *dp)
/* set desired link configuration on the source */
if ((lnkcmp = dp->outp->info.lnkcmp)) {
if (outp->version < 0x30) {
while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
while ((dp->link_bw / 10) < nvbios_rd16(bios, lnkcmp))
lnkcmp += 4;
init.offset = nv_ro16(bios, lnkcmp + 2);
init.offset = nvbios_rd16(bios, lnkcmp + 2);
} else {
while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
while ((dp->link_bw / 27000) < nvbios_rd08(bios, lnkcmp))
lnkcmp += 3;
init.offset = nv_ro16(bios, lnkcmp + 1);
init.offset = nvbios_rd16(bios, lnkcmp + 1);
}
nvbios_exec(&init);
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.c
View file @ 7f5f518f
......@@ -33,14 +33,14 @@ nvbios_M0203Te(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 2 && bit_M.length > 0x04)
data = nv_ro16(bios, bit_M.offset + 0x03);
data = nvbios_rd16(bios, bit_M.offset + 0x03);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
*ver = nvbios_rd08(bios, data + 0x00);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*cnt = nv_ro08(bios, data + 0x03);
*hdr = nvbios_rd08(bios, data + 0x01);
*len = nvbios_rd08(bios, data + 0x02);
*cnt = nvbios_rd08(bios, data + 0x03);
return data;
default:
break;
......@@ -59,8 +59,8 @@ nvbios_M0203Tp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->type = nv_ro08(bios, data + 0x04);
info->pointer = nv_ro16(bios, data + 0x05);
info->type = nvbios_rd08(bios, data + 0x04);
info->pointer = nvbios_rd16(bios, data + 0x05);
break;
default:
break;
......@@ -89,9 +89,9 @@ nvbios_M0203Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->type = (nv_ro08(bios, data + 0x00) & 0x0f) >> 0;
info->strap = (nv_ro08(bios, data + 0x00) & 0xf0) >> 4;
info->group = (nv_ro08(bios, data + 0x01) & 0x0f) >> 0;
info->type = (nvbios_rd08(bios, data + 0x00) & 0x0f) >> 0;
info->strap = (nvbios_rd08(bios, data + 0x00) & 0xf0) >> 4;
info->group = (nvbios_rd08(bios, data + 0x01) & 0x0f) >> 0;
return data;
default:
break;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.c
View file @ 7f5f518f
......@@ -34,16 +34,16 @@ nvbios_M0205Te(struct nvkm_bios *bios,
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 2 && bit_M.length > 0x08)
data = nv_ro32(bios, bit_M.offset + 0x05);
data = nvbios_rd32(bios, bit_M.offset + 0x05);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
*ver = nvbios_rd08(bios, data + 0x00);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*ssz = nv_ro08(bios, data + 0x03);
*snr = nv_ro08(bios, data + 0x04);
*cnt = nv_ro08(bios, data + 0x05);
*hdr = nvbios_rd08(bios, data + 0x01);
*len = nvbios_rd08(bios, data + 0x02);
*ssz = nvbios_rd08(bios, data + 0x03);
*snr = nvbios_rd08(bios, data + 0x04);
*cnt = nvbios_rd08(bios, data + 0x05);
return data;
default:
break;
......@@ -63,7 +63,7 @@ nvbios_M0205Tp(struct nvkm_bios *bios,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->freq = nv_ro16(bios, data + 0x06);
info->freq = nvbios_rd16(bios, data + 0x06);
break;
default:
break;
......@@ -96,7 +96,7 @@ nvbios_M0205Ep(struct nvkm_bios *bios, int idx,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->type = nv_ro08(bios, data + 0x00) & 0x0f;
info->type = nvbios_rd08(bios, data + 0x00) & 0x0f;
return data;
default:
break;
......@@ -126,7 +126,7 @@ nvbios_M0205Sp(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->data = nv_ro08(bios, data + 0x00);
info->data = nvbios_rd08(bios, data + 0x00);
return data;
default:
break;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c
View file @ 7f5f518f
......@@ -34,16 +34,16 @@ nvbios_M0209Te(struct nvkm_bios *bios,
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 2 && bit_M.length > 0x0c)
data = nv_ro32(bios, bit_M.offset + 0x09);
data = nvbios_rd32(bios, bit_M.offset + 0x09);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
*ver = nvbios_rd08(bios, data + 0x00);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*ssz = nv_ro08(bios, data + 0x03);
*hdr = nvbios_rd08(bios, data + 0x01);
*len = nvbios_rd08(bios, data + 0x02);
*ssz = nvbios_rd08(bios, data + 0x03);
*snr = 1;
*cnt = nv_ro08(bios, data + 0x04);
*cnt = nvbios_rd08(bios, data + 0x04);
return data;
default:
break;
......@@ -78,12 +78,12 @@ nvbios_M0209Ep(struct nvkm_bios *bios, int idx,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->v00_40 = (nv_ro08(bios, data + 0x00) & 0x40) >> 6;
info->bits = nv_ro08(bios, data + 0x00) & 0x3f;
info->modulo = nv_ro08(bios, data + 0x01);
info->v02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
info->v02_07 = nv_ro08(bios, data + 0x02) & 0x07;
info->v03 = nv_ro08(bios, data + 0x03);
info->v00_40 = (nvbios_rd08(bios, data + 0x00) & 0x40) >> 6;
info->bits = nvbios_rd08(bios, data + 0x00) & 0x3f;
info->modulo = nvbios_rd08(bios, data + 0x01);
info->v02_40 = (nvbios_rd08(bios, data + 0x02) & 0x40) >> 6;
info->v02_07 = nvbios_rd08(bios, data + 0x02) & 0x07;
info->v03 = nvbios_rd08(bios, data + 0x03);
return data;
default:
break;
......@@ -122,7 +122,7 @@ nvbios_M0209Sp(struct nvkm_bios *bios, int ent, int idx, u8 *ver, u8 *hdr,
u32 mask = (1ULL << M0209E.bits) - 1;
u16 off = bits / 8;
u8 mod = bits % 8;
info->data[i] = nv_ro32(bios, data + off);
info->data[i] = nvbios_rd32(bios, data + off);
info->data[i] = info->data[i] >> mod;
info->data[i] = info->data[i] & mask;
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.c
View file @ 7f5f518f
......@@ -34,15 +34,15 @@ nvbios_P0260Te(struct nvkm_bios *bios,
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2 && bit_P.length > 0x63)
data = nv_ro32(bios, bit_P.offset + 0x60);
data = nvbios_rd32(bios, bit_P.offset + 0x60);
if (data) {
*ver = nv_ro08(bios, data + 0);
*ver = nvbios_rd08(bios, data + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, data + 1);
*cnt = nv_ro08(bios, data + 2);
*hdr = nvbios_rd08(bios, data + 1);
*cnt = nvbios_rd08(bios, data + 2);
*len = 4;
*xnr = nv_ro08(bios, data + 3);
*xnr = nvbios_rd08(bios, data + 3);
*xsz = 4;
return data;
default:
......@@ -72,7 +72,7 @@ nvbios_P0260Ep(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->data = nv_ro32(bios, data);
info->data = nvbios_rd32(bios, data);
return data;
default:
break;
......@@ -98,7 +98,7 @@ nvbios_P0260Xp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x10:
info->data = nv_ro32(bios, data);
info->data = nvbios_rd32(bios, data);
return data;
default:
break;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
View file @ 7f5f518f
......@@ -52,6 +52,20 @@ nvbios_findstr(const u8 *data, int size, const char *str, int len)
return 0;
}
int
nvbios_memcmp(struct nvkm_bios *bios, u32 addr, const char *str, u32 len)
{
unsigned char c1, c2;
while (len--) {
c1 = nvbios_rd08(bios, addr++);
c2 = *(str++);
if (c1 != c2)
return c1 - c2;
}
return 0;
}
int
nvbios_extend(struct nvkm_bios *bios, u32 length)
{
......@@ -69,48 +83,6 @@ nvbios_extend(struct nvkm_bios *bios, u32 length)
return 0;
}
static u8
nvkm_bios_rd08(struct nvkm_object *object, u64 addr)
{
struct nvkm_bios *bios = (void *)object;
return bios->data[addr];
}
static u16
nvkm_bios_rd16(struct nvkm_object *object, u64 addr)
{
struct nvkm_bios *bios = (void *)object;
return get_unaligned_le16(&bios->data[addr]);
}
static u32
nvkm_bios_rd32(struct nvkm_object *object, u64 addr)
{
struct nvkm_bios *bios = (void *)object;
return get_unaligned_le32(&bios->data[addr]);
}
static void
nvkm_bios_wr08(struct nvkm_object *object, u64 addr, u8 data)
{
struct nvkm_bios *bios = (void *)object;
bios->data[addr] = data;
}
static void
nvkm_bios_wr16(struct nvkm_object *object, u64 addr, u16 data)
{
struct nvkm_bios *bios = (void *)object;
put_unaligned_le16(data, &bios->data[addr]);
}
static void
nvkm_bios_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
struct nvkm_bios *bios = (void *)object;
put_unaligned_le32(data, &bios->data[addr]);
}
static int
nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
......@@ -146,17 +118,17 @@ nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
/* determine the vbios version number */
if (!bit_entry(bios, 'i', &bit_i) && bit_i.length >= 4) {
bios->version.major = nv_ro08(bios, bit_i.offset + 3);
bios->version.chip = nv_ro08(bios, bit_i.offset + 2);
bios->version.minor = nv_ro08(bios, bit_i.offset + 1);
bios->version.micro = nv_ro08(bios, bit_i.offset + 0);
bios->version.patch = nv_ro08(bios, bit_i.offset + 4);
bios->version.major = nvbios_rd08(bios, bit_i.offset + 3);
bios->version.chip = nvbios_rd08(bios, bit_i.offset + 2);
bios->version.minor = nvbios_rd08(bios, bit_i.offset + 1);
bios->version.micro = nvbios_rd08(bios, bit_i.offset + 0);
bios->version.patch = nvbios_rd08(bios, bit_i.offset + 4);
} else
if (bmp_version(bios)) {
bios->version.major = nv_ro08(bios, bios->bmp_offset + 13);
bios->version.chip = nv_ro08(bios, bios->bmp_offset + 12);
bios->version.minor = nv_ro08(bios, bios->bmp_offset + 11);
bios->version.micro = nv_ro08(bios, bios->bmp_offset + 10);
bios->version.major = nvbios_rd08(bios, bios->bmp_offset + 13);
bios->version.chip = nvbios_rd08(bios, bios->bmp_offset + 12);
bios->version.minor = nvbios_rd08(bios, bios->bmp_offset + 11);
bios->version.micro = nvbios_rd08(bios, bios->bmp_offset + 10);
}
nvkm_info(&bios->subdev, "version %02x.%02x.%02x.%02x.%02x\n",
......@@ -195,11 +167,5 @@ nvkm_bios_oclass = {
.dtor = nvkm_bios_dtor,
.init = nvkm_bios_init,
.fini = nvkm_bios_fini,
.rd08 = nvkm_bios_rd08,
.rd16 = nvkm_bios_rd16,
.rd32 = nvkm_bios_rd32,
.wr08 = nvkm_bios_wr08,
.wr16 = nvkm_bios_wr16,
.wr32 = nvkm_bios_wr32,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.c
View file @ 7f5f518f
......@@ -28,18 +28,18 @@ int
bit_entry(struct nvkm_bios *bios, u8 id, struct bit_entry *bit)
{
if (likely(bios->bit_offset)) {
u8 entries = nv_ro08(bios, bios->bit_offset + 10);
u8 entries = nvbios_rd08(bios, bios->bit_offset + 10);
u32 entry = bios->bit_offset + 12;
while (entries--) {
if (nv_ro08(bios, entry + 0) == id) {
bit->id = nv_ro08(bios, entry + 0);
bit->version = nv_ro08(bios, entry + 1);
bit->length = nv_ro16(bios, entry + 2);
bit->offset = nv_ro16(bios, entry + 4);
if (nvbios_rd08(bios, entry + 0) == id) {
bit->id = nvbios_rd08(bios, entry + 0);
bit->version = nvbios_rd08(bios, entry + 1);
bit->length = nvbios_rd16(bios, entry + 2);
bit->offset = nvbios_rd16(bios, entry + 4);
return 0;
}
entry += nv_ro08(bios, bios->bit_offset + 9);
entry += nvbios_rd08(bios, bios->bit_offset + 9);
}
return -ENOENT;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
View file @ 7f5f518f
......@@ -34,17 +34,17 @@ nvbios_boostTe(struct nvkm_bios *bios,
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
boost = nv_ro16(bios, bit_P.offset + 0x30);
boost = nvbios_rd16(bios, bit_P.offset + 0x30);
if (boost) {
*ver = nv_ro08(bios, boost + 0);
*ver = nvbios_rd08(bios, boost + 0);
switch (*ver) {
case 0x11:
*hdr = nv_ro08(bios, boost + 1);
*cnt = nv_ro08(bios, boost + 5);
*len = nv_ro08(bios, boost + 2);
*snr = nv_ro08(bios, boost + 4);
*ssz = nv_ro08(bios, boost + 3);
*hdr = nvbios_rd08(bios, boost + 1);
*cnt = nvbios_rd08(bios, boost + 5);
*len = nvbios_rd08(bios, boost + 2);
*snr = nvbios_rd08(bios, boost + 4);
*ssz = nvbios_rd08(bios, boost + 3);
return boost;
default:
break;
......@@ -78,9 +78,9 @@ nvbios_boostEp(struct nvkm_bios *bios, int idx,
u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
info->min = nv_ro16(bios, data + 0x02) * 1000;
info->max = nv_ro16(bios, data + 0x04) * 1000;
info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5;
info->min = nvbios_rd16(bios, data + 0x02) * 1000;
info->max = nvbios_rd16(bios, data + 0x04) * 1000;
}
return data;
}
......@@ -117,10 +117,10 @@ nvbios_boostSp(struct nvkm_bios *bios, int idx,
data = nvbios_boostSe(bios, idx, data, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
info->domain = nv_ro08(bios, data + 0x00);
info->percent = nv_ro08(bios, data + 0x01);
info->min = nv_ro16(bios, data + 0x02) * 1000;
info->max = nv_ro16(bios, data + 0x04) * 1000;
info->domain = nvbios_rd08(bios, data + 0x00);
info->percent = nvbios_rd08(bios, data + 0x01);
info->min = nvbios_rd16(bios, data + 0x02) * 1000;
info->max = nvbios_rd16(bios, data + 0x04) * 1000;
}
return data;
}
drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.c
View file @ 7f5f518f
......@@ -30,12 +30,12 @@ nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u32 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb && *ver >= 0x30 && *hdr >= 0x16) {
u32 data = nv_ro16(bios, dcb + 0x14);
u32 data = nvbios_rd16(bios, dcb + 0x14);
if (data) {
*ver = nv_ro08(bios, data + 0);
*hdr = nv_ro08(bios, data + 1);
*cnt = nv_ro08(bios, data + 2);
*len = nv_ro08(bios, data + 3);
*ver = nvbios_rd08(bios, data + 0);
*hdr = nvbios_rd08(bios, data + 1);
*cnt = nvbios_rd08(bios, data + 2);
*len = nvbios_rd08(bios, data + 3);
return data;
}
}
......@@ -77,18 +77,18 @@ nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len,
switch (!!data * *ver) {
case 0x30:
case 0x40:
info->type = nv_ro08(bios, data + 0x00);
info->location = nv_ro08(bios, data + 0x01) & 0x0f;
info->hpd = (nv_ro08(bios, data + 0x01) & 0x30) >> 4;
info->dp = (nv_ro08(bios, data + 0x01) & 0xc0) >> 6;
info->type = nvbios_rd08(bios, data + 0x00);
info->location = nvbios_rd08(bios, data + 0x01) & 0x0f;
info->hpd = (nvbios_rd08(bios, data + 0x01) & 0x30) >> 4;
info->dp = (nvbios_rd08(bios, data + 0x01) & 0xc0) >> 6;
if (*len < 4)
return data;
info->hpd |= (nv_ro08(bios, data + 0x02) & 0x03) << 2;
info->dp |= nv_ro08(bios, data + 0x02) & 0x0c;
info->di = (nv_ro08(bios, data + 0x02) & 0xf0) >> 4;
info->hpd |= (nv_ro08(bios, data + 0x03) & 0x07) << 4;
info->sr = (nv_ro08(bios, data + 0x03) & 0x08) >> 3;
info->lcdid = (nv_ro08(bios, data + 0x03) & 0x70) >> 4;
info->hpd |= (nvbios_rd08(bios, data + 0x02) & 0x03) << 2;
info->dp |= nvbios_rd08(bios, data + 0x02) & 0x0c;
info->di = (nvbios_rd08(bios, data + 0x02) & 0xf0) >> 4;
info->hpd |= (nvbios_rd08(bios, data + 0x03) & 0x07) << 4;
info->sr = (nvbios_rd08(bios, data + 0x03) & 0x08) >> 3;
info->lcdid = (nvbios_rd08(bios, data + 0x03) & 0x70) >> 4;
return data;
default:
break;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
View file @ 7f5f518f
......@@ -34,17 +34,17 @@ nvbios_cstepTe(struct nvkm_bios *bios,
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
cstep = nv_ro16(bios, bit_P.offset + 0x34);
cstep = nvbios_rd16(bios, bit_P.offset + 0x34);
if (cstep) {
*ver = nv_ro08(bios, cstep + 0);
*ver = nvbios_rd08(bios, cstep + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, cstep + 1);
*cnt = nv_ro08(bios, cstep + 3);
*len = nv_ro08(bios, cstep + 2);
*xnr = nv_ro08(bios, cstep + 5);
*xsz = nv_ro08(bios, cstep + 4);
*hdr = nvbios_rd08(bios, cstep + 1);
*cnt = nvbios_rd08(bios, cstep + 3);
*len = nvbios_rd08(bios, cstep + 2);
*xnr = nvbios_rd08(bios, cstep + 5);
*xsz = nvbios_rd08(bios, cstep + 4);
return cstep;
default:
break;
......@@ -75,8 +75,8 @@ nvbios_cstepEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
u16 data = nvbios_cstepEe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
info->index = nv_ro08(bios, data + 0x03);
info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5;
info->index = nvbios_rd08(bios, data + 0x03);
}
return data;
}
......@@ -113,10 +113,10 @@ nvbios_cstepXp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
u16 data = nvbios_cstepXe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->freq = nv_ro16(bios, data + 0x00) * 1000;
info->unkn[0] = nv_ro08(bios, data + 0x02);
info->unkn[1] = nv_ro08(bios, data + 0x03);
info->voltage = nv_ro08(bios, data + 0x04);
info->freq = nvbios_rd16(bios, data + 0x00) * 1000;
info->unkn[0] = nvbios_rd08(bios, data + 0x02);
info->unkn[1] = nvbios_rd08(bios, data + 0x03);
info->voltage = nvbios_rd08(bios, data + 0x04);
}
return data;
}
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
View file @ 7f5f518f
......@@ -32,29 +32,29 @@ dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
u16 dcb = 0x0000;
if (device->card_type > NV_04)
dcb = nv_ro16(bios, 0x36);
dcb = nvbios_rd16(bios, 0x36);
if (!dcb) {
nvkm_warn(subdev, "DCB table not found\n");
return dcb;
}
*ver = nv_ro08(bios, dcb);
*ver = nvbios_rd08(bios, dcb);
if (*ver >= 0x42) {
nvkm_warn(subdev, "DCB version 0x%02x unknown\n", *ver);
return 0x0000;
} else
if (*ver >= 0x30) {
if (nv_ro32(bios, dcb + 6) == 0x4edcbdcb) {
*hdr = nv_ro08(bios, dcb + 1);
*cnt = nv_ro08(bios, dcb + 2);
*len = nv_ro08(bios, dcb + 3);
if (nvbios_rd32(bios, dcb + 6) == 0x4edcbdcb) {
*hdr = nvbios_rd08(bios, dcb + 1);
*cnt = nvbios_rd08(bios, dcb + 2);
*len = nvbios_rd08(bios, dcb + 3);
return dcb;
}
} else
if (*ver >= 0x20) {
if (nv_ro32(bios, dcb + 4) == 0x4edcbdcb) {
u16 i2c = nv_ro16(bios, dcb + 2);
if (nvbios_rd32(bios, dcb + 4) == 0x4edcbdcb) {
u16 i2c = nvbios_rd16(bios, dcb + 2);
*hdr = 8;
*cnt = (i2c - dcb) / 8;
*len = 8;
......@@ -62,8 +62,8 @@ dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
} else
if (*ver >= 0x15) {
if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
u16 i2c = nv_ro16(bios, dcb + 2);
if (!nvbios_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
u16 i2c = nvbios_rd16(bios, dcb + 2);
*hdr = 4;
*cnt = (i2c - dcb) / 10;
*len = 10;
......@@ -125,7 +125,7 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len,
memset(outp, 0x00, sizeof(*outp));
if (dcb) {
if (*ver >= 0x20) {
u32 conn = nv_ro32(bios, dcb + 0x00);
u32 conn = nvbios_rd32(bios, dcb + 0x00);
outp->or = (conn & 0x0f000000) >> 24;
outp->location = (conn & 0x00300000) >> 20;
outp->bus = (conn & 0x000f0000) >> 16;
......@@ -139,7 +139,7 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len,
}
if (*ver >= 0x40) {
u32 conf = nv_ro32(bios, dcb + 0x04);
u32 conf = nvbios_rd32(bios, dcb + 0x04);
switch (outp->type) {
case DCB_OUTPUT_DP:
switch (conf & 0x00e00000) {
......@@ -213,14 +213,14 @@ dcb_outp_foreach(struct nvkm_bios *bios, void *data,
u16 outp;
while ((outp = dcb_outp(bios, ++idx, &ver, &len))) {
if (nv_ro32(bios, outp) == 0x00000000)
if (nvbios_rd32(bios, outp) == 0x00000000)
break; /* seen on an NV11 with DCB v1.5 */
if (nv_ro32(bios, outp) == 0xffffffff)
if (nvbios_rd32(bios, outp) == 0xffffffff)
break; /* seen on an NV17 with DCB v2.0 */
if (nv_ro08(bios, outp) == DCB_OUTPUT_UNUSED)
if (nvbios_rd08(bios, outp) == DCB_OUTPUT_UNUSED)
continue;
if (nv_ro08(bios, outp) == DCB_OUTPUT_EOL)
if (nvbios_rd08(bios, outp) == DCB_OUTPUT_EOL)
break;
ret = exec(bios, data, idx, outp);
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c
View file @ 7f5f518f
......@@ -33,17 +33,17 @@ nvbios_disp_table(struct nvkm_bios *bios,
if (!bit_entry(bios, 'U', &U)) {
if (U.version == 1) {
u16 data = nv_ro16(bios, U.offset);
u16 data = nvbios_rd16(bios, U.offset);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
*ver = nvbios_rd08(bios, data + 0x00);
switch (*ver) {
case 0x20:
case 0x21:
case 0x22:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*cnt = nv_ro08(bios, data + 0x03);
*sub = nv_ro08(bios, data + 0x04);
*hdr = nvbios_rd08(bios, data + 0x01);
*len = nvbios_rd08(bios, data + 0x02);
*cnt = nvbios_rd08(bios, data + 0x03);
*sub = nvbios_rd08(bios, data + 0x04);
return data;
default:
break;
......@@ -72,7 +72,7 @@ nvbios_disp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, u8 *sub,
{
u16 data = nvbios_disp_entry(bios, idx, ver, len, sub);
if (data && *len >= 2) {
info->data = nv_ro16(bios, data + 0);
info->data = nvbios_rd16(bios, data + 0);
return data;
}
return 0x0000;
......@@ -85,7 +85,7 @@ nvbios_outp_entry(struct nvkm_bios *bios, u8 idx,
struct nvbios_disp info;
u16 data = nvbios_disp_parse(bios, idx, ver, len, hdr, &info);
if (data) {
*cnt = nv_ro08(bios, info.data + 0x05);
*cnt = nvbios_rd08(bios, info.data + 0x05);
*len = 0x06;
data = info.data;
}
......@@ -98,15 +98,15 @@ nvbios_outp_parse(struct nvkm_bios *bios, u8 idx,
{
u16 data = nvbios_outp_entry(bios, idx, ver, hdr, cnt, len);
if (data && *hdr >= 0x0a) {
info->type = nv_ro16(bios, data + 0x00);
info->mask = nv_ro32(bios, data + 0x02);
info->type = nvbios_rd16(bios, data + 0x00);
info->mask = nvbios_rd32(bios, data + 0x02);
if (*ver <= 0x20) /* match any link */
info->mask |= 0x00c0;
info->script[0] = nv_ro16(bios, data + 0x06);
info->script[1] = nv_ro16(bios, data + 0x08);
info->script[0] = nvbios_rd16(bios, data + 0x06);
info->script[1] = nvbios_rd16(bios, data + 0x08);
info->script[2] = 0x0000;
if (*hdr >= 0x0c)
info->script[2] = nv_ro16(bios, data + 0x0a);
info->script[2] = nvbios_rd16(bios, data + 0x0a);
return data;
}
return 0x0000;
......@@ -141,9 +141,9 @@ nvbios_ocfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
{
u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len);
if (data) {
info->match = nv_ro16(bios, data + 0x00);
info->clkcmp[0] = nv_ro16(bios, data + 0x02);
info->clkcmp[1] = nv_ro16(bios, data + 0x04);
info->match = nvbios_rd16(bios, data + 0x00);
info->clkcmp[0] = nvbios_rd16(bios, data + 0x02);
info->clkcmp[1] = nvbios_rd16(bios, data + 0x04);
}
return data;
}
......@@ -164,8 +164,8 @@ u16
nvbios_oclk_match(struct nvkm_bios *bios, u16 cmp, u32 khz)
{
while (cmp) {
if (khz / 10 >= nv_ro16(bios, cmp + 0x00))
return nv_ro16(bios, cmp + 0x02);
if (khz / 10 >= nvbios_rd16(bios, cmp + 0x00))
return nvbios_rd16(bios, cmp + 0x02);
cmp += 0x04;
}
return 0x0000;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
View file @ 7f5f518f
......@@ -32,17 +32,17 @@ nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (!bit_entry(bios, 'd', &d)) {
if (d.version == 1 && d.length >= 2) {
u16 data = nv_ro16(bios, d.offset);
u16 data = nvbios_rd16(bios, d.offset);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
*ver = nvbios_rd08(bios, data + 0x00);
switch (*ver) {
case 0x21:
case 0x30:
case 0x40:
case 0x41:
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*cnt = nv_ro08(bios, data + 0x03);
*hdr = nvbios_rd08(bios, data + 0x01);
*len = nvbios_rd08(bios, data + 0x02);
*cnt = nvbios_rd08(bios, data + 0x03);
return data;
default:
break;
......@@ -60,17 +60,17 @@ nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx,
{
u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
if (data && idx < *cnt) {
u16 outp = nv_ro16(bios, data + *hdr + idx * *len);
u16 outp = nvbios_rd16(bios, data + *hdr + idx * *len);
switch (*ver * !!outp) {
case 0x21:
case 0x30:
*hdr = nv_ro08(bios, data + 0x04);
*len = nv_ro08(bios, data + 0x05);
*cnt = nv_ro08(bios, outp + 0x04);
*hdr = nvbios_rd08(bios, data + 0x04);
*len = nvbios_rd08(bios, data + 0x05);
*cnt = nvbios_rd08(bios, outp + 0x04);
break;
case 0x40:
case 0x41:
*hdr = nv_ro08(bios, data + 0x04);
*hdr = nvbios_rd08(bios, data + 0x04);
*cnt = 0;
*len = 0;
break;
......@@ -91,31 +91,31 @@ nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx,
u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data && *ver) {
info->type = nv_ro16(bios, data + 0x00);
info->mask = nv_ro16(bios, data + 0x02);
info->type = nvbios_rd16(bios, data + 0x00);
info->mask = nvbios_rd16(bios, data + 0x02);
switch (*ver) {
case 0x21:
case 0x30:
info->flags = nv_ro08(bios, data + 0x05);
info->script[0] = nv_ro16(bios, data + 0x06);
info->script[1] = nv_ro16(bios, data + 0x08);
info->lnkcmp = nv_ro16(bios, data + 0x0a);
info->flags = nvbios_rd08(bios, data + 0x05);
info->script[0] = nvbios_rd16(bios, data + 0x06);
info->script[1] = nvbios_rd16(bios, data + 0x08);
info->lnkcmp = nvbios_rd16(bios, data + 0x0a);
if (*len >= 0x0f) {
info->script[2] = nv_ro16(bios, data + 0x0c);
info->script[3] = nv_ro16(bios, data + 0x0e);
info->script[2] = nvbios_rd16(bios, data + 0x0c);
info->script[3] = nvbios_rd16(bios, data + 0x0e);
}
if (*len >= 0x11)
info->script[4] = nv_ro16(bios, data + 0x10);
info->script[4] = nvbios_rd16(bios, data + 0x10);
break;
case 0x40:
case 0x41:
info->flags = nv_ro08(bios, data + 0x04);
info->script[0] = nv_ro16(bios, data + 0x05);
info->script[1] = nv_ro16(bios, data + 0x07);
info->lnkcmp = nv_ro16(bios, data + 0x09);
info->script[2] = nv_ro16(bios, data + 0x0b);
info->script[3] = nv_ro16(bios, data + 0x0d);
info->script[4] = nv_ro16(bios, data + 0x0f);
info->flags = nvbios_rd08(bios, data + 0x04);
info->script[0] = nvbios_rd16(bios, data + 0x05);
info->script[1] = nvbios_rd16(bios, data + 0x07);
info->lnkcmp = nvbios_rd16(bios, data + 0x09);
info->script[2] = nvbios_rd16(bios, data + 0x0b);
info->script[3] = nvbios_rd16(bios, data + 0x0d);
info->script[4] = nvbios_rd16(bios, data + 0x0f);
break;
default:
data = 0x0000;
......@@ -147,9 +147,9 @@ nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
if (*ver >= 0x40) {
outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
*hdr = *hdr + (*len * * cnt);
*len = nv_ro08(bios, outp + 0x06);
*cnt = nv_ro08(bios, outp + 0x07) *
nv_ro08(bios, outp + 0x05);
*len = nvbios_rd08(bios, outp + 0x06);
*cnt = nvbios_rd08(bios, outp + 0x07) *
nvbios_rd08(bios, outp + 0x05);
}
if (idx < *cnt)
......@@ -168,17 +168,17 @@ nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
if (data) {
switch (*ver) {
case 0x21:
info->dc = nv_ro08(bios, data + 0x02);
info->pe = nv_ro08(bios, data + 0x03);
info->tx_pu = nv_ro08(bios, data + 0x04);
info->dc = nvbios_rd08(bios, data + 0x02);
info->pe = nvbios_rd08(bios, data + 0x03);
info->tx_pu = nvbios_rd08(bios, data + 0x04);
break;
case 0x30:
case 0x40:
case 0x41:
info->pc = nv_ro08(bios, data + 0x00);
info->dc = nv_ro08(bios, data + 0x01);
info->pe = nv_ro08(bios, data + 0x02);
info->tx_pu = nv_ro08(bios, data + 0x03);
info->pc = nvbios_rd08(bios, data + 0x00);
info->dc = nvbios_rd08(bios, data + 0x01);
info->pe = nvbios_rd08(bios, data + 0x02);
info->tx_pu = nvbios_rd08(bios, data + 0x03);
break;
default:
data = 0x0000;
......@@ -200,12 +200,12 @@ nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
const u8 vsoff[] = { 0, 4, 7, 9 };
idx = (pc * 10) + vsoff[vs] + pe;
if (*ver >= 0x40 && *hdr >= 0x12)
idx += nv_ro08(bios, outp + 0x11) * 40;
idx += nvbios_rd08(bios, outp + 0x11) * 40;
} else {
while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
ver, hdr, cnt, len))) {
if (nv_ro08(bios, data + 0x00) == vs &&
nv_ro08(bios, data + 0x01) == pe)
if (nvbios_rd08(bios, data + 0x00) == vs &&
nvbios_rd08(bios, data + 0x01) == pe)
break;
}
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c
View file @ 7f5f518f
......@@ -35,14 +35,14 @@ extdev_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
if (!dcb || (dcb_ver != 0x30 && dcb_ver != 0x40))
return 0x0000;
extdev = nv_ro16(bios, dcb + 18);
extdev = nvbios_rd16(bios, dcb + 18);
if (!extdev)
return 0x0000;
*ver = nv_ro08(bios, extdev + 0);
*hdr = nv_ro08(bios, extdev + 1);
*cnt = nv_ro08(bios, extdev + 2);
*len = nv_ro08(bios, extdev + 3);
*ver = nvbios_rd08(bios, extdev + 0);
*hdr = nvbios_rd08(bios, extdev + 1);
*cnt = nvbios_rd08(bios, extdev + 2);
*len = nvbios_rd08(bios, extdev + 3);
return extdev + *hdr;
}
......@@ -60,9 +60,9 @@ static void
extdev_parse_entry(struct nvkm_bios *bios, u16 offset,
struct nvbios_extdev_func *entry)
{
entry->type = nv_ro08(bios, offset + 0);
entry->addr = nv_ro08(bios, offset + 1);
entry->bus = (nv_ro08(bios, offset + 2) >> 4) & 1;
entry->type = nvbios_rd08(bios, offset + 0);
entry->addr = nvbios_rd08(bios, offset + 1);
entry->bus = (nvbios_rd08(bios, offset + 2) >> 4) & 1;
}
int
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
View file @ 7f5f518f
......@@ -33,15 +33,15 @@ nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2 && bit_P.length >= 0x5a)
fan = nv_ro16(bios, bit_P.offset + 0x58);
fan = nvbios_rd16(bios, bit_P.offset + 0x58);
if (fan) {
*ver = nv_ro08(bios, fan + 0);
*ver = nvbios_rd08(bios, fan + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, fan + 1);
*len = nv_ro08(bios, fan + 2);
*cnt = nv_ro08(bios, fan + 3);
*hdr = nvbios_rd08(bios, fan + 1);
*len = nvbios_rd08(bios, fan + 2);
*cnt = nvbios_rd08(bios, fan + 3);
return fan;
default:
break;
......@@ -69,7 +69,7 @@ nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
u16 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len);
if (data) {
u8 type = nv_ro08(bios, data + 0x00);
u8 type = nvbios_rd08(bios, data + 0x00);
switch (type) {
case 0:
fan->type = NVBIOS_THERM_FAN_TOGGLE;
......@@ -83,10 +83,10 @@ nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
fan->type = NVBIOS_THERM_FAN_UNK;
}
fan->min_duty = nv_ro08(bios, data + 0x02);
fan->max_duty = nv_ro08(bios, data + 0x03);
fan->min_duty = nvbios_rd08(bios, data + 0x02);
fan->max_duty = nvbios_rd08(bios, data + 0x03);
fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff;
fan->pwm_freq = nvbios_rd32(bios, data + 0x0b) & 0xffffff;
}
return data;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.c
View file @ 7f5f518f
......@@ -33,22 +33,22 @@ dcb_gpio_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb) {
if (*ver >= 0x30 && *hdr >= 0x0c)
data = nv_ro16(bios, dcb + 0x0a);
data = nvbios_rd16(bios, dcb + 0x0a);
else
if (*ver >= 0x22 && nv_ro08(bios, dcb - 1) >= 0x13)
data = nv_ro16(bios, dcb - 0x0f);
if (*ver >= 0x22 && nvbios_rd08(bios, dcb - 1) >= 0x13)
data = nvbios_rd16(bios, dcb - 0x0f);
if (data) {
*ver = nv_ro08(bios, data + 0x00);
*ver = nvbios_rd08(bios, data + 0x00);
if (*ver < 0x30) {
*hdr = 3;
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x01);
*cnt = nvbios_rd08(bios, data + 0x02);
*len = nvbios_rd08(bios, data + 0x01);
} else
if (*ver <= 0x41) {
*hdr = nv_ro08(bios, data + 0x01);
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x03);
*hdr = nvbios_rd08(bios, data + 0x01);
*cnt = nvbios_rd08(bios, data + 0x02);
*len = nvbios_rd08(bios, data + 0x03);
} else {
data = 0x0000;
}
......@@ -81,7 +81,7 @@ dcb_gpio_parse(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len,
u16 data = dcb_gpio_entry(bios, idx, ent, ver, len);
if (data) {
if (*ver < 0x40) {
u16 info = nv_ro16(bios, data);
u16 info = nvbios_rd16(bios, data);
*gpio = (struct dcb_gpio_func) {
.line = (info & 0x001f) >> 0,
.func = (info & 0x07e0) >> 5,
......@@ -91,7 +91,7 @@ dcb_gpio_parse(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len,
};
} else
if (*ver < 0x41) {
u32 info = nv_ro32(bios, data);
u32 info = nvbios_rd32(bios, data);
*gpio = (struct dcb_gpio_func) {
.line = (info & 0x0000001f) >> 0,
.func = (info & 0x0000ff00) >> 8,
......@@ -100,8 +100,8 @@ dcb_gpio_parse(struct nvkm_bios *bios, int idx, int ent, u8 *ver, u8 *len,
.param = !!(info & 0x80000000),
};
} else {
u32 info = nv_ro32(bios, data + 0);
u8 info1 = nv_ro32(bios, data + 4);
u32 info = nvbios_rd32(bios, data + 0);
u8 info1 = nvbios_rd32(bios, data + 4);
*gpio = (struct dcb_gpio_func) {
.line = (info & 0x0000003f) >> 0,
.func = (info & 0x0000ff00) >> 8,
......@@ -131,8 +131,8 @@ dcb_gpio_match(struct nvkm_bios *bios, int idx, u8 func, u8 line,
/* DCB 2.2, fixed TVDAC GPIO data */
if ((data = dcb_table(bios, ver, &hdr, &cnt, len))) {
if (*ver >= 0x22 && *ver < 0x30 && func == DCB_GPIO_TVDAC0) {
u8 conf = nv_ro08(bios, data - 5);
u8 addr = nv_ro08(bios, data - 4);
u8 conf = nvbios_rd08(bios, data - 5);
u8 addr = nvbios_rd08(bios, data - 4);
if (conf & 0x01) {
*gpio = (struct dcb_gpio_func) {
.func = DCB_GPIO_TVDAC0,
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
View file @ 7f5f518f
......@@ -32,9 +32,9 @@ dcb_i2c_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb) {
if (*ver >= 0x15)
i2c = nv_ro16(bios, dcb + 2);
i2c = nvbios_rd16(bios, dcb + 2);
if (*ver >= 0x30)
i2c = nv_ro16(bios, dcb + 4);
i2c = nvbios_rd16(bios, dcb + 4);
}
if (i2c && *ver >= 0x42) {
......@@ -43,10 +43,10 @@ dcb_i2c_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
if (i2c && *ver >= 0x30) {
*ver = nv_ro08(bios, i2c + 0);
*hdr = nv_ro08(bios, i2c + 1);
*cnt = nv_ro08(bios, i2c + 2);
*len = nv_ro08(bios, i2c + 3);
*ver = nvbios_rd08(bios, i2c + 0);
*hdr = nvbios_rd08(bios, i2c + 1);
*cnt = nvbios_rd08(bios, i2c + 2);
*len = nvbios_rd08(bios, i2c + 3);
} else {
*ver = *ver; /* use DCB version */
*hdr = 0;
......@@ -75,7 +75,7 @@ dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info)
u16 ent = dcb_i2c_entry(bios, idx, &ver, &len);
if (ent) {
if (ver >= 0x41) {
u32 ent_value = nv_ro32(bios, ent);
u32 ent_value = nvbios_rd32(bios, ent);
u8 i2c_port = (ent_value >> 27) & 0x1f;
u8 dpaux_port = (ent_value >> 22) & 0x1f;
/* value 0x1f means unused according to DCB 4.x spec */
......@@ -85,9 +85,9 @@ dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info)
info->type = DCB_I2C_PMGR;
} else
if (ver >= 0x30) {
info->type = nv_ro08(bios, ent + 0x03);
info->type = nvbios_rd08(bios, ent + 0x03);
} else {
info->type = nv_ro08(bios, ent + 0x03) & 0x07;
info->type = nvbios_rd08(bios, ent + 0x03) & 0x07;
if (info->type == 0x07)
info->type = DCB_I2C_UNUSED;
}
......@@ -99,27 +99,27 @@ dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info)
switch (info->type) {
case DCB_I2C_NV04_BIT:
info->drive = nv_ro08(bios, ent + 0);
info->sense = nv_ro08(bios, ent + 1);
info->drive = nvbios_rd08(bios, ent + 0);
info->sense = nvbios_rd08(bios, ent + 1);
return 0;
case DCB_I2C_NV4E_BIT:
info->drive = nv_ro08(bios, ent + 1);
info->drive = nvbios_rd08(bios, ent + 1);
return 0;
case DCB_I2C_NVIO_BIT:
info->drive = nv_ro08(bios, ent + 0) & 0x0f;
if (nv_ro08(bios, ent + 1) & 0x01)
info->share = nv_ro08(bios, ent + 1) >> 1;
info->drive = nvbios_rd08(bios, ent + 0) & 0x0f;
if (nvbios_rd08(bios, ent + 1) & 0x01)
info->share = nvbios_rd08(bios, ent + 1) >> 1;
return 0;
case DCB_I2C_NVIO_AUX:
info->auxch = nv_ro08(bios, ent + 0) & 0x0f;
if (nv_ro08(bios, ent + 1) & 0x01)
info->auxch = nvbios_rd08(bios, ent + 0) & 0x0f;
if (nvbios_rd08(bios, ent + 1) & 0x01)
info->share = info->auxch;
return 0;
case DCB_I2C_PMGR:
info->drive = (nv_ro16(bios, ent + 0) & 0x01f) >> 0;
info->drive = (nvbios_rd16(bios, ent + 0) & 0x01f) >> 0;
if (info->drive == 0x1f)
info->drive = DCB_I2C_UNUSED;
info->auxch = (nv_ro16(bios, ent + 0) & 0x3e0) >> 5;
info->auxch = (nvbios_rd16(bios, ent + 0) & 0x3e0) >> 5;
if (info->auxch == 0x1f)
info->auxch = DCB_I2C_UNUSED;
info->share = info->auxch;
......@@ -137,21 +137,21 @@ dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info)
/* BMP (from v4.0 has i2c info in the structure, it's in a
* fixed location on earlier VBIOS
*/
if (nv_ro08(bios, bios->bmp_offset + 5) < 4)
if (nvbios_rd08(bios, bios->bmp_offset + 5) < 4)
ent = 0x0048;
else
ent = 0x0036 + bios->bmp_offset;
if (idx == 0) {
info->drive = nv_ro08(bios, ent + 4);
info->drive = nvbios_rd08(bios, ent + 4);
if (!info->drive) info->drive = 0x3f;
info->sense = nv_ro08(bios, ent + 5);
info->sense = nvbios_rd08(bios, ent + 5);
if (!info->sense) info->sense = 0x3e;
} else
if (idx == 1) {
info->drive = nv_ro08(bios, ent + 6);
info->drive = nvbios_rd08(bios, ent + 6);
if (!info->drive) info->drive = 0x37;
info->sense = nv_ro08(bios, ent + 7);
info->sense = nvbios_rd08(bios, ent + 7);
if (!info->sense) info->sense = 0x36;
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
View file @ 7f5f518f
......@@ -36,7 +36,7 @@ nvbios_imagen(struct nvkm_bios *bios, struct nvbios_image *image)
u16 hdr;
u32 data;
switch ((data = nv_ro16(bios, image->base + 0x00))) {
switch ((data = nvbios_rd16(bios, image->base + 0x00))) {
case 0xaa55:
case 0xbb77:
case 0x4e56: /* NV */
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
View file @ 7f5f518f
......@@ -78,14 +78,14 @@ mxm_sor_map(struct nvkm_bios *bios, u8 conn)
u8 ver, hdr;
u16 mxm = mxm_table(bios, &ver, &hdr);
if (mxm && hdr >= 6) {
u16 map = nv_ro16(bios, mxm + 4);
u16 map = nvbios_rd16(bios, mxm + 4);
if (map) {
ver = nv_ro08(bios, map);
ver = nvbios_rd08(bios, map);
if (ver == 0x10) {
if (conn < nv_ro08(bios, map + 3)) {
map += nv_ro08(bios, map + 1);
if (conn < nvbios_rd08(bios, map + 3)) {
map += nvbios_rd08(bios, map + 1);
map += conn;
return nv_ro08(bios, map);
return nvbios_rd08(bios, map);
}
return 0x00;
......@@ -115,14 +115,14 @@ mxm_ddc_map(struct nvkm_bios *bios, u8 port)
u8 ver, hdr;
u16 mxm = mxm_table(bios, &ver, &hdr);
if (mxm && hdr >= 8) {
u16 map = nv_ro16(bios, mxm + 6);
u16 map = nvbios_rd16(bios, mxm + 6);
if (map) {
ver = nv_ro08(bios, map);
ver = nvbios_rd08(bios, map);
if (ver == 0x10) {
if (port < nv_ro08(bios, map + 3)) {
map += nv_ro08(bios, map + 1);
if (port < nvbios_rd08(bios, map + 3)) {
map += nvbios_rd08(bios, map + 1);
map += port;
return nv_ro08(bios, map);
return nvbios_rd08(bios, map);
}
return 0x00;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
View file @ 7f5f518f
......@@ -32,13 +32,13 @@ nvbios_npdeTe(struct nvkm_bios *bios, u32 base)
u8 ver; u16 hdr;
u32 data = nvbios_pcirTp(bios, base, &ver, &hdr, &pcir);
if (data = (data + hdr + 0x0f) & ~0x0f, data) {
switch (nv_ro32(bios, data + 0x00)) {
switch (nvbios_rd32(bios, data + 0x00)) {
case 0x4544504e: /* NPDE */
break;
default:
nvkm_debug(&bios->subdev,
"%08x: NPDE signature (%08x) unknown\n",
data, nv_ro32(bios, data + 0x00));
data, nvbios_rd32(bios, data + 0x00));
data = 0;
break;
}
......@@ -52,8 +52,8 @@ nvbios_npdeTp(struct nvkm_bios *bios, u32 base, struct nvbios_npdeT *info)
u32 data = nvbios_npdeTe(bios, base);
memset(info, 0x00, sizeof(*info));
if (data) {
info->image_size = nv_ro16(bios, data + 0x08) * 512;
info->last = nv_ro08(bios, data + 0x0a) & 0x80;
info->image_size = nvbios_rd16(bios, data + 0x08) * 512;
info->last = nvbios_rd08(bios, data + 0x0a) & 0x80;
}
return data;
}
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
View file @ 7f5f518f
......@@ -27,20 +27,20 @@
u32
nvbios_pcirTe(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr)
{
u32 data = nv_ro16(bios, base + 0x18);
u32 data = nvbios_rd16(bios, base + 0x18);
if (data) {
data += base;
switch (nv_ro32(bios, data + 0x00)) {
switch (nvbios_rd32(bios, data + 0x00)) {
case 0x52494350: /* PCIR */
case 0x53494752: /* RGIS */
case 0x5344504e: /* NPDS */
*hdr = nv_ro16(bios, data + 0x0a);
*ver = nv_ro08(bios, data + 0x0c);
*hdr = nvbios_rd16(bios, data + 0x0a);
*ver = nvbios_rd08(bios, data + 0x0c);
break;
default:
nvkm_debug(&bios->subdev,
"%08x: PCIR signature (%08x) unknown\n",
data, nv_ro32(bios, data + 0x00));
data, nvbios_rd32(bios, data + 0x00));
data = 0;
break;
}
......@@ -55,15 +55,15 @@ nvbios_pcirTp(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr,
u32 data = nvbios_pcirTe(bios, base, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->vendor_id = nv_ro16(bios, data + 0x04);
info->device_id = nv_ro16(bios, data + 0x06);
info->class_code[0] = nv_ro08(bios, data + 0x0d);
info->class_code[1] = nv_ro08(bios, data + 0x0e);
info->class_code[2] = nv_ro08(bios, data + 0x0f);
info->image_size = nv_ro16(bios, data + 0x10) * 512;
info->image_rev = nv_ro16(bios, data + 0x12);
info->image_type = nv_ro08(bios, data + 0x14);
info->last = nv_ro08(bios, data + 0x15) & 0x80;
info->vendor_id = nvbios_rd16(bios, data + 0x04);
info->device_id = nvbios_rd16(bios, data + 0x06);
info->class_code[0] = nvbios_rd08(bios, data + 0x0d);
info->class_code[1] = nvbios_rd08(bios, data + 0x0e);
info->class_code[2] = nvbios_rd08(bios, data + 0x0f);
info->image_size = nvbios_rd16(bios, data + 0x10) * 512;
info->image_rev = nvbios_rd16(bios, data + 0x12);
info->image_type = nvbios_rd08(bios, data + 0x14);
info->last = nvbios_rd08(bios, data + 0x15) & 0x80;
}
return data;
}
drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
View file @ 7f5f518f
......@@ -34,22 +34,22 @@ nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version <= 2) {
perf = nv_ro16(bios, bit_P.offset + 0);
perf = nvbios_rd16(bios, bit_P.offset + 0);
if (perf) {
*ver = nv_ro08(bios, perf + 0);
*hdr = nv_ro08(bios, perf + 1);
*ver = nvbios_rd08(bios, perf + 0);
*hdr = nvbios_rd08(bios, perf + 1);
if (*ver >= 0x40 && *ver < 0x41) {
*cnt = nv_ro08(bios, perf + 5);
*len = nv_ro08(bios, perf + 2);
*snr = nv_ro08(bios, perf + 4);
*ssz = nv_ro08(bios, perf + 3);
*cnt = nvbios_rd08(bios, perf + 5);
*len = nvbios_rd08(bios, perf + 2);
*snr = nvbios_rd08(bios, perf + 4);
*ssz = nvbios_rd08(bios, perf + 3);
return perf;
} else
if (*ver >= 0x20 && *ver < 0x40) {
*cnt = nv_ro08(bios, perf + 2);
*len = nv_ro08(bios, perf + 3);
*snr = nv_ro08(bios, perf + 4);
*ssz = nv_ro08(bios, perf + 5);
*cnt = nvbios_rd08(bios, perf + 2);
*len = nvbios_rd08(bios, perf + 3);
*snr = nvbios_rd08(bios, perf + 4);
*ssz = nvbios_rd08(bios, perf + 5);
return perf;
}
}
......@@ -57,13 +57,13 @@ nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
}
if (bios->bmp_offset) {
if (nv_ro08(bios, bios->bmp_offset + 6) >= 0x25) {
perf = nv_ro16(bios, bios->bmp_offset + 0x94);
if (nvbios_rd08(bios, bios->bmp_offset + 6) >= 0x25) {
perf = nvbios_rd16(bios, bios->bmp_offset + 0x94);
if (perf) {
*hdr = nv_ro08(bios, perf + 0);
*ver = nv_ro08(bios, perf + 1);
*cnt = nv_ro08(bios, perf + 2);
*len = nv_ro08(bios, perf + 3);
*hdr = nvbios_rd08(bios, perf + 0);
*ver = nvbios_rd08(bios, perf + 1);
*cnt = nvbios_rd08(bios, perf + 2);
*len = nvbios_rd08(bios, perf + 3);
*snr = 0;
*ssz = 0;
return perf;
......@@ -96,55 +96,55 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx,
{
u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
info->pstate = nv_ro08(bios, perf + 0x00);
info->pstate = nvbios_rd08(bios, perf + 0x00);
switch (!!perf * *ver) {
case 0x12:
case 0x13:
case 0x14:
info->core = nv_ro32(bios, perf + 0x01) * 10;
info->memory = nv_ro32(bios, perf + 0x05) * 20;
info->fanspeed = nv_ro08(bios, perf + 0x37);
info->core = nvbios_rd32(bios, perf + 0x01) * 10;
info->memory = nvbios_rd32(bios, perf + 0x05) * 20;
info->fanspeed = nvbios_rd08(bios, perf + 0x37);
if (*hdr > 0x38)
info->voltage = nv_ro08(bios, perf + 0x38);
info->voltage = nvbios_rd08(bios, perf + 0x38);
break;
case 0x21:
case 0x23:
case 0x24:
info->fanspeed = nv_ro08(bios, perf + 0x04);
info->voltage = nv_ro08(bios, perf + 0x05);
info->shader = nv_ro16(bios, perf + 0x06) * 1000;
info->fanspeed = nvbios_rd08(bios, perf + 0x04);
info->voltage = nvbios_rd08(bios, perf + 0x05);
info->shader = nvbios_rd16(bios, perf + 0x06) * 1000;
info->core = info->shader + (signed char)
nv_ro08(bios, perf + 0x08) * 1000;
nvbios_rd08(bios, perf + 0x08) * 1000;
switch (nv_device(bios)->chipset) {
case 0x49:
case 0x4b:
info->memory = nv_ro16(bios, perf + 0x0b) * 1000;
info->memory = nvbios_rd16(bios, perf + 0x0b) * 1000;
break;
default:
info->memory = nv_ro16(bios, perf + 0x0b) * 2000;
info->memory = nvbios_rd16(bios, perf + 0x0b) * 2000;
break;
}
break;
case 0x25:
info->fanspeed = nv_ro08(bios, perf + 0x04);
info->voltage = nv_ro08(bios, perf + 0x05);
info->core = nv_ro16(bios, perf + 0x06) * 1000;
info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
info->fanspeed = nvbios_rd08(bios, perf + 0x04);
info->voltage = nvbios_rd08(bios, perf + 0x05);
info->core = nvbios_rd16(bios, perf + 0x06) * 1000;
info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
break;
case 0x30:
info->script = nv_ro16(bios, perf + 0x02);
info->script = nvbios_rd16(bios, perf + 0x02);
case 0x35:
info->fanspeed = nv_ro08(bios, perf + 0x06);
info->voltage = nv_ro08(bios, perf + 0x07);
info->core = nv_ro16(bios, perf + 0x08) * 1000;
info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
info->vdec = nv_ro16(bios, perf + 0x10) * 1000;
info->disp = nv_ro16(bios, perf + 0x14) * 1000;
info->fanspeed = nvbios_rd08(bios, perf + 0x06);
info->voltage = nvbios_rd08(bios, perf + 0x07);
info->core = nvbios_rd16(bios, perf + 0x08) * 1000;
info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
info->vdec = nvbios_rd16(bios, perf + 0x10) * 1000;
info->disp = nvbios_rd16(bios, perf + 0x14) * 1000;
break;
case 0x40:
info->voltage = nv_ro08(bios, perf + 0x02);
info->voltage = nvbios_rd08(bios, perf + 0x02);
break;
default:
return 0x0000;
......@@ -173,7 +173,7 @@ nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x40:
info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000;
info->v40.freq = (nvbios_rd16(bios, data + 0x00) & 0x3fff) * 1000;
break;
default:
break;
......@@ -191,7 +191,7 @@ nvbios_perf_fan_parse(struct nvkm_bios *bios,
return -ENODEV;
if (ver >= 0x20 && ver < 0x40 && hdr > 6)
fan->pwm_divisor = nv_ro16(bios, perf + 6);
fan->pwm_divisor = nvbios_rd16(bios, perf + 6);
else
fan->pwm_divisor = 0;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
View file @ 7f5f518f
......@@ -83,20 +83,20 @@ pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
struct bit_entry bit_C;
if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) {
u16 data = nv_ro16(bios, bit_C.offset + 8);
u16 data = nvbios_rd16(bios, bit_C.offset + 8);
if (data) {
*ver = nv_ro08(bios, data + 0);
*hdr = nv_ro08(bios, data + 1);
*len = nv_ro08(bios, data + 2);
*cnt = nv_ro08(bios, data + 3);
*ver = nvbios_rd08(bios, data + 0);
*hdr = nvbios_rd08(bios, data + 1);
*len = nvbios_rd08(bios, data + 2);
*cnt = nvbios_rd08(bios, data + 3);
return data;
}
}
if (bmp_version(bios) >= 0x0524) {
u16 data = nv_ro16(bios, bios->bmp_offset + 142);
u16 data = nvbios_rd16(bios, bios->bmp_offset + 142);
if (data) {
*ver = nv_ro08(bios, data + 0);
*ver = nvbios_rd08(bios, data + 0);
*hdr = 1;
*cnt = 1;
*len = 0x18;
......@@ -145,8 +145,8 @@ pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
if (data && *ver >= 0x30) {
data += hdr;
while (cnt--) {
if (nv_ro32(bios, data + 3) == reg) {
*type = nv_ro08(bios, data + 0);
if (nvbios_rd32(bios, data + 3) == reg) {
*type = nvbios_rd08(bios, data + 0);
return data;
}
data += *len;
......@@ -160,7 +160,7 @@ pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
u16 addr = (data += hdr);
*type = map->type;
while (cnt--) {
if (nv_ro32(bios, data) == map->reg)
if (nvbios_rd32(bios, data) == map->reg)
return data;
data += *len;
}
......@@ -187,8 +187,8 @@ pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
if (data && *ver >= 0x30) {
data += hdr;
while (cnt--) {
if (nv_ro08(bios, data + 0) == type) {
*reg = nv_ro32(bios, data + 3);
if (nvbios_rd08(bios, data + 0) == type) {
*reg = nvbios_rd32(bios, data + 3);
return data;
}
data += *len;
......@@ -202,7 +202,7 @@ pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
u16 addr = (data += hdr);
*reg = map->reg;
while (cnt--) {
if (nv_ro32(bios, data) == map->reg)
if (nvbios_rd32(bios, data) == map->reg)
return data;
data += *len;
}
......@@ -246,12 +246,12 @@ nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
break;
case 0x10:
case 0x11:
info->vco1.min_freq = nv_ro32(bios, data + 0);
info->vco1.max_freq = nv_ro32(bios, data + 4);
info->vco2.min_freq = nv_ro32(bios, data + 8);
info->vco2.max_freq = nv_ro32(bios, data + 12);
info->vco1.min_inputfreq = nv_ro32(bios, data + 16);
info->vco2.min_inputfreq = nv_ro32(bios, data + 20);
info->vco1.min_freq = nvbios_rd32(bios, data + 0);
info->vco1.max_freq = nvbios_rd32(bios, data + 4);
info->vco2.min_freq = nvbios_rd32(bios, data + 8);
info->vco2.max_freq = nvbios_rd32(bios, data + 12);
info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16);
info->vco2.min_inputfreq = nvbios_rd32(bios, data + 20);
info->vco1.max_inputfreq = INT_MAX;
info->vco2.max_inputfreq = INT_MAX;
......@@ -292,69 +292,69 @@ nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
break;
case 0x20:
case 0x21:
info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000;
info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000;
info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000;
info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000;
info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000;
info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000;
info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000;
info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000;
info->vco1.min_n = nv_ro08(bios, data + 20);
info->vco1.max_n = nv_ro08(bios, data + 21);
info->vco1.min_m = nv_ro08(bios, data + 22);
info->vco1.max_m = nv_ro08(bios, data + 23);
info->vco2.min_n = nv_ro08(bios, data + 24);
info->vco2.max_n = nv_ro08(bios, data + 25);
info->vco2.min_m = nv_ro08(bios, data + 26);
info->vco2.max_m = nv_ro08(bios, data + 27);
info->max_p = nv_ro08(bios, data + 29);
info->vco1.min_freq = nvbios_rd16(bios, data + 4) * 1000;
info->vco1.max_freq = nvbios_rd16(bios, data + 6) * 1000;
info->vco2.min_freq = nvbios_rd16(bios, data + 8) * 1000;
info->vco2.max_freq = nvbios_rd16(bios, data + 10) * 1000;
info->vco1.min_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
info->vco2.min_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
info->vco1.max_inputfreq = nvbios_rd16(bios, data + 16) * 1000;
info->vco2.max_inputfreq = nvbios_rd16(bios, data + 18) * 1000;
info->vco1.min_n = nvbios_rd08(bios, data + 20);
info->vco1.max_n = nvbios_rd08(bios, data + 21);
info->vco1.min_m = nvbios_rd08(bios, data + 22);
info->vco1.max_m = nvbios_rd08(bios, data + 23);
info->vco2.min_n = nvbios_rd08(bios, data + 24);
info->vco2.max_n = nvbios_rd08(bios, data + 25);
info->vco2.min_m = nvbios_rd08(bios, data + 26);
info->vco2.max_m = nvbios_rd08(bios, data + 27);
info->max_p = nvbios_rd08(bios, data + 29);
info->max_p_usable = info->max_p;
if (bios->version.chip < 0x60)
info->max_p_usable = 0x6;
info->bias_p = nv_ro08(bios, data + 30);
info->bias_p = nvbios_rd08(bios, data + 30);
if (len > 0x22)
info->refclk = nv_ro32(bios, data + 31);
info->refclk = nvbios_rd32(bios, data + 31);
break;
case 0x30:
data = nv_ro16(bios, data + 1);
info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000;
info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000;
info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000;
info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000;
info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000;
info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000;
info->vco1.min_n = nv_ro08(bios, data + 16);
info->vco1.max_n = nv_ro08(bios, data + 17);
info->vco1.min_m = nv_ro08(bios, data + 18);
info->vco1.max_m = nv_ro08(bios, data + 19);
info->vco2.min_n = nv_ro08(bios, data + 20);
info->vco2.max_n = nv_ro08(bios, data + 21);
info->vco2.min_m = nv_ro08(bios, data + 22);
info->vco2.max_m = nv_ro08(bios, data + 23);
info->max_p_usable = info->max_p = nv_ro08(bios, data + 25);
info->bias_p = nv_ro08(bios, data + 27);
info->refclk = nv_ro32(bios, data + 28);
data = nvbios_rd16(bios, data + 1);
info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
info->vco2.min_freq = nvbios_rd16(bios, data + 4) * 1000;
info->vco2.max_freq = nvbios_rd16(bios, data + 6) * 1000;
info->vco1.min_inputfreq = nvbios_rd16(bios, data + 8) * 1000;
info->vco2.min_inputfreq = nvbios_rd16(bios, data + 10) * 1000;
info->vco1.max_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
info->vco2.max_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
info->vco1.min_n = nvbios_rd08(bios, data + 16);
info->vco1.max_n = nvbios_rd08(bios, data + 17);
info->vco1.min_m = nvbios_rd08(bios, data + 18);
info->vco1.max_m = nvbios_rd08(bios, data + 19);
info->vco2.min_n = nvbios_rd08(bios, data + 20);
info->vco2.max_n = nvbios_rd08(bios, data + 21);
info->vco2.min_m = nvbios_rd08(bios, data + 22);
info->vco2.max_m = nvbios_rd08(bios, data + 23);
info->max_p_usable = info->max_p = nvbios_rd08(bios, data + 25);
info->bias_p = nvbios_rd08(bios, data + 27);
info->refclk = nvbios_rd32(bios, data + 28);
break;
case 0x40:
info->refclk = nv_ro16(bios, data + 9) * 1000;
data = nv_ro16(bios, data + 1);
info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000;
info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000;
info->vco1.min_m = nv_ro08(bios, data + 8);
info->vco1.max_m = nv_ro08(bios, data + 9);
info->vco1.min_n = nv_ro08(bios, data + 10);
info->vco1.max_n = nv_ro08(bios, data + 11);
info->min_p = nv_ro08(bios, data + 12);
info->max_p = nv_ro08(bios, data + 13);
info->refclk = nvbios_rd16(bios, data + 9) * 1000;
data = nvbios_rd16(bios, data + 1);
info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
info->vco1.min_inputfreq = nvbios_rd16(bios, data + 4) * 1000;
info->vco1.max_inputfreq = nvbios_rd16(bios, data + 6) * 1000;
info->vco1.min_m = nvbios_rd08(bios, data + 8);
info->vco1.max_m = nvbios_rd08(bios, data + 9);
info->vco1.min_n = nvbios_rd08(bios, data + 10);
info->vco1.max_n = nvbios_rd08(bios, data + 11);
info->min_p = nvbios_rd08(bios, data + 12);
info->max_p = nvbios_rd08(bios, data + 13);
break;
default:
nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver);
......@@ -381,8 +381,8 @@ nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
* with an empty limit table (seen on nv18)
*/
if (!info->vco1.max_freq) {
info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67);
info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71);
info->vco1.max_freq = nvbios_rd32(bios, bios->bmp_offset + 67);
info->vco1.min_freq = nvbios_rd32(bios, bios->bmp_offset + 71);
if (bmp_version(bios) < 0x0506) {
info->vco1.max_freq = 256000;
info->vco1.min_freq = 128000;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c
View file @ 7f5f518f
......@@ -49,12 +49,12 @@ nvbios_pmuTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (!bit_entry(bios, 'p', &bit_p)) {
if (bit_p.version == 2 && bit_p.length >= 4)
data = nv_ro32(bios, bit_p.offset + 0x00);
data = nvbios_rd32(bios, bit_p.offset + 0x00);
if ((data = weirdo_pointer(bios, data))) {
*ver = nv_ro08(bios, data + 0x00); /* maybe? */
*hdr = nv_ro08(bios, data + 0x01);
*len = nv_ro08(bios, data + 0x02);
*cnt = nv_ro08(bios, data + 0x03);
*ver = nvbios_rd08(bios, data + 0x00); /* maybe? */
*hdr = nvbios_rd08(bios, data + 0x01);
*len = nvbios_rd08(bios, data + 0x02);
*cnt = nvbios_rd08(bios, data + 0x03);
}
}
......@@ -95,8 +95,8 @@ nvbios_pmuEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr,
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
default:
info->type = nv_ro08(bios, data + 0x00);
info->data = nv_ro32(bios, data + 0x02);
info->type = nvbios_rd08(bios, data + 0x00);
info->data = nvbios_rd32(bios, data + 0x02);
break;
}
return data;
......@@ -112,21 +112,21 @@ nvbios_pmuRm(struct nvkm_bios *bios, u8 type, struct nvbios_pmuR *info)
while ((data = nvbios_pmuEp(bios, idx++, &ver, &hdr, &pmuE))) {
if ( pmuE.type == type &&
(data = weirdo_pointer(bios, pmuE.data))) {
info->init_addr_pmu = nv_ro32(bios, data + 0x08);
info->args_addr_pmu = nv_ro32(bios, data + 0x0c);
info->init_addr_pmu = nvbios_rd32(bios, data + 0x08);
info->args_addr_pmu = nvbios_rd32(bios, data + 0x0c);
info->boot_addr = data + 0x30;
info->boot_addr_pmu = nv_ro32(bios, data + 0x10) +
nv_ro32(bios, data + 0x18);
info->boot_size = nv_ro32(bios, data + 0x1c) -
nv_ro32(bios, data + 0x18);
info->boot_addr_pmu = nvbios_rd32(bios, data + 0x10) +
nvbios_rd32(bios, data + 0x18);
info->boot_size = nvbios_rd32(bios, data + 0x1c) -
nvbios_rd32(bios, data + 0x18);
info->code_addr = info->boot_addr + info->boot_size;
info->code_addr_pmu = info->boot_addr_pmu +
info->boot_size;
info->code_size = nv_ro32(bios, data + 0x20);
info->code_size = nvbios_rd32(bios, data + 0x20);
info->data_addr = data + 0x30 +
nv_ro32(bios, data + 0x24);
info->data_addr_pmu = nv_ro32(bios, data + 0x28);
info->data_size = nv_ro32(bios, data + 0x2c);
nvbios_rd32(bios, data + 0x24);
info->data_addr_pmu = nvbios_rd32(bios, data + 0x28);
info->data_size = nvbios_rd32(bios, data + 0x2c);
return true;
}
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
View file @ 7f5f518f
......@@ -39,9 +39,9 @@ nvbios_ramcfg_count(struct nvkm_bios *bios)
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 1 && bit_M.length >= 5)
return nv_ro08(bios, bit_M.offset + 2);
return nvbios_rd08(bios, bit_M.offset + 2);
if (bit_M.version == 2 && bit_M.length >= 3)
return nv_ro08(bios, bit_M.offset + 0);
return nvbios_rd08(bios, bit_M.offset + 0);
}
return 0x00;
......@@ -59,7 +59,7 @@ nvbios_ramcfg_index(struct nvkm_subdev *subdev)
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 1 && bit_M.length >= 5)
xlat = nv_ro16(bios, bit_M.offset + 3);
xlat = nvbios_rd16(bios, bit_M.offset + 3);
if (bit_M.version == 2 && bit_M.length >= 3) {
/*XXX: is M ever shorter than this?
* if not - what is xlat used for now?
......@@ -68,11 +68,11 @@ nvbios_ramcfg_index(struct nvkm_subdev *subdev)
if (bit_M.length >= 7 &&
nvbios_M0203Em(bios, strap, &ver, &hdr, &M0203E))
return M0203E.group;
xlat = nv_ro16(bios, bit_M.offset + 1);
xlat = nvbios_rd16(bios, bit_M.offset + 1);
}
}
if (xlat)
strap = nv_ro08(bios, xlat + strap);
strap = nvbios_rd08(bios, xlat + strap);
return strap;
}
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
View file @ 7f5f518f
......@@ -28,7 +28,6 @@
#include <subdev/bios/image.h>
struct shadow {
struct nvkm_oclass base;
u32 skip;
const struct nvbios_source *func;
void *data;
......@@ -37,9 +36,8 @@ struct shadow {
};
static bool
shadow_fetch(struct nvkm_bios *bios, u32 upto)
shadow_fetch(struct nvkm_bios *bios, struct shadow *mthd, u32 upto)
{
struct shadow *mthd = (void *)nv_object(bios)->oclass;
const u32 limit = (upto + 3) & ~3;
const u32 start = bios->size;
void *data = mthd->data;
......@@ -50,50 +48,18 @@ shadow_fetch(struct nvkm_bios *bios, u32 upto)
return bios->size >= limit;
}
static u8
shadow_rd08(struct nvkm_object *object, u64 addr)
{
struct nvkm_bios *bios = (void *)object;
if (shadow_fetch(bios, addr + 1))
return bios->data[addr];
return 0x00;
}
static u16
shadow_rd16(struct nvkm_object *object, u64 addr)
{
struct nvkm_bios *bios = (void *)object;
if (shadow_fetch(bios, addr + 2))
return get_unaligned_le16(&bios->data[addr]);
return 0x0000;
}
static u32
shadow_rd32(struct nvkm_object *object, u64 addr)
{
struct nvkm_bios *bios = (void *)object;
if (shadow_fetch(bios, addr + 4))
return get_unaligned_le32(&bios->data[addr]);
return 0x00000000;
}
static struct nvkm_oclass
shadow_class = {
.handle = NV_SUBDEV(VBIOS, 0x00),
.ofuncs = &(struct nvkm_ofuncs) {
.rd08 = shadow_rd08,
.rd16 = shadow_rd16,
.rd32 = shadow_rd32,
},
};
static int
shadow_image(struct nvkm_bios *bios, int idx, struct shadow *mthd)
shadow_image(struct nvkm_bios *bios, int idx, u32 offset, struct shadow *mthd)
{
struct nvkm_subdev *subdev = &bios->subdev;
struct nvbios_image image;
int score = 1;
if (!shadow_fetch(bios, mthd, offset + 0x1000)) {
nvkm_debug(subdev, "%08x: header fetch failed\n", offset);
return 0;
}
if (!nvbios_image(bios, idx, &image)) {
nvkm_debug(subdev, "image %d invalid\n", idx);
return 0;
......@@ -101,7 +67,7 @@ shadow_image(struct nvkm_bios *bios, int idx, struct shadow *mthd)
nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",
image.base, image.type, image.size);
if (!shadow_fetch(bios, image.size)) {
if (!shadow_fetch(bios, mthd, image.size)) {
nvkm_debug(subdev, "%08x: fetch failed\n", image.base);
return 0;
}
......@@ -124,22 +90,10 @@ shadow_image(struct nvkm_bios *bios, int idx, struct shadow *mthd)
}
if (!image.last)
score += shadow_image(bios, idx + 1, mthd);
score += shadow_image(bios, idx + 1, offset + image.size, mthd);
return score;
}
static int
shadow_score(struct nvkm_bios *bios, struct shadow *mthd)
{
struct nvkm_oclass *oclass = nv_object(bios)->oclass;
int score;
nv_object(bios)->oclass = &mthd->base;
score = shadow_image(bios, 0, mthd);
nv_object(bios)->oclass = oclass;
return score;
}
static int
shadow_method(struct nvkm_bios *bios, struct shadow *mthd, const char *name)
{
......@@ -154,7 +108,7 @@ shadow_method(struct nvkm_bios *bios, struct shadow *mthd, const char *name)
return 0;
}
}
mthd->score = shadow_score(bios, mthd);
mthd->score = shadow_image(bios, 0, 0, mthd);
if (func->fini)
func->fini(mthd->data);
nvkm_debug(subdev, "scored %d\n", mthd->score);
......@@ -203,14 +157,14 @@ nvbios_shadow(struct nvkm_bios *bios)
struct nvkm_subdev *subdev = &bios->subdev;
struct nvkm_device *device = subdev->device;
struct shadow mthds[] = {
{ shadow_class, 0, &nvbios_of },
{ shadow_class, 0, &nvbios_ramin },
{ shadow_class, 0, &nvbios_rom },
{ shadow_class, 0, &nvbios_acpi_fast },
{ shadow_class, 4, &nvbios_acpi_slow },
{ shadow_class, 1, &nvbios_pcirom },
{ shadow_class, 1, &nvbios_platform },
{ shadow_class }
{ 0, &nvbios_of },
{ 0, &nvbios_ramin },
{ 0, &nvbios_rom },
{ 0, &nvbios_acpi_fast },
{ 4, &nvbios_acpi_slow },
{ 1, &nvbios_pcirom },
{ 1, &nvbios_platform },
{}
}, *mthd, *best = NULL;
const char *optarg;
char *source;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
View file @ 7f5f518f
......@@ -33,9 +33,9 @@ therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 1)
therm = nv_ro16(bios, bit_P.offset + 12);
therm = nvbios_rd16(bios, bit_P.offset + 12);
else if (bit_P.version == 2)
therm = nv_ro16(bios, bit_P.offset + 16);
therm = nvbios_rd16(bios, bit_P.offset + 16);
else
nvkm_error(&bios->subdev,
"unknown offset for thermal in BIT P %d\n",
......@@ -46,11 +46,11 @@ therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
if (!therm)
return 0x0000;
*ver = nv_ro08(bios, therm + 0);
*hdr = nv_ro08(bios, therm + 1);
*len = nv_ro08(bios, therm + 2);
*cnt = nv_ro08(bios, therm + 3);
return therm + nv_ro08(bios, therm + 1);
*ver = nvbios_rd08(bios, therm + 0);
*hdr = nvbios_rd08(bios, therm + 1);
*len = nvbios_rd08(bios, therm + 2);
*cnt = nvbios_rd08(bios, therm + 3);
return therm + nvbios_rd08(bios, therm + 1);
}
static u16
......@@ -81,9 +81,9 @@ nvbios_therm_sensor_parse(struct nvkm_bios *bios,
sensor_section = -1;
i = 0;
while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) {
s16 value = nv_ro16(bios, entry + 1);
s16 value = nvbios_rd16(bios, entry + 1);
switch (nv_ro08(bios, entry + 0)) {
switch (nvbios_rd08(bios, entry + 0)) {
case 0x0:
thrs_section = value;
if (value > 0)
......@@ -92,7 +92,7 @@ nvbios_therm_sensor_parse(struct nvkm_bios *bios,
case 0x01:
sensor_section++;
if (sensor_section == 0) {
offset = ((s8) nv_ro08(bios, entry + 2)) / 2;
offset = ((s8) nvbios_rd08(bios, entry + 2)) / 2;
sensor->offset_constant = offset;
}
break;
......@@ -163,9 +163,9 @@ nvbios_therm_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
fan->nr_fan_trip = 0;
fan->fan_mode = NVBIOS_THERM_FAN_OTHER;
while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) {
s16 value = nv_ro16(bios, entry + 1);
s16 value = nvbios_rd16(bios, entry + 1);
switch (nv_ro08(bios, entry + 0)) {
switch (nvbios_rd08(bios, entry + 0)) {
case 0x22:
fan->min_duty = value & 0xff;
fan->max_duty = (value & 0xff00) >> 8;
......@@ -196,8 +196,8 @@ nvbios_therm_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
case 0x46:
if (fan->fan_mode > NVBIOS_THERM_FAN_LINEAR)
fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
fan->linear_min_temp = nv_ro08(bios, entry + 1);
fan->linear_max_temp = nv_ro08(bios, entry + 2);
fan->linear_min_temp = nvbios_rd08(bios, entry + 1);
fan->linear_max_temp = nvbios_rd08(bios, entry + 2);
break;
}
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
View file @ 7f5f518f
......@@ -34,27 +34,27 @@ nvbios_timingTe(struct nvkm_bios *bios,
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 1)
timing = nv_ro16(bios, bit_P.offset + 4);
timing = nvbios_rd16(bios, bit_P.offset + 4);
else
if (bit_P.version == 2)
timing = nv_ro16(bios, bit_P.offset + 8);
timing = nvbios_rd16(bios, bit_P.offset + 8);
if (timing) {
*ver = nv_ro08(bios, timing + 0);
*ver = nvbios_rd08(bios, timing + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, timing + 1);
*cnt = nv_ro08(bios, timing + 2);
*len = nv_ro08(bios, timing + 3);
*hdr = nvbios_rd08(bios, timing + 1);
*cnt = nvbios_rd08(bios, timing + 2);
*len = nvbios_rd08(bios, timing + 3);
*snr = 0;
*ssz = 0;
return timing;
case 0x20:
*hdr = nv_ro08(bios, timing + 1);
*cnt = nv_ro08(bios, timing + 5);
*len = nv_ro08(bios, timing + 2);
*snr = nv_ro08(bios, timing + 4);
*ssz = nv_ro08(bios, timing + 3);
*hdr = nvbios_rd08(bios, timing + 1);
*cnt = nvbios_rd08(bios, timing + 5);
*len = nvbios_rd08(bios, timing + 2);
*snr = nvbios_rd08(bios, timing + 4);
*ssz = nvbios_rd08(bios, timing + 3);
return timing;
default:
break;
......@@ -90,20 +90,20 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
p->timing_hdr = *hdr;
switch (!!data * *ver) {
case 0x10:
p->timing_10_WR = nv_ro08(bios, data + 0x00);
p->timing_10_WTR = nv_ro08(bios, data + 0x01);
p->timing_10_CL = nv_ro08(bios, data + 0x02);
p->timing_10_RC = nv_ro08(bios, data + 0x03);
p->timing_10_RFC = nv_ro08(bios, data + 0x05);
p->timing_10_RAS = nv_ro08(bios, data + 0x07);
p->timing_10_RP = nv_ro08(bios, data + 0x09);
p->timing_10_RCDRD = nv_ro08(bios, data + 0x0a);
p->timing_10_RCDWR = nv_ro08(bios, data + 0x0b);
p->timing_10_RRD = nv_ro08(bios, data + 0x0c);
p->timing_10_13 = nv_ro08(bios, data + 0x0d);
p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
p->timing_10_WR = nvbios_rd08(bios, data + 0x00);
p->timing_10_WTR = nvbios_rd08(bios, data + 0x01);
p->timing_10_CL = nvbios_rd08(bios, data + 0x02);
p->timing_10_RC = nvbios_rd08(bios, data + 0x03);
p->timing_10_RFC = nvbios_rd08(bios, data + 0x05);
p->timing_10_RAS = nvbios_rd08(bios, data + 0x07);
p->timing_10_RP = nvbios_rd08(bios, data + 0x09);
p->timing_10_RCDRD = nvbios_rd08(bios, data + 0x0a);
p->timing_10_RCDWR = nvbios_rd08(bios, data + 0x0b);
p->timing_10_RRD = nvbios_rd08(bios, data + 0x0c);
p->timing_10_13 = nvbios_rd08(bios, data + 0x0d);
p->timing_10_ODT = nvbios_rd08(bios, data + 0x0e) & 0x07;
if (p->ramcfg_ver >= 0x10)
p->ramcfg_RON = nv_ro08(bios, data + 0x0e) & 0x07;
p->ramcfg_RON = nvbios_rd08(bios, data + 0x0e) & 0x07;
p->timing_10_24 = 0xff;
p->timing_10_21 = 0;
......@@ -114,45 +114,45 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
switch (min_t(u8, *hdr, 25)) {
case 25:
p->timing_10_24 = nv_ro08(bios, data + 0x18);
p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
case 24:
case 23:
case 22:
p->timing_10_21 = nv_ro08(bios, data + 0x15);
p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
case 21:
p->timing_10_20 = nv_ro08(bios, data + 0x14);
p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
case 20:
p->timing_10_CWL = nv_ro08(bios, data + 0x13);
p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
case 19:
p->timing_10_18 = nv_ro08(bios, data + 0x12);
p->timing_10_18 = nvbios_rd08(bios, data + 0x12);
case 18:
case 17:
p->timing_10_16 = nv_ro08(bios, data + 0x10);
p->timing_10_16 = nvbios_rd08(bios, data + 0x10);
}
break;
case 0x20:
p->timing[0] = nv_ro32(bios, data + 0x00);
p->timing[1] = nv_ro32(bios, data + 0x04);
p->timing[2] = nv_ro32(bios, data + 0x08);
p->timing[3] = nv_ro32(bios, data + 0x0c);
p->timing[4] = nv_ro32(bios, data + 0x10);
p->timing[5] = nv_ro32(bios, data + 0x14);
p->timing[6] = nv_ro32(bios, data + 0x18);
p->timing[7] = nv_ro32(bios, data + 0x1c);
p->timing[8] = nv_ro32(bios, data + 0x20);
p->timing[9] = nv_ro32(bios, data + 0x24);
p->timing[10] = nv_ro32(bios, data + 0x28);
p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
temp = nv_ro16(bios, data + 0x2c);
p->timing[0] = nvbios_rd32(bios, data + 0x00);
p->timing[1] = nvbios_rd32(bios, data + 0x04);
p->timing[2] = nvbios_rd32(bios, data + 0x08);
p->timing[3] = nvbios_rd32(bios, data + 0x0c);
p->timing[4] = nvbios_rd32(bios, data + 0x10);
p->timing[5] = nvbios_rd32(bios, data + 0x14);
p->timing[6] = nvbios_rd32(bios, data + 0x18);
p->timing[7] = nvbios_rd32(bios, data + 0x1c);
p->timing[8] = nvbios_rd32(bios, data + 0x20);
p->timing[9] = nvbios_rd32(bios, data + 0x24);
p->timing[10] = nvbios_rd32(bios, data + 0x28);
p->timing_20_2e_03 = (nvbios_rd08(bios, data + 0x2e) & 0x03) >> 0;
p->timing_20_2e_30 = (nvbios_rd08(bios, data + 0x2e) & 0x30) >> 4;
p->timing_20_2e_c0 = (nvbios_rd08(bios, data + 0x2e) & 0xc0) >> 6;
p->timing_20_2f_03 = (nvbios_rd08(bios, data + 0x2f) & 0x03) >> 0;
temp = nvbios_rd16(bios, data + 0x2c);
p->timing_20_2c_003f = (temp & 0x003f) >> 0;
p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
temp = nv_ro16(bios, data + 0x31);
p->timing_20_30_07 = (nvbios_rd08(bios, data + 0x30) & 0x07) >> 0;
p->timing_20_30_f8 = (nvbios_rd08(bios, data + 0x30) & 0xf8) >> 3;
temp = nvbios_rd16(bios, data + 0x31);
p->timing_20_31_0007 = (temp & 0x0007) >> 0;
p->timing_20_31_0078 = (temp & 0x0078) >> 3;
p->timing_20_31_0780 = (temp & 0x0780) >> 7;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c
View file @ 7f5f518f
......@@ -33,15 +33,15 @@ nvbios_vmap_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2) {
vmap = nv_ro16(bios, bit_P.offset + 0x20);
vmap = nvbios_rd16(bios, bit_P.offset + 0x20);
if (vmap) {
*ver = nv_ro08(bios, vmap + 0);
*ver = nvbios_rd08(bios, vmap + 0);
switch (*ver) {
case 0x10:
case 0x20:
*hdr = nv_ro08(bios, vmap + 1);
*cnt = nv_ro08(bios, vmap + 3);
*len = nv_ro08(bios, vmap + 2);
*hdr = nvbios_rd08(bios, vmap + 1);
*cnt = nvbios_rd08(bios, vmap + 3);
*len = nvbios_rd08(bios, vmap + 2);
return vmap;
default:
break;
......@@ -88,23 +88,23 @@ nvbios_vmap_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
switch (!!vmap * *ver) {
case 0x10:
info->link = 0xff;
info->min = nv_ro32(bios, vmap + 0x00);
info->max = nv_ro32(bios, vmap + 0x04);
info->arg[0] = nv_ro32(bios, vmap + 0x08);
info->arg[1] = nv_ro32(bios, vmap + 0x0c);
info->arg[2] = nv_ro32(bios, vmap + 0x10);
info->min = nvbios_rd32(bios, vmap + 0x00);
info->max = nvbios_rd32(bios, vmap + 0x04);
info->arg[0] = nvbios_rd32(bios, vmap + 0x08);
info->arg[1] = nvbios_rd32(bios, vmap + 0x0c);
info->arg[2] = nvbios_rd32(bios, vmap + 0x10);
break;
case 0x20:
info->unk0 = nv_ro08(bios, vmap + 0x00);
info->link = nv_ro08(bios, vmap + 0x01);
info->min = nv_ro32(bios, vmap + 0x02);
info->max = nv_ro32(bios, vmap + 0x06);
info->arg[0] = nv_ro32(bios, vmap + 0x0a);
info->arg[1] = nv_ro32(bios, vmap + 0x0e);
info->arg[2] = nv_ro32(bios, vmap + 0x12);
info->arg[3] = nv_ro32(bios, vmap + 0x16);
info->arg[4] = nv_ro32(bios, vmap + 0x1a);
info->arg[5] = nv_ro32(bios, vmap + 0x1e);
info->unk0 = nvbios_rd08(bios, vmap + 0x00);
info->link = nvbios_rd08(bios, vmap + 0x01);
info->min = nvbios_rd32(bios, vmap + 0x02);
info->max = nvbios_rd32(bios, vmap + 0x06);
info->arg[0] = nvbios_rd32(bios, vmap + 0x0a);
info->arg[1] = nvbios_rd32(bios, vmap + 0x0e);
info->arg[2] = nvbios_rd32(bios, vmap + 0x12);
info->arg[3] = nvbios_rd32(bios, vmap + 0x16);
info->arg[4] = nvbios_rd32(bios, vmap + 0x1a);
info->arg[5] = nvbios_rd32(bios, vmap + 0x1e);
break;
}
return vmap;
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c
View file @ 7f5f518f
......@@ -33,30 +33,30 @@ nvbios_volt_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
volt = nv_ro16(bios, bit_P.offset + 0x0c);
volt = nvbios_rd16(bios, bit_P.offset + 0x0c);
else
if (bit_P.version == 1)
volt = nv_ro16(bios, bit_P.offset + 0x10);
volt = nvbios_rd16(bios, bit_P.offset + 0x10);
if (volt) {
*ver = nv_ro08(bios, volt + 0);
*ver = nvbios_rd08(bios, volt + 0);
switch (*ver) {
case 0x12:
*hdr = 5;
*cnt = nv_ro08(bios, volt + 2);
*len = nv_ro08(bios, volt + 1);
*cnt = nvbios_rd08(bios, volt + 2);
*len = nvbios_rd08(bios, volt + 1);
return volt;
case 0x20:
*hdr = nv_ro08(bios, volt + 1);
*cnt = nv_ro08(bios, volt + 2);
*len = nv_ro08(bios, volt + 3);
*hdr = nvbios_rd08(bios, volt + 1);
*cnt = nvbios_rd08(bios, volt + 2);
*len = nvbios_rd08(bios, volt + 3);
return volt;
case 0x30:
case 0x40:
case 0x50:
*hdr = nv_ro08(bios, volt + 1);
*cnt = nv_ro08(bios, volt + 3);
*len = nv_ro08(bios, volt + 2);
*hdr = nvbios_rd08(bios, volt + 1);
*cnt = nvbios_rd08(bios, volt + 3);
*len = nvbios_rd08(bios, volt + 2);
return volt;
}
}
......@@ -73,28 +73,28 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
memset(info, 0x00, sizeof(*info));
switch (!!volt * *ver) {
case 0x12:
info->vidmask = nv_ro08(bios, volt + 0x04);
info->vidmask = nvbios_rd08(bios, volt + 0x04);
break;
case 0x20:
info->vidmask = nv_ro08(bios, volt + 0x05);
info->vidmask = nvbios_rd08(bios, volt + 0x05);
break;
case 0x30:
info->vidmask = nv_ro08(bios, volt + 0x04);
info->vidmask = nvbios_rd08(bios, volt + 0x04);
break;
case 0x40:
info->base = nv_ro32(bios, volt + 0x04);
info->step = nv_ro16(bios, volt + 0x08);
info->vidmask = nv_ro08(bios, volt + 0x0b);
info->base = nvbios_rd32(bios, volt + 0x04);
info->step = nvbios_rd16(bios, volt + 0x08);
info->vidmask = nvbios_rd08(bios, volt + 0x0b);
/*XXX*/
info->min = 0;
info->max = info->base;
break;
case 0x50:
info->vidmask = nv_ro08(bios, volt + 0x06);
info->min = nv_ro32(bios, volt + 0x0a);
info->max = nv_ro32(bios, volt + 0x0e);
info->base = nv_ro32(bios, volt + 0x12) & 0x00ffffff;
info->step = nv_ro16(bios, volt + 0x16);
info->vidmask = nvbios_rd08(bios, volt + 0x06);
info->min = nvbios_rd32(bios, volt + 0x0a);
info->max = nvbios_rd32(bios, volt + 0x0e);
info->base = nvbios_rd32(bios, volt + 0x12) & 0x00ffffff;
info->step = nvbios_rd16(bios, volt + 0x16);
break;
}
return volt;
......@@ -121,12 +121,12 @@ nvbios_volt_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len,
switch (!!volt * *ver) {
case 0x12:
case 0x20:
info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
info->vid = nv_ro08(bios, volt + 0x01);
info->voltage = nvbios_rd08(bios, volt + 0x00) * 10000;
info->vid = nvbios_rd08(bios, volt + 0x01);
break;
case 0x30:
info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
info->vid = nv_ro08(bios, volt + 0x01) >> 2;
info->voltage = nvbios_rd08(bios, volt + 0x00) * 10000;
info->vid = nvbios_rd08(bios, volt + 0x01) >> 2;
break;
case 0x40:
case 0x50:
......
drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.c
View file @ 7f5f518f
......@@ -30,12 +30,12 @@ dcb_xpiod_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 data = dcb_gpio_table(bios, ver, hdr, cnt, len);
if (data && *ver >= 0x40 && *hdr >= 0x06) {
u16 xpio = nv_ro16(bios, data + 0x04);
u16 xpio = nvbios_rd16(bios, data + 0x04);
if (xpio) {
*ver = nv_ro08(bios, data + 0x00);
*hdr = nv_ro08(bios, data + 0x01);
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x03);
*ver = nvbios_rd08(bios, data + 0x00);
*hdr = nvbios_rd08(bios, data + 0x01);
*cnt = nvbios_rd08(bios, data + 0x02);
*len = nvbios_rd08(bios, data + 0x03);
return xpio;
}
}
......@@ -48,12 +48,12 @@ dcb_xpio_table(struct nvkm_bios *bios, u8 idx,
{
u16 data = dcb_xpiod_table(bios, ver, hdr, cnt, len);
if (data && idx < *cnt) {
u16 xpio = nv_ro16(bios, data + *hdr + (idx * *len));
u16 xpio = nvbios_rd16(bios, data + *hdr + (idx * *len));
if (xpio) {
*ver = nv_ro08(bios, data + 0x00);
*hdr = nv_ro08(bios, data + 0x01);
*cnt = nv_ro08(bios, data + 0x02);
*len = nv_ro08(bios, data + 0x03);
*ver = nvbios_rd08(bios, data + 0x00);
*hdr = nvbios_rd08(bios, data + 0x01);
*cnt = nvbios_rd08(bios, data + 0x02);
*len = nvbios_rd08(bios, data + 0x03);
return xpio;
}
}
......@@ -66,9 +66,9 @@ dcb_xpio_parse(struct nvkm_bios *bios, u8 idx,
{
u16 data = dcb_xpio_table(bios, idx, ver, hdr, cnt, len);
if (data && *len >= 6) {
info->type = nv_ro08(bios, data + 0x04);
info->addr = nv_ro08(bios, data + 0x05);
info->flags = nv_ro08(bios, data + 0x06);
info->type = nvbios_rd08(bios, data + 0x04);
info->addr = nvbios_rd08(bios, data + 0x05);
info->flags = nvbios_rd08(bios, data + 0x06);
}
return 0x0000;
}
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
View file @ 7f5f518f
......@@ -38,7 +38,7 @@ pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
for (i = 0; i < len; i += 4) {
if ((i & 0xff) == 0)
nvkm_wr32(device, 0x10a188, (pmu + i) >> 8);
nvkm_wr32(device, 0x10a184, nv_ro32(bios, img + i));
nvkm_wr32(device, 0x10a184, nvbios_rd32(bios, img + i));
}
while (i & 0xff) {
......@@ -56,7 +56,7 @@ pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu);
for (i = 0; i < len; i += 4)
nvkm_wr32(device, 0x10a1c4, nv_ro32(bios, img + i));
nvkm_wr32(device, 0x10a1c4, nvbios_rd32(bios, img + i));
}
static u32
......@@ -138,16 +138,16 @@ gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
/* upload first chunk of init data */
if (post) {
u32 pmu = pmu_args(init, args + 0x08, 0x08);
u32 img = nv_ro16(bios, bit_I.offset + 0x14);
u32 len = nv_ro16(bios, bit_I.offset + 0x16);
u32 img = nvbios_rd16(bios, bit_I.offset + 0x14);
u32 len = nvbios_rd16(bios, bit_I.offset + 0x16);
pmu_data(init, pmu, img, len);
}
/* upload second chunk of init data */
if (post) {
u32 pmu = pmu_args(init, args + 0x08, 0x10);
u32 img = nv_ro16(bios, bit_I.offset + 0x18);
u32 len = nv_ro16(bios, bit_I.offset + 0x1a);
u32 img = nvbios_rd16(bios, bit_I.offset + 0x18);
u32 len = nvbios_rd16(bios, bit_I.offset + 0x1a);
pmu_data(init, pmu, img, len);
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
View file @ 7f5f518f
......@@ -62,8 +62,8 @@ nv05_devinit_meminit(struct nvkm_devinit *init)
strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;
if ((data = bmp_mem_init_table(bios))) {
ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
ramcfg[0] = nvbios_rd08(bios, data + 2 * strap + 0);
ramcfg[1] = nvbios_rd08(bios, data + 2 * strap + 1);
} else {
ramcfg[0] = default_config_tab[strap][0];
ramcfg[1] = default_config_tab[strap][1];
......@@ -80,7 +80,7 @@ nv05_devinit_meminit(struct nvkm_devinit *init)
/* If present load the hardcoded scrambling table */
if (data) {
for (i = 0, data += 0x10; i < 8; i++, data += 4) {
u32 scramble = nv_ro32(bios, data);
u32 scramble = nvbios_rd32(bios, data);
nvkm_wr32(device, NV04_PFB_SCRAMBLE(i), scramble);
}
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
View file @ 7f5f518f
......@@ -165,7 +165,7 @@ gf100_ram_calc(struct nvkm_fb *fb, u32 freq)
}
/* lookup memory timings, if bios says they're present */
strap = nv_ro08(bios, ramcfg.data + 0x01);
strap = nvbios_rd08(bios, ramcfg.data + 0x01);
if (strap != 0xff) {
timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
&cnt, &len);
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
View file @ 7f5f518f
......@@ -1340,8 +1340,8 @@ gk104_ram_init(struct nvkm_object *object)
if (!data || hdr < 0x15)
return -EINVAL;
cnt = nv_ro08(bios, data + 0x14); /* guess at count */
data = nv_ro32(bios, data + 0x10); /* guess u32... */
cnt = nvbios_rd08(bios, data + 0x14); /* guess at count */
data = nvbios_rd32(bios, data + 0x10); /* guess u32... */
save = nvkm_rd32(device, 0x10f65c) & 0x000000f0;
for (i = 0; i < cnt; i++, data += 4) {
if (i != save >> 4) {
......@@ -1349,7 +1349,7 @@ gk104_ram_init(struct nvkm_object *object)
nvbios_exec(&(struct nvbios_init) {
.subdev = nv_subdev(fb),
.bios = bios,
.offset = nv_ro32(bios, data),
.offset = nvbios_rd32(bios, data),
.execute = 1,
});
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
View file @ 7f5f518f
......@@ -154,7 +154,7 @@ nv40_ram_prog(struct nvkm_fb *fb)
struct nvbios_init init = {
.subdev = nv_subdev(fb),
.bios = bios,
.offset = nv_ro16(bios, M.offset + 0x00),
.offset = nvbios_rd16(bios, M.offset + 0x00),
.execute = 1,
};
......
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c
View file @ 7f5f518f
......@@ -33,7 +33,7 @@ gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match)
int ent = -1;
while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
u32 data = nv_ro32(bios, entry);
u32 data = nvbios_rd32(bios, entry);
u8 line = (data & 0x0000003f);
u8 defs = !!(data & 0x00000080);
u8 func = (data & 0x0000ff00) >> 8;
......
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
View file @ 7f5f518f
......@@ -34,7 +34,7 @@ nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
static const u32 regs[] = { 0xe100, 0xe28c };
u32 data = nv_ro32(bios, entry);
u32 data = nvbios_rd32(bios, entry);
u8 line = (data & 0x0000001f);
u8 func = (data & 0x0000ff00) >> 8;
u8 defs = !!(data & 0x01000000);
......
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
View file @ 7f5f518f
......@@ -176,7 +176,7 @@ nvkm_i2c_find(struct nvkm_i2c *i2c, u8 index)
u8 ver, hdr, cnt, len;
u16 i2c = dcb_i2c_table(bios, &ver, &hdr, &cnt, &len);
if (i2c && ver >= 0x30) {
u8 auxidx = nv_ro08(bios, i2c + 4);
u8 auxidx = nvbios_rd08(bios, i2c + 4);
if (index == NV_I2C_DEFAULT(0))
index = (auxidx & 0x0f) >> 0;
else
......
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
View file @ 7f5f518f
......@@ -243,7 +243,7 @@ nvkm_mxm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
return ret;
data = mxm_table(bios, &ver, &len);
if (!data || !(ver = nv_ro08(bios, data))) {
if (!data || !(ver = nvbios_rd08(bios, data))) {
nvkm_debug(&mxm->subdev, "no VBIOS data, nothing to do\n");
return 0;
}
......
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