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Commit 7f83560d authored by David S. Miller's avatar David S. Miller
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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next

parents 87b6d218 8f56e4b9
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Showing with 62 additions and 58 deletions
drivers/net/ethernet/intel/e100.c
View file @ 7f83560d
......@@ -1759,6 +1759,7 @@ static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
skb->data, skb->len, PCI_DMA_TODEVICE));
/* check for mapping failure? */
cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
skb_tx_timestamp(skb);
}
static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
......@@ -2733,6 +2734,7 @@ static const struct ethtool_ops e100_ethtool_ops = {
.set_phys_id = e100_set_phys_id,
.get_ethtool_stats = e100_get_ethtool_stats,
.get_sset_count = e100_get_sset_count,
.get_ts_info = ethtool_op_get_ts_info,
};
static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
......
drivers/net/ethernet/intel/e1000e/80003es2lan.c
View file @ 7f83560d
......@@ -228,9 +228,7 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
/* FWSM register */
mac->has_fwsm = true;
/* ARC supported; valid only if manageability features are enabled. */
mac->arc_subsystem_valid =
(er32(FWSM) & E1000_FWSM_MODE_MASK)
? true : false;
mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
/* Adaptive IFS not supported */
mac->adaptive_ifs = false;
......
drivers/net/ethernet/intel/e1000e/82571.c
View file @ 7f83560d
......@@ -295,9 +295,8 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
* ARC supported; valid only if manageability features are
* enabled.
*/
mac->arc_subsystem_valid =
(er32(FWSM) & E1000_FWSM_MODE_MASK)
? true : false;
mac->arc_subsystem_valid = !!(er32(FWSM) &
E1000_FWSM_MODE_MASK);
break;
case e1000_82574:
case e1000_82583:
......@@ -798,7 +797,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
/* Check for pending operations. */
for (i = 0; i < E1000_FLASH_UPDATES; i++) {
usleep_range(1000, 2000);
if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
if (!(er32(EECD) & E1000_EECD_FLUPD))
break;
}
......@@ -822,7 +821,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
for (i = 0; i < E1000_FLASH_UPDATES; i++) {
usleep_range(1000, 2000);
if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
if (!(er32(EECD) & E1000_EECD_FLUPD))
break;
}
......
drivers/net/ethernet/intel/e1000e/ethtool.c
View file @ 7f83560d
......@@ -259,8 +259,7 @@ static int e1000_set_settings(struct net_device *netdev,
* cannot be changed
*/
if (hw->phy.ops.check_reset_block(hw)) {
e_err("Cannot change link characteristics when SoL/IDER is "
"active.\n");
e_err("Cannot change link characteristics when SoL/IDER is active.\n");
return -EINVAL;
}
......@@ -727,9 +726,8 @@ static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
(test[pat] & write));
val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset);
if (val != (test[pat] & write & mask)) {
e_err("pattern test reg %04X failed: got 0x%08X "
"expected 0x%08X\n", reg + offset, val,
(test[pat] & write & mask));
e_err("pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
reg + offset, val, (test[pat] & write & mask));
*data = reg;
return 1;
}
......@@ -744,8 +742,8 @@ static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
__ew32(&adapter->hw, reg, write & mask);
val = __er32(&adapter->hw, reg);
if ((write & mask) != (val & mask)) {
e_err("set/check reg %04X test failed: got 0x%08X "
"expected 0x%08X\n", reg, (val & mask), (write & mask));
e_err("set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
reg, (val & mask), (write & mask));
*data = reg;
return 1;
}
......@@ -797,8 +795,8 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
ew32(STATUS, toggle);
after = er32(STATUS) & toggle;
if (value != after) {
e_err("failed STATUS register test got: 0x%08X expected: "
"0x%08X\n", after, value);
e_err("failed STATUS register test got: 0x%08X expected: 0x%08X\n",
after, value);
*data = 1;
return 1;
}
......@@ -1791,8 +1789,7 @@ static void e1000_get_wol(struct net_device *netdev,
wol->supported &= ~WAKE_UCAST;
if (adapter->wol & E1000_WUFC_EX)
e_err("Interface does not support directed (unicast) "
"frame wake-up packets\n");
e_err("Interface does not support directed (unicast) frame wake-up packets\n");
}
if (adapter->wol & E1000_WUFC_EX)
......
drivers/net/ethernet/intel/e1000e/ich8lan.c
View file @ 7f83560d
......@@ -2212,7 +2212,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
/* Check if the flash descriptor is valid */
if (hsfsts.hsf_status.fldesvalid == 0) {
if (!hsfsts.hsf_status.fldesvalid) {
e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
return -E1000_ERR_NVM;
}
......@@ -2232,7 +2232,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
* completed.
*/
if (hsfsts.hsf_status.flcinprog == 0) {
if (!hsfsts.hsf_status.flcinprog) {
/*
* There is no cycle running at present,
* so we can start a cycle.
......@@ -2250,7 +2250,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
*/
for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcinprog == 0) {
if (!hsfsts.hsf_status.flcinprog) {
ret_val = 0;
break;
}
......@@ -2292,12 +2292,12 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
/* wait till FDONE bit is set to 1 */
do {
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcdone == 1)
if (hsfsts.hsf_status.flcdone)
break;
udelay(1);
} while (i++ < timeout);
if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
return 0;
return -E1000_ERR_NVM;
......@@ -2408,10 +2408,10 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
* ICH_FLASH_CYCLE_REPEAT_COUNT times.
*/
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcerr == 1) {
if (hsfsts.hsf_status.flcerr) {
/* Repeat for some time before giving up. */
continue;
} else if (hsfsts.hsf_status.flcdone == 0) {
} else if (!hsfsts.hsf_status.flcdone) {
e_dbg("Timeout error - flash cycle did not complete.\n");
break;
}
......@@ -2641,7 +2641,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if ((data & 0x40) == 0) {
if (!(data & 0x40)) {
data |= 0x40;
ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
if (ret_val)
......@@ -2759,10 +2759,10 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
*/
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcerr == 1)
if (hsfsts.hsf_status.flcerr)
/* Repeat for some time before giving up. */
continue;
if (hsfsts.hsf_status.flcdone == 0) {
if (!hsfsts.hsf_status.flcdone) {
e_dbg("Timeout error - flash cycle did not complete.\n");
break;
}
......@@ -2914,10 +2914,10 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
* a few more times else Done
*/
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
if (hsfsts.hsf_status.flcerr == 1)
if (hsfsts.hsf_status.flcerr)
/* repeat for some time before giving up */
continue;
else if (hsfsts.hsf_status.flcdone == 0)
else if (!hsfsts.hsf_status.flcdone)
return ret_val;
} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
}
......@@ -3916,7 +3916,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
/* If EEPROM is not marked present, init the IGP 3 PHY manually */
if (hw->mac.type <= e1000_ich9lan) {
if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
if (!(er32(EECD) & E1000_EECD_PRES) &&
(hw->phy.type == e1000_phy_igp_3)) {
e1000e_phy_init_script_igp3(hw);
}
......
drivers/net/ethernet/intel/e1000e/mac.c
View file @ 7f83560d
......@@ -681,7 +681,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
return ret_val;
}
if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
hw->fc.requested_mode = e1000_fc_none;
else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
hw->fc.requested_mode = e1000_fc_tx_pause;
......
drivers/net/ethernet/intel/e1000e/manage.c
View file @ 7f83560d
......@@ -85,7 +85,7 @@ static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
/* Check that the host interface is enabled. */
hicr = er32(HICR);
if ((hicr & E1000_HICR_EN) == 0) {
if (!(hicr & E1000_HICR_EN)) {
e_dbg("E1000_HOST_EN bit disabled.\n");
return -E1000_ERR_HOST_INTERFACE_COMMAND;
}
......
drivers/net/ethernet/intel/e1000e/param.c
View file @ 7f83560d
......@@ -166,8 +166,8 @@ E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lea
*
* Default Value: 1 (enabled)
*/
E1000_PARAM(CrcStripping, "Enable CRC Stripping, disable if your BMC needs " \
"the CRC");
E1000_PARAM(CrcStripping,
"Enable CRC Stripping, disable if your BMC needs the CRC");
struct e1000_option {
enum { enable_option, range_option, list_option } type;
......@@ -360,8 +360,8 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
adapter->itr = 20000;
break;
case 4:
e_info("%s set to simplified (2000-8000 ints) "
"mode\n", opt.name);
e_info("%s set to simplified (2000-8000 ints) mode\n",
opt.name);
adapter->itr_setting = 4;
break;
default:
......
drivers/net/ethernet/intel/e1000e/phy.c
View file @ 7f83560d
......@@ -718,7 +718,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
* 1 - Enabled
*/
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
if (phy->disable_polarity_correction == 1)
if (phy->disable_polarity_correction)
phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
/* Enable downshift on BM (disabled by default) */
......@@ -1090,7 +1090,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
* If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if (phy->autoneg_advertised == 0)
if (!phy->autoneg_advertised)
phy->autoneg_advertised = phy->autoneg_mask;
e_dbg("Reconfiguring auto-neg advertisement params\n");
......@@ -1596,7 +1596,7 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
ret_val = e1e_rphy(hw, offset, &phy_data);
if (!ret_val)
phy->speed_downgraded = (phy_data & mask);
phy->speed_downgraded = !!(phy_data & mask);
return ret_val;
}
......@@ -1925,7 +1925,7 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
if (ret_val)
return ret_val;
phy->polarity_correction = (phy_data &
phy->polarity_correction = !!(phy_data &
M88E1000_PSCR_POLARITY_REVERSAL);
ret_val = e1000_check_polarity_m88(hw);
......@@ -1936,7 +1936,7 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
if (ret_val)
return ret_val;
phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
ret_val = e1000_get_cable_length(hw);
......@@ -1999,7 +1999,7 @@ s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
if (ret_val)
return ret_val;
phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
......@@ -2052,8 +2052,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
if (ret_val)
return ret_val;
phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
? false : true;
phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
if (phy->polarity_correction) {
ret_val = e1000_check_polarity_ife(hw);
......@@ -2070,7 +2069,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
if (ret_val)
return ret_val;
phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
/* The following parameters are undefined for 10/100 operation. */
phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
......@@ -2979,7 +2978,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
if ((hw->phy.type == e1000_phy_82578) &&
(hw->phy.revision >= 1) &&
(hw->phy.addr == 2) &&
((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) {
!(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
u16 data2 = 0x7EFF;
ret_val = e1000_access_phy_debug_regs_hv(hw,
(1 << 6) | 0x3,
......@@ -3265,7 +3264,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
if (ret_val)
return ret_val;
phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
I82577_PHY_STATUS2_SPEED_1000MBPS) {
......
drivers/net/ethernet/intel/igb/igb_main.c
View file @ 7f83560d
......@@ -60,8 +60,8 @@
#include "igb.h"
#define MAJ 3
#define MIN 2
#define BUILD 10
#define MIN 4
#define BUILD 7
#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
__stringify(BUILD) "-k"
char igb_driver_name[] = "igb";
......
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
View file @ 7f83560d
......@@ -1582,13 +1582,21 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
**/
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
*i2cctl |= IXGBE_I2C_CLK_OUT;
u32 i = 0;
u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
u32 i2cctl_r = 0;
for (i = 0; i < timeout; i++) {
*i2cctl |= IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
IXGBE_WRITE_FLUSH(hw);
/* SCL rise time (1000ns) */
udelay(IXGBE_I2C_T_RISE);
i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
if (i2cctl_r & IXGBE_I2C_CLK_IN)
break;
}
}
/**
......
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View file @ 7f83560d
......@@ -110,6 +110,7 @@
#define IXGBE_I2C_CLK_OUT 0x00000002
#define IXGBE_I2C_DATA_IN 0x00000004
#define IXGBE_I2C_DATA_OUT 0x00000008
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
/* Interrupt Registers */
#define IXGBE_EICR 0x00800
......
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