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Commit 7fa12181 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'vexpress-for-v4.6/dt-updates' of... 

Merge tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt

Few updates for ARM VExpress/Juno platforms

1. GICv3 support on Foundation models

2. Support for Juno R2 board

3. Support for ARM HDLCD on all Juno platforms

* tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: Add HDLCD support on Juno platforms
  Documentation: drm: Add DT bindings for ARM HDLCD
  arm64: dts: Add support for Juno r2 board
  arm64: dts: move juno pcie-controller to base file
  arm64: dts: add .dts for GICv3 Foundation model
  arm64: dts: split Foundation model dts to put the GIC separately
  arm64: dts: Foundation model: increase GICC region to allow EOImode=1
  arm64: dts: prepare foundation-v8.dts to cope with GICv3
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9a9f1826 9fd9288e
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Documentation/devicetree/bindings/arm/arm-boards
View file @ 7fa12181
......@@ -180,6 +180,7 @@ described under the RS1 memory mapping.
Required properties (in root node):
compatible = "arm,juno"; /* For Juno r0 board */
compatible = "arm,juno-r1"; /* For Juno r1 board */
compatible = "arm,juno-r2"; /* For Juno r2 board */
Required nodes:
The description for the board must include:
......
Documentation/devicetree/bindings/display/arm,hdlcd.txt 0 → 100644
View file @ 7fa12181
ARM HDLCD
This is a display controller found on several development platforms produced
by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
streamer that reads the data from a framebuffer and sends it to a single
digital encoder (DVI or HDMI).
Required properties:
- compatible: "arm,hdlcd"
- reg: Physical base address and length of the controller's registers.
- interrupts: One interrupt used by the display controller to notify the
interrupt controller when any of the interrupt sources programmed in
the interrupt mask register have activated.
- clocks: A list of phandle + clock-specifier pairs, one for each
entry in 'clock-names'.
- clock-names: A list of clock names. For HDLCD it should contain:
- "pxlclk" for the clock feeding the output PLL of the controller.
Required sub-nodes:
- port: The HDLCD connection to an encoder chip. The connection is modeled
using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt.
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
used for the framebuffer; if not present, the framebuffer may be located
anywhere in memory.
Example:
/ {
...
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
port {
hdlcd_output: endpoint@0 {
remote-endpoint = <&hdmi_enc_input>;
};
};
};
/* HDMI encoder on I2C bus */
i2c@7ffa0000 {
....
hdmi-transmitter@70 {
compatible = ".....";
reg = <0x70>;
port@0 {
hdmi_enc_input: endpoint {
remote-endpoint = <&hdlcd_output>;
};
hdmi_enc_output: endpoint {
remote-endpoint = <&hdmi_1_port>;
};
};
};
};
hdmi1: connector@1 {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_1_port: endpoint {
remote-endpoint = <&hdmi_enc_output>;
};
};
};
...
};
arch/arm64/boot/dts/arm/Makefile
View file @ 7fa12181
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
......
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts 0 → 100644
View file @ 7fa12181
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv3 configuration)
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x200000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <1 9 4>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
};
arch/arm64/boot/dts/arm/foundation-v8.dts
View file @ 7fa12181
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS
* ARMv8 Foundation model DTS (GICv2 configuration)
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00010000;
#include "foundation-v8.dtsi"
/ {
model = "Foundation-v8A";
compatible = "arm,foundation-aarch64", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
#address-cells = <2>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x1000>,
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
smb {
compatible = "arm,vexpress,v2m-p1", "simple-bus";
arm,v2m-memory-map = "rs1";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
iofpga@3,00000000 {
compatible = "arm,amba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
virtio_block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
};
};
};
};
arch/arm64/boot/dts/arm/foundation-v8.dtsi 0 → 100644
View file @ 7fa12181
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00010000;
/ {
model = "Foundation-v8A";
compatible = "arm,foundation-aarch64", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
smb {
compatible = "arm,vexpress,v2m-p1", "simple-bus";
arm,v2m-memory-map = "rs1";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
<0 0 1 &gic 0 0 0 1 4>,
<0 0 2 &gic 0 0 0 2 4>,
<0 0 3 &gic 0 0 0 3 4>,
<0 0 4 &gic 0 0 0 4 4>,
<0 0 5 &gic 0 0 0 5 4>,
<0 0 6 &gic 0 0 0 6 4>,
<0 0 7 &gic 0 0 0 7 4>,
<0 0 8 &gic 0 0 0 8 4>,
<0 0 9 &gic 0 0 0 9 4>,
<0 0 10 &gic 0 0 0 10 4>,
<0 0 11 &gic 0 0 0 11 4>,
<0 0 12 &gic 0 0 0 12 4>,
<0 0 13 &gic 0 0 0 13 4>,
<0 0 14 &gic 0 0 0 14 4>,
<0 0 15 &gic 0 0 0 15 4>,
<0 0 16 &gic 0 0 0 16 4>,
<0 0 17 &gic 0 0 0 17 4>,
<0 0 18 &gic 0 0 0 18 4>,
<0 0 19 &gic 0 0 0 19 4>,
<0 0 20 &gic 0 0 0 20 4>,
<0 0 21 &gic 0 0 0 21 4>,
<0 0 22 &gic 0 0 0 22 4>,
<0 0 23 &gic 0 0 0 23 4>,
<0 0 24 &gic 0 0 0 24 4>,
<0 0 25 &gic 0 0 0 25 4>,
<0 0 26 &gic 0 0 0 26 4>,
<0 0 27 &gic 0 0 0 27 4>,
<0 0 28 &gic 0 0 0 28 4>,
<0 0 29 &gic 0 0 0 29 4>,
<0 0 30 &gic 0 0 0 30 4>,
<0 0 31 &gic 0 0 0 31 4>,
<0 0 32 &gic 0 0 0 32 4>,
<0 0 33 &gic 0 0 0 33 4>,
<0 0 34 &gic 0 0 0 34 4>,
<0 0 35 &gic 0 0 0 35 4>,
<0 0 36 &gic 0 0 0 36 4>,
<0 0 37 &gic 0 0 0 37 4>,
<0 0 38 &gic 0 0 0 38 4>,
<0 0 39 &gic 0 0 0 39 4>,
<0 0 40 &gic 0 0 0 40 4>,
<0 0 41 &gic 0 0 0 41 4>,
<0 0 42 &gic 0 0 0 42 4>;
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
iofpga@3,00000000 {
compatible = "arm,amba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
virtio_block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
};
};
};
};
arch/arm64/boot/dts/arm/juno-base.dtsi
View file @ 7fa12181
......@@ -75,6 +75,28 @@ cpu_scp_hpri: scp-shmem@200 {
};
};
pcie_ctlr: pcie-controller@40000000 {
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
device_type = "pci";
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
bus-range = <0 255>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
<0 0 0 2 &gic 0 0 0 137 4>,
<0 0 0 3 &gic 0 0 0 138 4>,
<0 0 0 4 &gic 0 0 0 139 4>;
msi-parent = <&v2m_0>;
status = "disabled";
};
scpi {
compatible = "arm,scpi";
mboxes = <&mailbox 1>;
......@@ -92,8 +114,8 @@ scpi_dvfs: scpi_clocks@0 {
scpi_clk: scpi_clocks@3 {
compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>;
clock-indices = <3>, <4>;
clock-output-names = "pxlclk0", "pxlclk1";
clock-indices = <3>;
clock-output-names = "pxlclk";
};
};
......@@ -124,6 +146,34 @@ dma@7ff00000 {
clock-names = "apb_pclk";
};
hdlcd@7ff50000 {
compatible = "arm,hdlcd";
reg = <0 0x7ff50000 0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
port {
hdlcd1_output: endpoint@0 {
remote-endpoint = <&tda998x_1_input>;
};
};
};
hdlcd@7ff60000 {
compatible = "arm,hdlcd";
reg = <0 0x7ff60000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
port {
hdlcd0_output: endpoint@0 {
remote-endpoint = <&tda998x_0_input>;
};
};
};
soc_uart0: uart@7ff80000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x7ff80000 0x0 0x1000>;
......@@ -142,14 +192,24 @@ i2c@7ffa0000 {
i2c-sda-hold-time-ns = <500>;
clocks = <&soc_smc50mhz>;
dvi0: dvi-transmitter@70 {
hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
port {
tda998x_0_input: endpoint@0 {
remote-endpoint = <&hdlcd0_output>;
};
};
};
dvi1: dvi-transmitter@71 {
hdmi-transmitter@71 {
compatible = "nxp,tda998x";
reg = <0x71>;
port {
tda998x_1_input: endpoint@0 {
remote-endpoint = <&hdlcd1_output>;
};
};
};
};
......
arch/arm64/boot/dts/arm/juno-r1.dts
View file @ 7fa12181
......@@ -172,29 +172,12 @@ pmu_a53 {
};
#include "juno-base.dtsi"
pcie-controller@40000000 {
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
device_type = "pci";
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
bus-range = <0 255>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
<0 0 0 2 &gic 0 0 0 137 4>,
<0 0 0 3 &gic 0 0 0 138 4>,
<0 0 0 4 &gic 0 0 0 139 4>;
msi-parent = <&v2m_0>;
};
};
&memtimer {
status = "okay";
};
&pcie_ctlr {
status = "okay";
};
arch/arm64/boot/dts/arm/juno-r2.dts 0 → 100644
View file @ 7fa12181
/*
* ARM Ltd. Juno Platform
*
* Copyright (c) 2015 ARM Ltd.
*
* This file is licensed under a dual GPLv2 or BSD license.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "ARM Juno development board (r2)";
compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &soc_uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&A72_0>;
};
core1 {
cpu = <&A72_1>;
};
};
cluster1 {
core0 {
cpu = <&A53_0>;
};
core1 {
cpu = <&A53_1>;
};
core2 {
cpu = <&A53_2>;
};
core3 {
cpu = <&A53_3>;
};
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
A72_0: cpu@0 {
compatible = "arm,cortex-a72","arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A72_1: cpu@1 {
compatible = "arm,cortex-a72","arm,armv8";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A72_L2: l2-cache0 {
compatible = "cache";
};
A53_L2: l2-cache1 {
compatible = "cache";
};
};
pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A72_0>,
<&A72_1>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A53_0>,
<&A53_1>,
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&memtimer {
status = "okay";
};
&pcie_ctlr {
status = "okay";
};
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