Commit 80f47f82 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

wifi: rtw89: rfk: send channel information to firmware for RF calibrations

We are going to do RF calibrations in firmware, so driver needs to provide
channel information for calibrations, which can do the same things as
they did in driver.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20240202030642.108385-3-pkshih@realtek.com
parent ad1c86e9
...@@ -4282,15 +4282,18 @@ struct rtw89_dack_info { ...@@ -4282,15 +4282,18 @@ struct rtw89_dack_info {
bool msbk_timeout[RTW89_DACK_PATH_NR]; bool msbk_timeout[RTW89_DACK_PATH_NR];
}; };
#define RTW89_IQK_CHS_NR 2 #define RTW89_RFK_CHS_NR 3
#define RTW89_IQK_PATH_NR 4
struct rtw89_rfk_mcc_info { struct rtw89_rfk_mcc_info {
u8 ch[RTW89_IQK_CHS_NR]; u8 ch[RTW89_RFK_CHS_NR];
u8 band[RTW89_IQK_CHS_NR]; u8 band[RTW89_RFK_CHS_NR];
u8 bw[RTW89_RFK_CHS_NR];
u8 table_idx; u8 table_idx;
}; };
#define RTW89_IQK_CHS_NR 2
#define RTW89_IQK_PATH_NR 4
struct rtw89_lck_info { struct rtw89_lck_info {
u8 thermal[RF_PATH_MAX]; u8 thermal[RF_PATH_MAX];
}; };
......
...@@ -4520,6 +4520,79 @@ int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev) ...@@ -4520,6 +4520,79 @@ int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev)
} }
EXPORT_SYMBOL(rtw89_fw_h2c_rf_ntfy_mcc); EXPORT_SYMBOL(rtw89_fw_h2c_rf_ntfy_mcc);
int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
struct rtw89_fw_h2c_rfk_pre_info *h2c;
u8 tbl_sel = rfk_mcc->table_idx;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
u8 tbl, path;
u32 val32;
int ret;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "failed to alloc skb for h2c rfk_pre_ntfy\n");
return -ENOMEM;
}
skb_put(skb, len);
h2c = (struct rtw89_fw_h2c_rfk_pre_info *)skb->data;
h2c->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
BUILD_BUG_ON(NUM_OF_RTW89_FW_RFK_TBL > RTW89_RFK_CHS_NR);
for (tbl = 0; tbl < NUM_OF_RTW89_FW_RFK_TBL; tbl++) {
for (path = 0; path < NUM_OF_RTW89_FW_RFK_PATH; path++) {
h2c->dbcc.ch[path][tbl] = cpu_to_le32(rfk_mcc->ch[tbl]);
h2c->dbcc.band[path][tbl] = cpu_to_le32(rfk_mcc->band[tbl]);
}
}
for (path = 0; path < NUM_OF_RTW89_FW_RFK_PATH; path++) {
h2c->tbl.cur_ch[path] = cpu_to_le32(rfk_mcc->ch[tbl_sel]);
h2c->tbl.cur_band[path] = cpu_to_le32(rfk_mcc->band[tbl_sel]);
}
h2c->phy_idx = cpu_to_le32(phy_idx);
h2c->cur_band = cpu_to_le32(rfk_mcc->band[tbl_sel]);
h2c->cur_bw = cpu_to_le32(rfk_mcc->bw[tbl_sel]);
h2c->cur_center_ch = cpu_to_le32(rfk_mcc->ch[tbl_sel]);
val32 = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_IQC_V1);
h2c->ktbl_sel0 = cpu_to_le32(val32);
val32 = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_IQC_V1);
h2c->ktbl_sel1 = cpu_to_le32(val32);
val32 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
h2c->rfmod0 = cpu_to_le32(val32);
val32 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_CFGCH, RFREG_MASK);
h2c->rfmod1 = cpu_to_le32(val32);
if (rtw89_is_mlo_1_1(rtwdev))
h2c->mlo_1_1 = cpu_to_le32(1);
h2c->rfe_type = cpu_to_le32(rtwdev->efuse.rfe_type);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK,
H2C_FUNC_RFK_PRE_NOTIFY, 0, 0,
len);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {
rtw89_err(rtwdev, "failed to send h2c\n");
goto fail;
}
return 0;
fail:
dev_kfree_skb_any(skb);
return ret;
}
int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
bool rack, bool dack) bool rack, bool dack)
......
...@@ -3932,6 +3932,11 @@ enum rtw89_mcc_h2c_func { ...@@ -3932,6 +3932,11 @@ enum rtw89_mcc_h2c_func {
#define H2C_CL_OUTSRC_RF_REG_B 0x9 #define H2C_CL_OUTSRC_RF_REG_B 0x9
#define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
#define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
#define H2C_CL_OUTSRC_RF_FW_RFK 0xb
enum rtw89_rfk_offload_h2c_func {
H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
};
struct rtw89_fw_h2c_rf_get_mccch { struct rtw89_fw_h2c_rf_get_mccch {
__le32 ch_0; __le32 ch_0;
...@@ -3942,6 +3947,41 @@ struct rtw89_fw_h2c_rf_get_mccch { ...@@ -3942,6 +3947,41 @@ struct rtw89_fw_h2c_rf_get_mccch {
__le32 current_band_type; __le32 current_band_type;
} __packed; } __packed;
#define NUM_OF_RTW89_FW_RFK_PATH 2
#define NUM_OF_RTW89_FW_RFK_TBL 3
struct rtw89_fw_h2c_rfk_pre_info {
struct {
__le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
__le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
} __packed dbcc;
__le32 mlo_mode;
struct {
__le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
__le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
} __packed tbl;
__le32 phy_idx;
__le32 cur_band;
__le32 cur_bw;
__le32 cur_center_ch;
__le32 ktbl_sel0;
__le32 ktbl_sel1;
__le32 rfmod0;
__le32 rfmod1;
__le32 mlo_1_1;
__le32 rfe_type;
__le32 drv_mode;
struct {
__le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
__le32 band[NUM_OF_RTW89_FW_RFK_PATH];
} __packed mlo;
} __packed;
enum rtw89_rf_log_type { enum rtw89_rf_log_type {
RTW89_RF_RUN_LOG = 0, RTW89_RF_RUN_LOG = 0,
RTW89_RF_RPT_LOG = 1, RTW89_RF_RPT_LOG = 1,
...@@ -4127,6 +4167,8 @@ int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, ...@@ -4127,6 +4167,8 @@ int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
struct rtw89_fw_h2c_rf_reg_info *info, struct rtw89_fw_h2c_rf_reg_info *info,
u16 len, u8 page); u16 len, u8 page);
int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx);
int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
bool rack, bool dack); bool rack, bool dack);
......
...@@ -8730,7 +8730,9 @@ ...@@ -8730,7 +8730,9 @@
#define B_PRT_COM_RXBB_V1 GENMASK(4, 0) #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
#define B_PRT_COM_DONE BIT(0) #define B_PRT_COM_DONE BIT(0)
#define R_COEF_SEL 0x8104 #define R_COEF_SEL 0x8104
#define R_COEF_SEL_C1 0x8204
#define B_COEF_SEL_IQC BIT(0) #define B_COEF_SEL_IQC BIT(0)
#define B_COEF_SEL_IQC_V1 GENMASK(1, 0)
#define B_COEF_SEL_MDPD BIT(8) #define B_COEF_SEL_MDPD BIT(8)
#define R_CFIR_SYS 0x8120 #define R_CFIR_SYS 0x8120
#define R_IQK_RES 0x8124 #define R_IQK_RES 0x8124
......
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