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Commit 821e3a48 authored by Dave Jiang's avatar Dave Jiang Committed by Russell King
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[ARM PATCH] 2355/1: cleanup of PCI defines for IOP33x platforms 

Patch from Dave Jiang

Signed-off-by: Dave Jiang

Major cleanup of the IOP33x family platform PCI defines. Hopefully should be more coherent and removed some magic numbers. Also should be finalized with the latest redboot ATU config.
Signed-off-by: Russell King
parent 9c0c7e70
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Showing with 63 additions and 68 deletions
arch/arm/mach-iop3xx/iop331-pci.c
View file @ 821e3a48
......@@ -4,7 +4,7 @@
* PCI support for the Intel IOP331 chipset
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2003 Intel Corp.
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -26,7 +26,8 @@
#include <asm/arch/iop331.h>
//#define DEBUG
#undef DEBUG
#undef DEBUG1
#ifdef DEBUG
#define DBG(x...) printk(x)
......@@ -34,6 +35,12 @@
#define DBG(x...) do { } while (0)
#endif
#ifdef DEBUG1
#define DBG1(x...) printk(x)
#else
#define DBG1(x...) do { } while (0)
#endif
/*
* This routine builds either a type0 or type1 configuration command. If the
* bus is on the 80331 then a type0 made, else a type1 is created.
......@@ -197,21 +204,19 @@ struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys)
void iop331_init(void)
{
DBG("PCI: Intel 80331 PCI init code.\n");
DBG("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
DBG("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
DBG1("PCI: Intel 80331 PCI init code.\n");
DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
*IOP331_OMWTVR0,
*IOP331_OIOWTVR);
DBG("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
DBG("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
DBG("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
DBG("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
DBG("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
/* redboot changed, reset IABAR0 to something sane */
/* fixes master aborts in plugged in cards */
/* will clean up later and work nicely with redboot */
*IOP331_IABAR0 = 0x00000004;
DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1);
DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1);
DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");
}
arch/arm/mach-iop3xx/iq80331-pci.c
View file @ 821e3a48
......@@ -4,7 +4,7 @@
* PCI support for the Intel IQ80331 reference board
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2003 Intel Corp.
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -68,44 +68,28 @@ static int iq80331_setup(int nr, struct pci_sys_data *sys)
memset(res, 0, sizeof(struct resource) * 2);
res[0].start = IQ80331_PCI_IO_BASE + 0x6e000000;
res[0].end = IQ80331_PCI_IO_BASE + IQ80331_PCI_IO_SIZE - 1 + IQ80331_PCI_IO_OFFSET;
res[0].start = IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].end = IOP331_PCI_UPPER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].name = "IQ80331 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IQ80331_PCI_MEM_BASE;
res[1].end = IQ80331_PCI_MEM_BASE + IQ80331_PCI_MEM_SIZE;
res[1].start = IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].end = IOP331_PCI_UPPER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].name = "IQ80331 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
/*
* Since the IQ80331 is a slave card on a PCI backplane,
* it uses BAR1 to reserve a portion of PCI memory space for
* use with the private devices on the secondary bus
* (GigE and PCI-X slot). We read BAR1 and configure
* our outbound translation windows to target that
* address range and assign all devices in that
* address range. W/O this, certain BIOSes will fail
* to boot as the IQ80331 claims addresses that are
* in use by other devices.
*
* Note that the same cannot be done with I/O space,
* so hopefully the host will stick to the lower 64K for
* PCI I/O and leave us alone.
*/
sys->mem_offset = IQ80331_PCI_MEM_BASE -
(*IOP331_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
sys->mem_offset = IOP331_PCI_MEM_OFFSET;
sys->io_offset = IOP331_PCI_IO_OFFSET;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
sys->io_offset = IQ80331_PCI_IO_OFFSET;
iop3xx_pcibios_min_io = IQ80331_PCI_IO_BASE;
iop3xx_pcibios_min_mem = IQ80331_PCI_MEM_BASE;
iop3xx_pcibios_min_io = IOP331_PCI_LOWER_IO_VA;
iop3xx_pcibios_min_mem = IOP331_PCI_LOWER_MEM_VA;
return 1;
}
......
include/asm-arm/arch-iop3xx/iop331.h
View file @ 821e3a48
......@@ -4,7 +4,7 @@
* Intel IOP331 Chip definitions
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2003 Intel Corp.
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -21,7 +21,8 @@
*/
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_IOP331
#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090)
/*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */
#define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010)
#else
#define iop_is_331() 0
#endif
......@@ -30,20 +31,28 @@
/*
* IOP331 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP331_PCI_LOWER_IO 0x90000000
#define IOP331_PCI_UPPER_IO 0x900fffff
#define IOP331_PCI_LOWER_MEM 0x80000000
#define IOP331_PCI_UPPER_MEM 0x87ffffff
#define IOP331_PCI_WINDOW_SIZE 128 * 0x100000
#define IOP331_PCI_IO_WINDOW_SIZE 0x10000
#define IOP331_PCI_LOWER_IO_PA 0x90000000
#define IOP331_PCI_LOWER_IO_VA 0xfe000000
#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
#define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1)
#define IOP331_PCI_LOWER_MEM_PA 0x80000000
#define IOP331_PCI_LOWER_MEM_VA 0x80000000
#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_MEM_VA (IOP331_PCI_LOWER_MEM_VA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_VA - IOP331_PCI_LOWER_MEM_BA)
/*
* IOP331 chipset registers
*/
#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
// #define IOP331_VIRT_MEM_BASE 0xfff00000 /* chip virtual mem address*/
#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
......@@ -248,8 +257,14 @@
#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
#define IOP331_TICK_RATE 266000000 /* 266 MHz clock */
#if defined(CONFIG_ARCH_IOP331)
#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
#endif
#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
#undef IOP331_TICK_RATE
#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
#endif
/* Application accelerator unit 0x00000800 - 0x000008FF */
#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
......@@ -324,6 +339,11 @@
/* 0x00001740 through 0x0000176C UART 1 */
#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
/* Reserved 0x00001770 through 0x0000177F */
/* General Purpose I/O Registers */
......@@ -333,6 +353,7 @@
/* Reserved 0x0000178c through 0x000019ff */
#ifndef __ASSEMBLY__
extern void iop331_map_io(void);
extern void iop331_init_irq(void);
......
include/asm-arm/arch-iop3xx/iq80331.h
View file @ 821e3a48
......@@ -7,30 +7,15 @@
#ifndef _IQ80331_H_
#define _IQ80331_H_
#define IQ80331_RAMBASE 0x00000000
#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
#define IQ80331_FLASHSIZE 0x00800000
#define IQ80331_FLASHWIDTH 1
#define IQ80331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
#define IQ80331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
#define IQ80331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
#define IQ80331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
/*
* IQ80331 PCI I/O and Mem space regions
*/
#define IQ80331_PCI_IO_BASE 0x90000000
#define IQ80331_PCI_IO_SIZE 0x00010000
#define IQ80331_PCI_MEM_BASE 0x80000000
#define IQ80331_PCI_MEM_SIZE 0x08000000
#define IQ80331_PCI_IO_OFFSET 0x6e000000
#ifndef __ASSEMBLY__
extern void iq80331_map_io(void);
#endif
......
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