Commit 83a5a2d7 authored by Yan-Hsuan Chuang's avatar Yan-Hsuan Chuang Committed by Kalle Valo

rtw88: pci: use macros to access PCI DBI/MDIO registers

Add some register and bit macros to access DBI/MDIO register. This
should not change the logic.
Signed-off-by: default avatarYan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent df0af4c7
...@@ -1060,14 +1060,15 @@ static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev, ...@@ -1060,14 +1060,15 @@ static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev,
static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data) static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data)
{ {
u16 write_addr; u16 write_addr;
u16 remainder = addr & 0x3; u16 remainder = addr & ~(BITS_DBI_WREN | BITS_DBI_ADDR_MASK);
u8 flag; u8 flag;
u8 cnt = 20; u8 cnt = RTW_PCI_WR_RETRY_CNT;
write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); write_addr = addr & BITS_DBI_ADDR_MASK;
write_addr |= u16_encode_bits(BIT(remainder), BITS_DBI_WREN);
rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data); rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data);
rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr); rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr);
rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, 0x01); rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16);
flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2);
while (flag && (cnt != 0)) { while (flag && (cnt != 0)) {
...@@ -1083,19 +1084,17 @@ static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1) ...@@ -1083,19 +1084,17 @@ static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1)
{ {
u8 page; u8 page;
u8 wflag; u8 wflag;
u8 cnt; u8 cnt = RTW_PCI_WR_RETRY_CNT;
rtw_write16(rtwdev, REG_MDIO_V1, data); rtw_write16(rtwdev, REG_MDIO_V1, data);
page = addr < 0x20 ? 0 : 1; page = addr < RTW_PCI_MDIO_PG_SZ ? 0 : 1;
page += g1 ? 0 : 2; page += g1 ? RTW_PCI_MDIO_PG_OFFS_G1 : RTW_PCI_MDIO_PG_OFFS_G2;
rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & 0x1f); rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK);
rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page); rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page);
rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1);
wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
cnt = 20; wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
while (wflag && (cnt != 0)) { while (wflag && (cnt != 0)) {
udelay(10); udelay(10);
wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG,
......
...@@ -21,9 +21,19 @@ ...@@ -21,9 +21,19 @@
#define BIT_RX_TAG_EN BIT(15) #define BIT_RX_TAG_EN BIT(15)
#define REG_DBI_WDATA_V1 0x03E8 #define REG_DBI_WDATA_V1 0x03E8
#define REG_DBI_FLAG_V1 0x03F0 #define REG_DBI_FLAG_V1 0x03F0
#define BIT_DBI_RFLAG BIT(17)
#define BIT_DBI_WFLAG BIT(16)
#define BITS_DBI_WREN GENMASK(15, 12)
#define BITS_DBI_ADDR_MASK GENMASK(11, 2)
#define REG_MDIO_V1 0x03F4 #define REG_MDIO_V1 0x03F4
#define REG_PCIE_MIX_CFG 0x03F8 #define REG_PCIE_MIX_CFG 0x03F8
#define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
#define BIT_MDIO_WFLAG_V1 BIT(5) #define BIT_MDIO_WFLAG_V1 BIT(5)
#define RTW_PCI_MDIO_PG_SZ BIT(5)
#define RTW_PCI_MDIO_PG_OFFS_G1 0
#define RTW_PCI_MDIO_PG_OFFS_G2 2
#define RTW_PCI_WR_RETRY_CNT 20
#define BIT_PCI_BCNQ_FLAG BIT(4) #define BIT_PCI_BCNQ_FLAG BIT(4)
#define RTK_PCI_TXBD_DESA_BCNQ 0x308 #define RTK_PCI_TXBD_DESA_BCNQ 0x308
......
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