Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kirill Smelkov
linux
Commits
845f2725
Commit
845f2725
authored
Nov 08, 2015
by
Ben Skeggs
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/nouveau/nvif: split out ctxdma interface definitions
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
75445a4d
Changes
12
Show whitespace changes
Inline
Side-by-side
Showing
12 changed files
with
79 additions
and
75 deletions
+79
-75
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
+66
-0
drivers/gpu/drm/nouveau/include/nvif/class.h
drivers/gpu/drm/nouveau/include/nvif/class.h
+3
-71
drivers/gpu/drm/nouveau/nouveau_abi16.c
drivers/gpu/drm/nouveau/nouveau_abi16.c
+1
-0
drivers/gpu/drm/nouveau/nouveau_chan.c
drivers/gpu/drm/nouveau/nouveau_chan.c
+1
-0
drivers/gpu/drm/nouveau/nouveau_drm.c
drivers/gpu/drm/nouveau/nouveau_drm.c
+1
-0
drivers/gpu/drm/nouveau/nv17_fence.c
drivers/gpu/drm/nouveau/nv17_fence.c
+1
-0
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nv50_display.c
+1
-0
drivers/gpu/drm/nouveau/nv50_fence.c
drivers/gpu/drm/nouveau/nv50_fence.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c
drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c
drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c
drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c
+1
-1
No files found.
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
0 → 100644
View file @
845f2725
#ifndef __NVIF_CL0002_H__
#define __NVIF_CL0002_H__
struct
nv_dma_v0
{
__u8
version
;
#define NV_DMA_V0_TARGET_VM 0x00
#define NV_DMA_V0_TARGET_VRAM 0x01
#define NV_DMA_V0_TARGET_PCI 0x02
#define NV_DMA_V0_TARGET_PCI_US 0x03
#define NV_DMA_V0_TARGET_AGP 0x04
__u8
target
;
#define NV_DMA_V0_ACCESS_VM 0x00
#define NV_DMA_V0_ACCESS_RD 0x01
#define NV_DMA_V0_ACCESS_WR 0x02
#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
__u8
access
;
__u8
pad03
[
5
];
__u64
start
;
__u64
limit
;
/* ... chipset-specific class data */
};
struct
nv50_dma_v0
{
__u8
version
;
#define NV50_DMA_V0_PRIV_VM 0x00
#define NV50_DMA_V0_PRIV_US 0x01
#define NV50_DMA_V0_PRIV__S 0x02
__u8
priv
;
#define NV50_DMA_V0_PART_VM 0x00
#define NV50_DMA_V0_PART_256 0x01
#define NV50_DMA_V0_PART_1KB 0x02
__u8
part
;
#define NV50_DMA_V0_COMP_NONE 0x00
#define NV50_DMA_V0_COMP_1 0x01
#define NV50_DMA_V0_COMP_2 0x02
#define NV50_DMA_V0_COMP_VM 0x03
__u8
comp
;
#define NV50_DMA_V0_KIND_PITCH 0x00
#define NV50_DMA_V0_KIND_VM 0x7f
__u8
kind
;
__u8
pad05
[
3
];
};
struct
gf100_dma_v0
{
__u8
version
;
#define GF100_DMA_V0_PRIV_VM 0x00
#define GF100_DMA_V0_PRIV_US 0x01
#define GF100_DMA_V0_PRIV__S 0x02
__u8
priv
;
#define GF100_DMA_V0_KIND_PITCH 0x00
#define GF100_DMA_V0_KIND_VM 0xff
__u8
kind
;
__u8
pad03
[
5
];
};
struct
gf119_dma_v0
{
__u8
version
;
#define GF119_DMA_V0_PAGE_LP 0x00
#define GF119_DMA_V0_PAGE_SP 0x01
__u8
page
;
#define GF119_DMA_V0_KIND_PITCH 0x00
#define GF119_DMA_V0_KIND_VM 0xff
__u8
kind
;
__u8
pad03
[
5
];
};
#endif
drivers/gpu/drm/nouveau/include/nvif/class.h
View file @
845f2725
...
@@ -13,9 +13,9 @@
...
@@ -13,9 +13,9 @@
/* the below match nvidia-assigned (either in hw, or sw) class numbers */
/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_DEVICE 0x00000080
#define NV_DEVICE 0x00000080
#define NV_DMA_FROM_MEMORY
0x00000002
#define NV_DMA_FROM_MEMORY
/* cl0002.h */
0x00000002
#define NV_DMA_TO_MEMORY
0x00000003
#define NV_DMA_TO_MEMORY
/* cl0002.h */
0x00000003
#define NV_DMA_IN_MEMORY
0x0000003d
#define NV_DMA_IN_MEMORY
/* cl0002.h */
0x0000003d
#define FERMI_TWOD_A 0x0000902d
#define FERMI_TWOD_A 0x0000902d
...
@@ -198,72 +198,4 @@ struct nv_device_time_v0 {
...
@@ -198,72 +198,4 @@ struct nv_device_time_v0 {
__u8
pad01
[
7
];
__u8
pad01
[
7
];
__u64
time
;
__u64
time
;
};
};
/*******************************************************************************
* context dma
******************************************************************************/
struct
nv_dma_v0
{
__u8
version
;
#define NV_DMA_V0_TARGET_VM 0x00
#define NV_DMA_V0_TARGET_VRAM 0x01
#define NV_DMA_V0_TARGET_PCI 0x02
#define NV_DMA_V0_TARGET_PCI_US 0x03
#define NV_DMA_V0_TARGET_AGP 0x04
__u8
target
;
#define NV_DMA_V0_ACCESS_VM 0x00
#define NV_DMA_V0_ACCESS_RD 0x01
#define NV_DMA_V0_ACCESS_WR 0x02
#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
__u8
access
;
__u8
pad03
[
5
];
__u64
start
;
__u64
limit
;
/* ... chipset-specific class data */
};
struct
nv50_dma_v0
{
__u8
version
;
#define NV50_DMA_V0_PRIV_VM 0x00
#define NV50_DMA_V0_PRIV_US 0x01
#define NV50_DMA_V0_PRIV__S 0x02
__u8
priv
;
#define NV50_DMA_V0_PART_VM 0x00
#define NV50_DMA_V0_PART_256 0x01
#define NV50_DMA_V0_PART_1KB 0x02
__u8
part
;
#define NV50_DMA_V0_COMP_NONE 0x00
#define NV50_DMA_V0_COMP_1 0x01
#define NV50_DMA_V0_COMP_2 0x02
#define NV50_DMA_V0_COMP_VM 0x03
__u8
comp
;
#define NV50_DMA_V0_KIND_PITCH 0x00
#define NV50_DMA_V0_KIND_VM 0x7f
__u8
kind
;
__u8
pad05
[
3
];
};
struct
gf100_dma_v0
{
__u8
version
;
#define GF100_DMA_V0_PRIV_VM 0x00
#define GF100_DMA_V0_PRIV_US 0x01
#define GF100_DMA_V0_PRIV__S 0x02
__u8
priv
;
#define GF100_DMA_V0_KIND_PITCH 0x00
#define GF100_DMA_V0_KIND_VM 0xff
__u8
kind
;
__u8
pad03
[
5
];
};
struct
gf119_dma_v0
{
__u8
version
;
#define GF119_DMA_V0_PAGE_LP 0x00
#define GF119_DMA_V0_PAGE_SP 0x01
__u8
page
;
#define GF119_DMA_V0_KIND_PITCH 0x00
#define GF119_DMA_V0_KIND_VM 0xff
__u8
kind
;
__u8
pad03
[
5
];
};
#endif
#endif
drivers/gpu/drm/nouveau/nouveau_abi16.c
View file @
845f2725
...
@@ -25,6 +25,7 @@
...
@@ -25,6 +25,7 @@
#include <nvif/driver.h>
#include <nvif/driver.h>
#include <nvif/ioctl.h>
#include <nvif/ioctl.h>
#include <nvif/class.h>
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvif/cla06f.h>
#include <nvif/cla06f.h>
#include <nvif/unpack.h>
#include <nvif/unpack.h>
...
...
drivers/gpu/drm/nouveau/nouveau_chan.c
View file @
845f2725
...
@@ -24,6 +24,7 @@
...
@@ -24,6 +24,7 @@
#include <nvif/os.h>
#include <nvif/os.h>
#include <nvif/class.h>
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvif/cl006b.h>
#include <nvif/cl006b.h>
#include <nvif/cl506f.h>
#include <nvif/cl506f.h>
#include <nvif/cl906f.h>
#include <nvif/cl906f.h>
...
...
drivers/gpu/drm/nouveau/nouveau_drm.c
View file @
845f2725
...
@@ -37,6 +37,7 @@
...
@@ -37,6 +37,7 @@
#include <core/pci.h>
#include <core/pci.h>
#include <core/tegra.h>
#include <core/tegra.h>
#include <nvif/cl0002.h>
#include <nvif/cla06f.h>
#include <nvif/cla06f.h>
#include <nvif/if0004.h>
#include <nvif/if0004.h>
...
...
drivers/gpu/drm/nouveau/nv17_fence.c
View file @
845f2725
...
@@ -24,6 +24,7 @@
...
@@ -24,6 +24,7 @@
#include <nvif/os.h>
#include <nvif/os.h>
#include <nvif/class.h>
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include "nouveau_drm.h"
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_dma.h"
...
...
drivers/gpu/drm/nouveau/nv50_display.c
View file @
845f2725
...
@@ -31,6 +31,7 @@
...
@@ -31,6 +31,7 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_fb_helper.h>
#include <nvif/class.h>
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvif/cl5070.h>
#include <nvif/cl5070.h>
#include <nvif/cl507a.h>
#include <nvif/cl507a.h>
#include <nvif/cl507b.h>
#include <nvif/cl507b.h>
...
...
drivers/gpu/drm/nouveau/nv50_fence.c
View file @
845f2725
...
@@ -24,6 +24,7 @@
...
@@ -24,6 +24,7 @@
#include <nvif/os.h>
#include <nvif/os.h>
#include <nvif/class.h>
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include "nouveau_drm.h"
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_dma.h"
...
...
drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c
View file @
845f2725
...
@@ -28,7 +28,7 @@
...
@@ -28,7 +28,7 @@
#include <subdev/fb.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/instmem.h>
#include <nvif/cl
ass
.h>
#include <nvif/cl
0002
.h>
#include <nvif/unpack.h>
#include <nvif/unpack.h>
static
int
static
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c
View file @
845f2725
...
@@ -28,7 +28,7 @@
...
@@ -28,7 +28,7 @@
#include <core/gpuobj.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/fb.h>
#include <nvif/cl
ass
.h>
#include <nvif/cl
0002
.h>
#include <nvif/unpack.h>
#include <nvif/unpack.h>
struct
gf100_dmaobj
{
struct
gf100_dmaobj
{
...
...
drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c
View file @
845f2725
...
@@ -28,7 +28,7 @@
...
@@ -28,7 +28,7 @@
#include <core/gpuobj.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/fb.h>
#include <nvif/cl
ass
.h>
#include <nvif/cl
0002
.h>
#include <nvif/unpack.h>
#include <nvif/unpack.h>
struct
gf119_dmaobj
{
struct
gf119_dmaobj
{
...
...
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c
View file @
845f2725
...
@@ -28,7 +28,7 @@
...
@@ -28,7 +28,7 @@
#include <core/gpuobj.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/fb.h>
#include <nvif/cl
ass
.h>
#include <nvif/cl
0002
.h>
#include <nvif/unpack.h>
#include <nvif/unpack.h>
struct
nv50_dmaobj
{
struct
nv50_dmaobj
{
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment