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Commit 848ebfd7 authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu: add BIF 5.0 register headers 

These are register headers for the BIF (Bus InterFace) block on
the GPU.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 054e4c60
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drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h 0 → 100644
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/*
* BIF_5_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BIF_5_0_D_H
#define BIF_5_0_D_H
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
#define mmBIF_MM_INDACCESS_CNTL 0x1500
#define mmBIF_DOORBELL_APER_EN 0x1501
#define mmBUS_CNTL 0x1508
#define mmCONFIG_CNTL 0x1509
#define mmCONFIG_MEMSIZE 0x150a
#define mmCONFIG_RESERVED 0x1502
#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
#define mmCONFIG_F0_BASE 0x150b
#define mmCONFIG_APER_SIZE 0x150c
#define mmCONFIG_REG_APER_SIZE 0x150d
#define mmBIF_SCRATCH0 0x150e
#define mmBIF_SCRATCH1 0x150f
#define mmBIF_RLC_INTR_CNTL 0x1510
#define mmBIF_BME_STATUS 0x1511
#define mmBIF_ATOMIC_ERR_LOG 0x1512
#define mmBX_RESET_EN 0x1514
#define mmMM_CFGREGS_CNTL 0x1513
#define mmHW_DEBUG 0x1515
#define mmMASTER_CREDIT_CNTL 0x1516
#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
#define mmBX_RESET_CNTL 0x1518
#define mmINTERRUPT_CNTL 0x151a
#define mmINTERRUPT_CNTL2 0x151b
#define mmBIF_DEBUG_CNTL 0x151c
#define mmBIF_DEBUG_MUX 0x151d
#define mmBIF_DEBUG_OUT 0x151e
#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
#define mmCLKREQB_PAD_CNTL 0x1521
#define mmCLKREQB_PERF_COUNTER 0x1522
#define mmBIF_XDMA_LO 0x14c0
#define mmBIF_XDMA_HI 0x14c1
#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
#define mmBIF_DOORBELL_CNTL 0x14c3
#define mmBIF_SLVARB_MODE 0x14c4
#define mmBIF_CLK_CTRL 0x14c5
#define mmBIF_FB_EN 0x1524
#define mmBIF_BUSNUM_CNTL1 0x1525
#define mmBIF_BUSNUM_LIST0 0x1526
#define mmBIF_BUSNUM_LIST1 0x1527
#define mmBIF_BUSNUM_CNTL2 0x152b
#define mmBIF_BUSY_DELAY_CNTR 0x1529
#define mmBIF_PERFMON_CNTL 0x152c
#define mmBIF_PERFCOUNTER0_RESULT 0x152d
#define mmBIF_PERFCOUNTER1_RESULT 0x152e
#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
#define mmGPU_HDP_FLUSH_REQ 0x1537
#define mmGPU_HDP_FLUSH_DONE 0x1538
#define mmSLAVE_HANG_ERROR 0x153b
#define mmCAPTURE_HOST_BUSNUM 0x153c
#define mmHOST_BUSNUM 0x153d
#define mmPEER_REG_RANGE0 0x153e
#define mmPEER_REG_RANGE1 0x153f
#define mmPEER0_FB_OFFSET_HI 0x14f3
#define mmPEER0_FB_OFFSET_LO 0x14f2
#define mmPEER1_FB_OFFSET_HI 0x14f1
#define mmPEER1_FB_OFFSET_LO 0x14f0
#define mmPEER2_FB_OFFSET_HI 0x14ef
#define mmPEER2_FB_OFFSET_LO 0x14ee
#define mmPEER3_FB_OFFSET_HI 0x14ed
#define mmPEER3_FB_OFFSET_LO 0x14ec
#define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb
#define mmBIF_MST_TRANS_PENDING 0x14ea
#define mmBIF_SLV_TRANS_PENDING 0x14e9
#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
#define mmBACO_CNTL 0x14e5
#define mmBF_ANA_ISO_CNTL 0x14c7
#define mmMEM_TYPE_CNTL 0x14e4
#define mmBIF_BACO_DEBUG 0x14df
#define mmBIF_BACO_DEBUG_LATCH 0x14dc
#define mmBACO_CNTL_MISC 0x14db
#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8
#define mmBIF_VDDGFX_GFX0_LOWER 0x1428
#define mmBIF_VDDGFX_GFX0_UPPER 0x1429
#define mmBIF_VDDGFX_GFX1_LOWER 0x142a
#define mmBIF_VDDGFX_GFX1_UPPER 0x142b
#define mmBIF_VDDGFX_GFX2_LOWER 0x142c
#define mmBIF_VDDGFX_GFX2_UPPER 0x142d
#define mmBIF_VDDGFX_GFX3_LOWER 0x142e
#define mmBIF_VDDGFX_GFX3_UPPER 0x142f
#define mmBIF_VDDGFX_GFX4_LOWER 0x1430
#define mmBIF_VDDGFX_GFX4_UPPER 0x1431
#define mmBIF_VDDGFX_GFX5_LOWER 0x1432
#define mmBIF_VDDGFX_GFX5_UPPER 0x1433
#define mmBIF_VDDGFX_RSV1_LOWER 0x1434
#define mmBIF_VDDGFX_RSV1_UPPER 0x1435
#define mmBIF_VDDGFX_RSV2_LOWER 0x1436
#define mmBIF_VDDGFX_RSV2_UPPER 0x1437
#define mmBIF_VDDGFX_RSV3_LOWER 0x1438
#define mmBIF_VDDGFX_RSV3_UPPER 0x1439
#define mmBIF_VDDGFX_RSV4_LOWER 0x143a
#define mmBIF_VDDGFX_RSV4_UPPER 0x143b
#define mmBIF_VDDGFX_FB_CMP 0x143c
#define mmBIF_SMU_INDEX 0x143d
#define mmBIF_SMU_DATA 0x143e
#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc
#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd
#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe
#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff
#define mmIMPCTL_RESET 0x14f5
#define mmGARLIC_FLUSH_CNTL 0x1401
#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
#define mmGARLIC_FLUSH_REQ 0x1412
#define mmGPU_GARLIC_FLUSH_REQ 0x1413
#define mmGPU_GARLIC_FLUSH_DONE 0x1414
#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426
#define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427
#define mmBIOS_SCRATCH_0 0x5c9
#define mmBIOS_SCRATCH_1 0x5ca
#define mmBIOS_SCRATCH_2 0x5cb
#define mmBIOS_SCRATCH_3 0x5cc
#define mmBIOS_SCRATCH_4 0x5cd
#define mmBIOS_SCRATCH_5 0x5ce
#define mmBIOS_SCRATCH_6 0x5cf
#define mmBIOS_SCRATCH_7 0x5d0
#define mmBIOS_SCRATCH_8 0x5d1
#define mmBIOS_SCRATCH_9 0x5d2
#define mmBIOS_SCRATCH_10 0x5d3
#define mmBIOS_SCRATCH_11 0x5d4
#define mmBIOS_SCRATCH_12 0x5d5
#define mmBIOS_SCRATCH_13 0x5d6
#define mmBIOS_SCRATCH_14 0x5d7
#define mmBIOS_SCRATCH_15 0x5d8
#define mmBIF_RB_CNTL 0x1530
#define mmBIF_RB_BASE 0x1531
#define mmBIF_RB_RPTR 0x1532
#define mmBIF_RB_WPTR 0x1533
#define mmBIF_RB_WPTR_ADDR_HI 0x1534
#define mmBIF_RB_WPTR_ADDR_LO 0x1535
#define mmMAILBOX_INDEX 0x14c6
#define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8
#define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9
#define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca
#define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb
#define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc
#define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd
#define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce
#define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf
#define mmMAILBOX_CONTROL 0x14d0
#define mmMAILBOX_INT_CNTL 0x14d1
#define mmBIF_VIRT_RESET_REQ 0x14d2
#define mmVM_INIT_STATUS 0x14d3
#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5
#define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6
#define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8
#define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c
#define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d
#define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e
#define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f
#define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420
#define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421
#define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422
#define mmBIF_GPU_IDLE_LATENCY 0x1415
#define mmBIF_MMIO_MAP_RANGE0 0x1416
#define mmBIF_MMIO_MAP_RANGE1 0x1417
#define mmBIF_MMIO_MAP_RANGE2 0x1418
#define mmBIF_MMIO_MAP_RANGE3 0x1419
#define mmBIF_MMIO_MAP_RANGE4 0x141a
#define mmBIF_MMIO_MAP_RANGE5 0x141b
#define mmVENDOR_ID 0x0
#define mmDEVICE_ID 0x0
#define mmCOMMAND 0x1
#define mmSTATUS 0x1
#define mmREVISION_ID 0x2
#define mmPROG_INTERFACE 0x2
#define mmSUB_CLASS 0x2
#define mmBASE_CLASS 0x2
#define mmCACHE_LINE 0x3
#define mmLATENCY 0x3
#define mmHEADER 0x3
#define mmBIST 0x3
#define mmBASE_ADDR_1 0x4
#define mmBASE_ADDR_2 0x5
#define mmBASE_ADDR_3 0x6
#define mmBASE_ADDR_4 0x7
#define mmBASE_ADDR_5 0x8
#define mmBASE_ADDR_6 0x9
#define mmROM_BASE_ADDR 0xc
#define mmCAP_PTR 0xd
#define mmINTERRUPT_LINE 0xf
#define mmINTERRUPT_PIN 0xf
#define mmADAPTER_ID 0xb
#define mmMIN_GRANT 0xf
#define mmMAX_LATENCY 0xf
#define mmVENDOR_CAP_LIST 0x12
#define mmADAPTER_ID_W 0x13
#define mmPMI_CAP_LIST 0x14
#define mmPMI_CAP 0x14
#define mmPMI_STATUS_CNTL 0x15
#define mmPCIE_CAP_LIST 0x16
#define mmPCIE_CAP 0x16
#define mmDEVICE_CAP 0x17
#define mmDEVICE_CNTL 0x18
#define mmDEVICE_STATUS 0x18
#define mmLINK_CAP 0x19
#define mmLINK_CNTL 0x1a
#define mmLINK_STATUS 0x1a
#define mmDEVICE_CAP2 0x1f
#define mmDEVICE_CNTL2 0x20
#define mmDEVICE_STATUS2 0x20
#define mmLINK_CAP2 0x21
#define mmLINK_CNTL2 0x22
#define mmLINK_STATUS2 0x22
#define mmMSI_CAP_LIST 0x28
#define mmMSI_MSG_CNTL 0x28
#define mmMSI_MSG_ADDR_LO 0x29
#define mmMSI_MSG_ADDR_HI 0x2a
#define mmMSI_MSG_DATA_64 0x2b
#define mmMSI_MSG_DATA 0x2a
#define mmMSI_MASK 0x2b
#define mmMSI_PENDING 0x2c
#define mmMSI_MASK_64 0x2c
#define mmMSI_PENDING_64 0x2d
#define mmMSIX_CAP_LIST 0x30
#define mmMSIX_MSG_CNTL 0x30
#define mmMSIX_TABLE 0x31
#define mmMSIX_PBA 0x32
#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
#define mmPCIE_VENDOR_SPECIFIC1 0x42
#define mmPCIE_VENDOR_SPECIFIC2 0x43
#define mmPCIE_VC_ENH_CAP_LIST 0x44
#define mmPCIE_PORT_VC_CAP_REG1 0x45
#define mmPCIE_PORT_VC_CAP_REG2 0x46
#define mmPCIE_PORT_VC_CNTL 0x47
#define mmPCIE_PORT_VC_STATUS 0x47
#define mmPCIE_VC0_RESOURCE_CAP 0x48
#define mmPCIE_VC0_RESOURCE_CNTL 0x49
#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
#define mmPCIE_VC1_RESOURCE_CAP 0x4b
#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
#define mmPCIE_UNCORR_ERR_STATUS 0x55
#define mmPCIE_UNCORR_ERR_MASK 0x56
#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
#define mmPCIE_CORR_ERR_STATUS 0x58
#define mmPCIE_CORR_ERR_MASK 0x59
#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
#define mmPCIE_HDR_LOG0 0x5b
#define mmPCIE_HDR_LOG1 0x5c
#define mmPCIE_HDR_LOG2 0x5d
#define mmPCIE_HDR_LOG3 0x5e
#define mmPCIE_TLP_PREFIX_LOG0 0x62
#define mmPCIE_TLP_PREFIX_LOG1 0x63
#define mmPCIE_TLP_PREFIX_LOG2 0x64
#define mmPCIE_TLP_PREFIX_LOG3 0x65
#define mmPCIE_BAR_ENH_CAP_LIST 0x80
#define mmPCIE_BAR1_CAP 0x81
#define mmPCIE_BAR1_CNTL 0x82
#define mmPCIE_BAR2_CAP 0x83
#define mmPCIE_BAR2_CNTL 0x84
#define mmPCIE_BAR3_CAP 0x85
#define mmPCIE_BAR3_CNTL 0x86
#define mmPCIE_BAR4_CAP 0x87
#define mmPCIE_BAR4_CNTL 0x88
#define mmPCIE_BAR5_CAP 0x89
#define mmPCIE_BAR5_CNTL 0x8a
#define mmPCIE_BAR6_CAP 0x8b
#define mmPCIE_BAR6_CNTL 0x8c
#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
#define mmPCIE_PWR_BUDGET_DATA 0x92
#define mmPCIE_PWR_BUDGET_CAP 0x93
#define mmPCIE_DPA_ENH_CAP_LIST 0x94
#define mmPCIE_DPA_CAP 0x95
#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
#define mmPCIE_DPA_STATUS 0x97
#define mmPCIE_DPA_CNTL 0x97
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
#define mmPCIE_LINK_CNTL3 0x9d
#define mmPCIE_LANE_ERROR_STATUS 0x9e
#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
#define mmPCIE_ACS_CAP 0xa9
#define mmPCIE_ACS_CNTL 0xa9
#define mmPCIE_ATS_ENH_CAP_LIST 0xac
#define mmPCIE_ATS_CAP 0xad
#define mmPCIE_ATS_CNTL 0xad
#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
#define mmPCIE_PAGE_REQ_CNTL 0xb1
#define mmPCIE_PAGE_REQ_STATUS 0xb1
#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
#define mmPCIE_PASID_CAP 0xb5
#define mmPCIE_PASID_CNTL 0xb5
#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
#define mmPCIE_TPH_REQR_CAP 0xb9
#define mmPCIE_TPH_REQR_CNTL 0xba
#define mmPCIE_MC_ENH_CAP_LIST 0xbc
#define mmPCIE_MC_CAP 0xbd
#define mmPCIE_MC_CNTL 0xbd
#define mmPCIE_MC_ADDR0 0xbe
#define mmPCIE_MC_ADDR1 0xbf
#define mmPCIE_MC_RCV0 0xc0
#define mmPCIE_MC_RCV1 0xc1
#define mmPCIE_MC_BLOCK_ALL0 0xc2
#define mmPCIE_MC_BLOCK_ALL1 0xc3
#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
#define mmPCIE_LTR_CAP 0xc9
#define mmPCIE_ARI_ENH_CAP_LIST 0xca
#define mmPCIE_ARI_CAP 0xcb
#define mmPCIE_ARI_CNTL 0xcb
#define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc
#define mmPCIE_SRIOV_CAP 0xcd
#define mmPCIE_SRIOV_CONTROL 0xce
#define mmPCIE_SRIOV_STATUS 0xce
#define mmPCIE_SRIOV_INITIAL_VFS 0xcf
#define mmPCIE_SRIOV_TOTAL_VFS 0xcf
#define mmPCIE_SRIOV_NUM_VFS 0xd0
#define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0
#define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1
#define mmPCIE_SRIOV_VF_STRIDE 0xd1
#define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2
#define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3
#define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4
#define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5
#define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6
#define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7
#define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8
#define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9
#define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda
#define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb
#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126
#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127
#define mmPCIE_INDEX 0xe
#define mmPCIE_DATA 0xf
#define mmPCIE_INDEX_2 0xc
#define mmPCIE_DATA_2 0xd
#define ixPCIE_HOLD_TRAINING_A 0x1500820
#define ixLNCNT_CONTROL 0x1508030
#define ixCFG_LNC_WINDOW 0x1508031
#define ixLNCNT_QUAN_THRD 0x1508032
#define ixLNCNT_WEIGHT 0x1508033
#define ixLNC_TOTAL_WACC 0x1508034
#define ixLNC_BW_WACC 0x1508035
#define ixLNC_CMN_WACC 0x1508036
#define mmPCIE_EFUSE 0xfc0
#define mmPCIE_EFUSE2 0xfc1
#define mmPCIE_EFUSE3 0xfc2
#define mmPCIE_EFUSE4 0xfc3
#define mmPCIE_EFUSE5 0xfc4
#define mmPCIE_EFUSE6 0xfc5
#define mmPCIE_EFUSE7 0xfc6
#define ixPCIE_WRAP_SCRATCH1 0x1308001
#define ixPCIE_WRAP_SCRATCH2 0x1308002
#define ixPCIE_WRAP_REG_TARG_MISC 0x1308005
#define ixPCIE_WRAP_DTM_MISC 0x1308006
#define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007
#define ixPCIE_WRAP_MISC 0x1308008
#define ixPCIE_WRAP_PIF_MISC 0x1308009
#define ixPCIE_RXDET_OVERRIDE 0x130800a
#define ixREG_ADAPT_pciecore0_CONTROL 0x1308090
#define ixREG_ADAPT_pwregt_CONTROL 0x1308096
#define ixREG_ADAPT_pwregr_CONTROL 0x1308097
#define ixREG_ADAPT_pif0_CONTROL 0x1308098
#define ixPCIE_RESERVED 0x1400000
#define ixPCIE_SCRATCH 0x1400001
#define ixPCIE_HW_DEBUG 0x1400002
#define ixPCIE_RX_NUM_NAK 0x140000e
#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
#define ixPCIE_CNTL 0x1400010
#define ixPCIE_CONFIG_CNTL 0x1400011
#define ixPCIE_DEBUG_CNTL 0x1400012
#define ixPCIE_INT_CNTL 0x140001a
#define ixPCIE_INT_STATUS 0x140001b
#define ixPCIE_CNTL2 0x140001c
#define ixPCIE_RX_CNTL2 0x140001d
#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
#define ixPCIE_CI_CNTL 0x1400020
#define ixPCIE_BUS_CNTL 0x1400021
#define ixPCIE_LC_STATE6 0x1400022
#define ixPCIE_LC_STATE7 0x1400023
#define ixPCIE_LC_STATE8 0x1400024
#define ixPCIE_LC_STATE9 0x1400025
#define ixPCIE_LC_STATE10 0x1400026
#define ixPCIE_LC_STATE11 0x1400027
#define ixPCIE_LC_STATUS1 0x1400028
#define ixPCIE_LC_STATUS2 0x1400029
#define ixPCIE_WPR_CNTL 0x1400030
#define ixPCIE_RX_LAST_TLP0 0x1400031
#define ixPCIE_RX_LAST_TLP1 0x1400032
#define ixPCIE_RX_LAST_TLP2 0x1400033
#define ixPCIE_RX_LAST_TLP3 0x1400034
#define ixPCIE_TX_LAST_TLP0 0x1400035
#define ixPCIE_TX_LAST_TLP1 0x1400036
#define ixPCIE_TX_LAST_TLP2 0x1400037
#define ixPCIE_TX_LAST_TLP3 0x1400038
#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
#define ixPCIE_I2C_REG_DATA 0x140003b
#define ixPCIE_CFG_CNTL 0x140003c
#define ixPCIE_LC_PM_CNTL 0x140003d
#define ixPCIE_P_CNTL 0x1400040
#define ixPCIE_P_BUF_STATUS 0x1400041
#define ixPCIE_P_DECODER_STATUS 0x1400042
#define ixPCIE_P_MISC_STATUS 0x1400043
#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
#define ixPCIE_OBFF_CNTL 0x1400061
#define ixPCIE_TX_LTR_CNTL 0x1400060
#define ixPCIE_IDLE_STATUS 0x1400062
#define ixPCIE_PERF_COUNT_CNTL 0x1400080
#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
#define ixPCIE_STRAP_F0 0x14000b0
#define ixPCIE_STRAP_F1 0x14000b1
#define ixPCIE_STRAP_F2 0x14000b2
#define ixPCIE_STRAP_F3 0x14000b3
#define ixPCIE_STRAP_F4 0x14000b4
#define ixPCIE_STRAP_F5 0x14000b5
#define ixPCIE_STRAP_F6 0x14000b6
#define ixPCIE_STRAP_MSIX 0x14000b7
#define ixPCIE_STRAP_MISC 0x14000c0
#define ixPCIE_STRAP_MISC2 0x14000c1
#define ixPCIE_STRAP_PI 0x14000c2
#define ixPCIE_STRAP_I2C_BD 0x14000c4
#define ixPCIE_PRBS_CLR 0x14000c8
#define ixPCIE_PRBS_STATUS1 0x14000c9
#define ixPCIE_PRBS_STATUS2 0x14000ca
#define ixPCIE_PRBS_FREERUN 0x14000cb
#define ixPCIE_PRBS_MISC 0x14000cc
#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
#define ixPCIE_PRBS_ERRCNT_10 0x14000da
#define ixPCIE_PRBS_ERRCNT_11 0x14000db
#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
#define ixPCIE_PRBS_ERRCNT_14 0x14000de
#define ixPCIE_PRBS_ERRCNT_15 0x14000df
#define ixPCIE_F0_DPA_CAP 0x14000e0
#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
#define ixPCIE_F0_DPA_CNTL 0x14000e5
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
#define mmSWRST_COMMAND_STATUS 0x14a0
#define mmSWRST_GENERAL_CONTROL 0x14a1
#define mmSWRST_COMMAND_0 0x14a2
#define mmSWRST_COMMAND_1 0x14a3
#define mmSWRST_CONTROL_0 0x14a4
#define mmSWRST_CONTROL_1 0x14a5
#define mmSWRST_CONTROL_2 0x14a6
#define mmSWRST_CONTROL_3 0x14a7
#define mmSWRST_CONTROL_4 0x14a8
#define mmSWRST_CONTROL_5 0x14a9
#define mmSWRST_CONTROL_6 0x14aa
#define mmSWRST_EP_COMMAND_0 0x14ab
#define mmSWRST_EP_CONTROL_0 0x14ac
#define mmCPM_CONTROL 0x14b8
#define mmGSKT_CONTROL 0x14bf
#define ixLM_CONTROL 0x1400120
#define ixLM_PCIETXMUX0 0x1400121
#define ixLM_PCIETXMUX1 0x1400122
#define ixLM_PCIETXMUX2 0x1400123
#define ixLM_PCIETXMUX3 0x1400124
#define ixLM_PCIERXMUX0 0x1400125
#define ixLM_PCIERXMUX1 0x1400126
#define ixLM_PCIERXMUX2 0x1400127
#define ixLM_PCIERXMUX3 0x1400128
#define ixLM_LANEENABLE 0x1400129
#define ixLM_PRBSCONTROL 0x140012a
#define ixLM_POWERCONTROL 0x140012b
#define ixLM_POWERCONTROL1 0x140012c
#define ixLM_POWERCONTROL2 0x140012d
#define ixLM_POWERCONTROL3 0x140012e
#define ixLM_POWERCONTROL4 0x140012f
#define ixPB0_GLB_CTRL_REG0 0x1200004
#define ixPB0_GLB_CTRL_REG1 0x1200008
#define ixPB0_GLB_CTRL_REG2 0x120000c
#define ixPB0_GLB_CTRL_REG3 0x1200010
#define ixPB0_GLB_CTRL_REG4 0x1200014
#define ixPB0_GLB_CTRL_REG5 0x1200018
#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
#define ixPB0_GLB_OVRD_REG0 0x1200030
#define ixPB0_GLB_OVRD_REG1 0x1200034
#define ixPB0_GLB_OVRD_REG2 0x1200038
#define ixPB0_HW_DEBUG 0x1202004
#define ixPB0_STRAP_GLB_REG0 0x1202020
#define ixPB0_STRAP_TX_REG0 0x1202024
#define ixPB0_STRAP_RX_REG0 0x1202028
#define ixPB0_STRAP_RX_REG1 0x120202c
#define ixPB0_STRAP_PLL_REG0 0x1202030
#define ixPB0_STRAP_PIN_REG0 0x1202034
#define ixPB0_STRAP_GLB_REG1 0x1202038
#define ixPB0_STRAP_GLB_REG2 0x120203c
#define ixPB0_DFT_JIT_INJ_REG0 0x1203000
#define ixPB0_DFT_JIT_INJ_REG1 0x1203004
#define ixPB0_DFT_JIT_INJ_REG2 0x1203008
#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
#define ixPB0_RX_GLB_CTRL_REG0 0x1206000
#define ixPB0_RX_GLB_CTRL_REG1 0x1206004
#define ixPB0_RX_GLB_CTRL_REG2 0x1206008
#define ixPB0_RX_GLB_CTRL_REG3 0x120600c
#define ixPB0_RX_GLB_CTRL_REG4 0x1206010
#define ixPB0_RX_GLB_CTRL_REG5 0x1206014
#define ixPB0_RX_GLB_CTRL_REG6 0x1206018
#define ixPB0_RX_GLB_CTRL_REG7 0x120601c
#define ixPB0_RX_GLB_CTRL_REG8 0x1206020
#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
#define ixPB0_RX_GLB_OVRD_REG0 0x1206030
#define ixPB0_RX_GLB_OVRD_REG1 0x1206034
#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
#define ixPB0_TX_GLB_CTRL_REG0 0x1208000
#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
#define ixPB0_TX_GLB_OVRD_REG0 0x1208030
#define ixPB0_TX_GLB_OVRD_REG1 0x1208034
#define ixPB0_TX_GLB_OVRD_REG2 0x1208038
#define ixPB0_TX_GLB_OVRD_REG3 0x120803c
#define ixPB0_TX_GLB_OVRD_REG4 0x1208040
#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
#define ixPB1_GLB_CTRL_REG0 0x2200004
#define ixPB1_GLB_CTRL_REG1 0x2200008
#define ixPB1_GLB_CTRL_REG2 0x220000c
#define ixPB1_GLB_CTRL_REG3 0x2200010
#define ixPB1_GLB_CTRL_REG4 0x2200014
#define ixPB1_GLB_CTRL_REG5 0x2200018
#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
#define ixPB1_GLB_OVRD_REG0 0x2200030
#define ixPB1_GLB_OVRD_REG1 0x2200034
#define ixPB1_GLB_OVRD_REG2 0x2200038
#define ixPB1_HW_DEBUG 0x2202004
#define ixPB1_STRAP_GLB_REG0 0x2202020
#define ixPB1_STRAP_TX_REG0 0x2202024
#define ixPB1_STRAP_RX_REG0 0x2202028
#define ixPB1_STRAP_RX_REG1 0x220202c
#define ixPB1_STRAP_PLL_REG0 0x2202030
#define ixPB1_STRAP_PIN_REG0 0x2202034
#define ixPB1_STRAP_GLB_REG1 0x2202038
#define ixPB1_STRAP_GLB_REG2 0x220203c
#define ixPB1_DFT_JIT_INJ_REG0 0x2203000
#define ixPB1_DFT_JIT_INJ_REG1 0x2203004
#define ixPB1_DFT_JIT_INJ_REG2 0x2203008
#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
#define ixPB1_RX_GLB_CTRL_REG0 0x2206000
#define ixPB1_RX_GLB_CTRL_REG1 0x2206004
#define ixPB1_RX_GLB_CTRL_REG2 0x2206008
#define ixPB1_RX_GLB_CTRL_REG3 0x220600c
#define ixPB1_RX_GLB_CTRL_REG4 0x2206010
#define ixPB1_RX_GLB_CTRL_REG5 0x2206014
#define ixPB1_RX_GLB_CTRL_REG6 0x2206018
#define ixPB1_RX_GLB_CTRL_REG7 0x220601c
#define ixPB1_RX_GLB_CTRL_REG8 0x2206020
#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
#define ixPB1_RX_GLB_OVRD_REG0 0x2206030
#define ixPB1_RX_GLB_OVRD_REG1 0x2206034
#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
#define ixPB1_TX_GLB_CTRL_REG0 0x2208000
#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
#define ixPB1_TX_GLB_OVRD_REG0 0x2208030
#define ixPB1_TX_GLB_OVRD_REG1 0x2208034
#define ixPB1_TX_GLB_OVRD_REG2 0x2208038
#define ixPB1_TX_GLB_OVRD_REG3 0x220803c
#define ixPB1_TX_GLB_OVRD_REG4 0x2208040
#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
#define ixPB0_PIF_SCRATCH 0x1100001
#define ixPB0_PIF_HW_DEBUG 0x1100002
#define ixPB0_PIF_STRAP_0 0x1100003
#define ixPB0_PIF_CTRL 0x1100004
#define ixPB0_PIF_TX_CTRL 0x1100008
#define ixPB0_PIF_TX_CTRL2 0x1100009
#define ixPB0_PIF_RX_CTRL 0x110000a
#define ixPB0_PIF_RX_CTRL2 0x110000b
#define ixPB0_PIF_GLB_OVRD 0x110000c
#define ixPB0_PIF_GLB_OVRD2 0x110000d
#define ixPB0_PIF_BIF_CMD_STATUS 0x1100010
#define ixPB0_PIF_CMD_BUS_CTRL 0x1100011
#define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013
#define ixPB0_PIF_LANE0_OVRD 0x1100014
#define ixPB0_PIF_LANE0_OVRD2 0x1100015
#define ixPB0_PIF_LANE1_OVRD 0x1100016
#define ixPB0_PIF_LANE1_OVRD2 0x1100017
#define ixPB0_PIF_LANE2_OVRD 0x1100018
#define ixPB0_PIF_LANE2_OVRD2 0x1100019
#define ixPB0_PIF_LANE3_OVRD 0x110001a
#define ixPB0_PIF_LANE3_OVRD2 0x110001b
#define ixPB0_PIF_LANE4_OVRD 0x110001c
#define ixPB0_PIF_LANE4_OVRD2 0x110001d
#define ixPB0_PIF_LANE5_OVRD 0x110001e
#define ixPB0_PIF_LANE5_OVRD2 0x110001f
#define ixPB0_PIF_LANE6_OVRD 0x1100020
#define ixPB0_PIF_LANE6_OVRD2 0x1100021
#define ixPB0_PIF_LANE7_OVRD 0x1100022
#define ixPB0_PIF_LANE7_OVRD2 0x1100023
#define ixPB1_PIF_SCRATCH 0x2100001
#define ixPB1_PIF_HW_DEBUG 0x2100002
#define ixPB1_PIF_STRAP_0 0x2100003
#define ixPB1_PIF_CTRL 0x2100004
#define ixPB1_PIF_TX_CTRL 0x2100008
#define ixPB1_PIF_TX_CTRL2 0x2100009
#define ixPB1_PIF_RX_CTRL 0x210000a
#define ixPB1_PIF_RX_CTRL2 0x210000b
#define ixPB1_PIF_GLB_OVRD 0x210000c
#define ixPB1_PIF_GLB_OVRD2 0x210000d
#define ixPB1_PIF_BIF_CMD_STATUS 0x2100010
#define ixPB1_PIF_CMD_BUS_CTRL 0x2100011
#define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013
#define ixPB1_PIF_LANE0_OVRD 0x2100014
#define ixPB1_PIF_LANE0_OVRD2 0x2100015
#define ixPB1_PIF_LANE1_OVRD 0x2100016
#define ixPB1_PIF_LANE1_OVRD2 0x2100017
#define ixPB1_PIF_LANE2_OVRD 0x2100018
#define ixPB1_PIF_LANE2_OVRD2 0x2100019
#define ixPB1_PIF_LANE3_OVRD 0x210001a
#define ixPB1_PIF_LANE3_OVRD2 0x210001b
#define ixPB1_PIF_LANE4_OVRD 0x210001c
#define ixPB1_PIF_LANE4_OVRD2 0x210001d
#define ixPB1_PIF_LANE5_OVRD 0x210001e
#define ixPB1_PIF_LANE5_OVRD2 0x210001f
#define ixPB1_PIF_LANE6_OVRD 0x2100020
#define ixPB1_PIF_LANE6_OVRD2 0x2100021
#define ixPB1_PIF_LANE7_OVRD 0x2100022
#define ixPB1_PIF_LANE7_OVRD2 0x2100023
#define ixPCIEP_RESERVED 0x10010000
#define ixPCIEP_SCRATCH 0x10010001
#define ixPCIEP_HW_DEBUG 0x10010002
#define ixPCIEP_PORT_CNTL 0x10010010
#define ixPCIE_TX_CNTL 0x10010020
#define ixPCIE_TX_REQUESTER_ID 0x10010021
#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
#define ixPCIE_TX_SEQ 0x10010024
#define ixPCIE_TX_REPLAY 0x10010025
#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
#define ixPCIE_TX_CREDITS_STATUS 0x10010036
#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
#define ixPCIE_FC_P 0x10010060
#define ixPCIE_FC_NP 0x10010061
#define ixPCIE_FC_CPL 0x10010062
#define ixPCIE_ERR_CNTL 0x1001006a
#define ixPCIE_RX_CNTL 0x10010070
#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
#define ixPCIE_RX_CNTL3 0x10010074
#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
#define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083
#define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084
#define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085
#define ixPCIE_LC_CNTL 0x100100a0
#define ixPCIE_LC_CNTL2 0x100100b1
#define ixPCIE_LC_CNTL3 0x100100b5
#define ixPCIE_LC_CNTL4 0x100100b6
#define ixPCIE_LC_CNTL5 0x100100b7
#define ixPCIE_LC_CNTL6 0x100100bb
#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
#define ixPCIE_LC_SPEED_CNTL 0x100100a4
#define ixPCIE_LC_CDR_CNTL 0x100100b3
#define ixPCIE_LC_LANE_CNTL 0x100100b4
#define ixPCIE_LC_FORCE_COEFF 0x100100b8
#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
#define ixPCIE_LC_STATE0 0x100100a5
#define ixPCIE_LC_STATE1 0x100100a6
#define ixPCIE_LC_STATE2 0x100100a7
#define ixPCIE_LC_STATE3 0x100100a8
#define ixPCIE_LC_STATE4 0x100100a9
#define ixPCIE_LC_STATE5 0x100100aa
#define ixPCIEP_STRAP_LC 0x100100c0
#define ixPCIEP_STRAP_MISC 0x100100c1
#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
#define ixPCIEP_HPGI_PRIVATE 0x100100d2
#define ixPCIEP_HPGI 0x100100da
#define mmPCIEMSIX_VECT0_ADDR_LO 0x6000
#define mmPCIEMSIX_VECT0_ADDR_HI 0x6001
#define mmPCIEMSIX_VECT0_MSG_DATA 0x6002
#define mmPCIEMSIX_VECT0_CONTROL 0x6003
#define mmPCIEMSIX_VECT1_ADDR_LO 0x6004
#define mmPCIEMSIX_VECT1_ADDR_HI 0x6005
#define mmPCIEMSIX_VECT1_MSG_DATA 0x6006
#define mmPCIEMSIX_VECT1_CONTROL 0x6007
#define mmPCIEMSIX_VECT2_ADDR_LO 0x6008
#define mmPCIEMSIX_VECT2_ADDR_HI 0x6009
#define mmPCIEMSIX_VECT2_MSG_DATA 0x600a
#define mmPCIEMSIX_VECT2_CONTROL 0x600b
#define mmPCIEMSIX_VECT3_ADDR_LO 0x600c
#define mmPCIEMSIX_VECT3_ADDR_HI 0x600d
#define mmPCIEMSIX_VECT3_MSG_DATA 0x600e
#define mmPCIEMSIX_VECT3_CONTROL 0x600f
#define mmPCIEMSIX_PBA 0x6200
#define mmBIF_RFE_SNOOP_REG 0x27
#define mmBIF_RFE_WARMRST_CNTL 0x1459
#define mmBIF_RFE_SOFTRST_CNTL 0x1441
#define mmBIF_RFE_IMPRST_CNTL 0x1458
#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
#define mmBIF_PWDN_COMMAND 0x1444
#define mmBIF_PWDN_STATUS 0x1445
#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
#define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448
#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449
#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
#define mmBIF_RFE_MMCFG_CNTL 0x144c
#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
#define mmBIF_IMPCTL_SMPLCNTL 0x1450
#define mmBIF_IMPCTL_RXCNTL 0x1451
#define mmBIF_IMPCTL_TXCNTL_pd 0x1452
#define mmBIF_IMPCTL_TXCNTL_pu 0x1453
#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
#endif /* BIF_5_0_D_H */
drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h 0 → 100644
View file @ 848ebfd7
/*
* BIF_5_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BIF_5_0_ENUM_H
#define BIF_5_0_ENUM_H
typedef enum SurfaceEndian {
ENDIAN_NONE = 0x0,
ENDIAN_8IN16 = 0x1,
ENDIAN_8IN32 = 0x2,
ENDIAN_8IN64 = 0x3,
} SurfaceEndian;
typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL = 0x0,
ARRAY_LINEAR_ALIGNED = 0x1,
ARRAY_1D_TILED_THIN1 = 0x2,
ARRAY_1D_TILED_THICK = 0x3,
ARRAY_2D_TILED_THIN1 = 0x4,
ARRAY_PRT_TILED_THIN1 = 0x5,
ARRAY_PRT_2D_TILED_THIN1 = 0x6,
ARRAY_2D_TILED_THICK = 0x7,
ARRAY_2D_TILED_XTHICK = 0x8,
ARRAY_PRT_TILED_THICK = 0x9,
ARRAY_PRT_2D_TILED_THICK = 0xa,
ARRAY_PRT_3D_TILED_THIN1 = 0xb,
ARRAY_3D_TILED_THIN1 = 0xc,
ARRAY_3D_TILED_THICK = 0xd,
ARRAY_3D_TILED_XTHICK = 0xe,
ARRAY_PRT_3D_TILED_THICK = 0xf,
} ArrayMode;
typedef enum PipeTiling {
CONFIG_1_PIPE = 0x0,
CONFIG_2_PIPE = 0x1,
CONFIG_4_PIPE = 0x2,
CONFIG_8_PIPE = 0x3,
} PipeTiling;
typedef enum BankTiling {
CONFIG_4_BANK = 0x0,
CONFIG_8_BANK = 0x1,
} BankTiling;
typedef enum GroupInterleave {
CONFIG_256B_GROUP = 0x0,
CONFIG_512B_GROUP = 0x1,
} GroupInterleave;
typedef enum RowTiling {
CONFIG_1KB_ROW = 0x0,
CONFIG_2KB_ROW = 0x1,
CONFIG_4KB_ROW = 0x2,
CONFIG_8KB_ROW = 0x3,
CONFIG_1KB_ROW_OPT = 0x4,
CONFIG_2KB_ROW_OPT = 0x5,
CONFIG_4KB_ROW_OPT = 0x6,
CONFIG_8KB_ROW_OPT = 0x7,
} RowTiling;
typedef enum BankSwapBytes {
CONFIG_128B_SWAPS = 0x0,
CONFIG_256B_SWAPS = 0x1,
CONFIG_512B_SWAPS = 0x2,
CONFIG_1KB_SWAPS = 0x3,
} BankSwapBytes;
typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT = 0x0,
CONFIG_2KB_SPLIT = 0x1,
CONFIG_4KB_SPLIT = 0x2,
CONFIG_8KB_SPLIT = 0x3,
} SampleSplitBytes;
typedef enum NumPipes {
ADDR_CONFIG_1_PIPE = 0x0,
ADDR_CONFIG_2_PIPE = 0x1,
ADDR_CONFIG_4_PIPE = 0x2,
ADDR_CONFIG_8_PIPE = 0x3,
} NumPipes;
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
} PipeInterleaveSize;
typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
} BankInterleaveSize;
typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
} NumShaderEngines;
typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16 = 0x0,
ADDR_CONFIG_SE_TILE_32 = 0x1,
} ShaderEngineTileSize;
typedef enum NumGPUs {
ADDR_CONFIG_1_GPU = 0x0,
ADDR_CONFIG_2_GPU = 0x1,
ADDR_CONFIG_4_GPU = 0x2,
} NumGPUs;
typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16 = 0x0,
ADDR_CONFIG_GPU_TILE_32 = 0x1,
ADDR_CONFIG_GPU_TILE_64 = 0x2,
ADDR_CONFIG_GPU_TILE_128 = 0x3,
} MultiGPUTileSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x0,
ADDR_CONFIG_2KB_ROW = 0x1,
ADDR_CONFIG_4KB_ROW = 0x2,
} RowSize;
typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES = 0x0,
ADDR_CONFIG_2_LOWER_PIPES = 0x1,
} NumLowerPipes;
typedef enum DebugBlockId {
DBG_CLIENT_BLKID_RESERVED = 0x0,
DBG_CLIENT_BLKID_dbg = 0x1,
DBG_CLIENT_BLKID_scf2 = 0x2,
DBG_CLIENT_BLKID_mcd5 = 0x3,
DBG_CLIENT_BLKID_vmc = 0x4,
DBG_CLIENT_BLKID_sx30 = 0x5,
DBG_CLIENT_BLKID_mcd2 = 0x6,
DBG_CLIENT_BLKID_bci1 = 0x7,
DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
DBG_CLIENT_BLKID_mcc0 = 0x9,
DBG_CLIENT_BLKID_uvdf_0 = 0xa,
DBG_CLIENT_BLKID_uvdf_1 = 0xb,
DBG_CLIENT_BLKID_uvdf_2 = 0xc,
DBG_CLIENT_BLKID_uvdi_0 = 0xd,
DBG_CLIENT_BLKID_bci0 = 0xe,
DBG_CLIENT_BLKID_vcec0_0 = 0xf,
DBG_CLIENT_BLKID_cb100 = 0x10,
DBG_CLIENT_BLKID_cb001 = 0x11,
DBG_CLIENT_BLKID_mcd4 = 0x12,
DBG_CLIENT_BLKID_tmonw00 = 0x13,
DBG_CLIENT_BLKID_cb101 = 0x14,
DBG_CLIENT_BLKID_sx10 = 0x15,
DBG_CLIENT_BLKID_cb301 = 0x16,
DBG_CLIENT_BLKID_tmonw01 = 0x17,
DBG_CLIENT_BLKID_vcea0_0 = 0x18,
DBG_CLIENT_BLKID_vcea0_1 = 0x19,
DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
DBG_CLIENT_BLKID_scf1 = 0x1c,
DBG_CLIENT_BLKID_sx20 = 0x1d,
DBG_CLIENT_BLKID_spim1 = 0x1e,
DBG_CLIENT_BLKID_pa10 = 0x1f,
DBG_CLIENT_BLKID_pa00 = 0x20,
DBG_CLIENT_BLKID_gmcon = 0x21,
DBG_CLIENT_BLKID_mcb = 0x22,
DBG_CLIENT_BLKID_vgt0 = 0x23,
DBG_CLIENT_BLKID_pc0 = 0x24,
DBG_CLIENT_BLKID_bci2 = 0x25,
DBG_CLIENT_BLKID_uvdb_0 = 0x26,
DBG_CLIENT_BLKID_spim3 = 0x27,
DBG_CLIENT_BLKID_cpc_0 = 0x28,
DBG_CLIENT_BLKID_cpc_1 = 0x29,
DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
DBG_CLIENT_BLKID_cb000 = 0x2e,
DBG_CLIENT_BLKID_spim0 = 0x2f,
DBG_CLIENT_BLKID_mcc2 = 0x30,
DBG_CLIENT_BLKID_ds0 = 0x31,
DBG_CLIENT_BLKID_srbm = 0x32,
DBG_CLIENT_BLKID_ih = 0x33,
DBG_CLIENT_BLKID_sem = 0x34,
DBG_CLIENT_BLKID_sdma_0 = 0x35,
DBG_CLIENT_BLKID_sdma_1 = 0x36,
DBG_CLIENT_BLKID_hdp = 0x37,
DBG_CLIENT_BLKID_acp_0 = 0x38,
DBG_CLIENT_BLKID_acp_1 = 0x39,
DBG_CLIENT_BLKID_cb200 = 0x3a,
DBG_CLIENT_BLKID_scf3 = 0x3b,
DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
DBG_CLIENT_BLKID_vcea1_3 = 0x40,
DBG_CLIENT_BLKID_bci3 = 0x41,
DBG_CLIENT_BLKID_mcd0 = 0x42,
DBG_CLIENT_BLKID_pa11 = 0x43,
DBG_CLIENT_BLKID_pa01 = 0x44,
DBG_CLIENT_BLKID_cb201 = 0x45,
DBG_CLIENT_BLKID_spim2 = 0x46,
DBG_CLIENT_BLKID_vgt2 = 0x47,
DBG_CLIENT_BLKID_pc2 = 0x48,
DBG_CLIENT_BLKID_smu_0 = 0x49,
DBG_CLIENT_BLKID_smu_1 = 0x4a,
DBG_CLIENT_BLKID_smu_2 = 0x4b,
DBG_CLIENT_BLKID_cb1 = 0x4c,
DBG_CLIENT_BLKID_ia0 = 0x4d,
DBG_CLIENT_BLKID_wd = 0x4e,
DBG_CLIENT_BLKID_ia1 = 0x4f,
DBG_CLIENT_BLKID_vcec1_0 = 0x50,
DBG_CLIENT_BLKID_scf0 = 0x51,
DBG_CLIENT_BLKID_vgt1 = 0x52,
DBG_CLIENT_BLKID_pc1 = 0x53,
DBG_CLIENT_BLKID_cb0 = 0x54,
DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
DBG_CLIENT_BLKID_vceb0_0 = 0x79,
DBG_CLIENT_BLKID_vgt3 = 0x7a,
DBG_CLIENT_BLKID_pc3 = 0x7b,
DBG_CLIENT_BLKID_mcd3 = 0x7c,
DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
DBG_CLIENT_BLKID_uvdu_3 = 0x80,
DBG_CLIENT_BLKID_uvdu_4 = 0x81,
DBG_CLIENT_BLKID_uvdu_5 = 0x82,
DBG_CLIENT_BLKID_uvdu_6 = 0x83,
DBG_CLIENT_BLKID_cb300 = 0x84,
DBG_CLIENT_BLKID_mcd1 = 0x85,
DBG_CLIENT_BLKID_sx00 = 0x86,
DBG_CLIENT_BLKID_uvdc_0 = 0x87,
DBG_CLIENT_BLKID_uvdc_1 = 0x88,
DBG_CLIENT_BLKID_mcc3 = 0x89,
DBG_CLIENT_BLKID_cpg_0 = 0x8a,
DBG_CLIENT_BLKID_cpg_1 = 0x8b,
DBG_CLIENT_BLKID_gck = 0x8c,
DBG_CLIENT_BLKID_mcc1 = 0x8d,
DBG_CLIENT_BLKID_cpf_0 = 0x8e,
DBG_CLIENT_BLKID_cpf_1 = 0x8f,
DBG_CLIENT_BLKID_rlc = 0x90,
DBG_CLIENT_BLKID_grbm = 0x91,
DBG_CLIENT_BLKID_sammsp = 0x92,
DBG_CLIENT_BLKID_dci_pg = 0x93,
DBG_CLIENT_BLKID_dci_0 = 0x94,
DBG_CLIENT_BLKID_dccg0_0 = 0x95,
DBG_CLIENT_BLKID_dccg0_1 = 0x96,
DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
} DebugBlockId;
typedef enum DebugBlockId_OLD {
DBG_BLOCK_ID_RESERVED = 0x0,
DBG_BLOCK_ID_DBG = 0x1,
DBG_BLOCK_ID_VMC = 0x2,
DBG_BLOCK_ID_PDMA = 0x3,
DBG_BLOCK_ID_CG = 0x4,
DBG_BLOCK_ID_SRBM = 0x5,
DBG_BLOCK_ID_GRBM = 0x6,
DBG_BLOCK_ID_RLC = 0x7,
DBG_BLOCK_ID_CSC = 0x8,
DBG_BLOCK_ID_SEM = 0x9,
DBG_BLOCK_ID_IH = 0xa,
DBG_BLOCK_ID_SC = 0xb,
DBG_BLOCK_ID_SQ = 0xc,
DBG_BLOCK_ID_AVP = 0xd,
DBG_BLOCK_ID_GMCON = 0xe,
DBG_BLOCK_ID_SMU = 0xf,
DBG_BLOCK_ID_DMA0 = 0x10,
DBG_BLOCK_ID_DMA1 = 0x11,
DBG_BLOCK_ID_SPIM = 0x12,
DBG_BLOCK_ID_GDS = 0x13,
DBG_BLOCK_ID_SPIS = 0x14,
DBG_BLOCK_ID_UNUSED0 = 0x15,
DBG_BLOCK_ID_PA0 = 0x16,
DBG_BLOCK_ID_PA1 = 0x17,
DBG_BLOCK_ID_CP0 = 0x18,
DBG_BLOCK_ID_CP1 = 0x19,
DBG_BLOCK_ID_CP2 = 0x1a,
DBG_BLOCK_ID_UNUSED1 = 0x1b,
DBG_BLOCK_ID_UVDU = 0x1c,
DBG_BLOCK_ID_UVDM = 0x1d,
DBG_BLOCK_ID_VCE = 0x1e,
DBG_BLOCK_ID_UNUSED2 = 0x1f,
DBG_BLOCK_ID_VGT0 = 0x20,
DBG_BLOCK_ID_VGT1 = 0x21,
DBG_BLOCK_ID_IA = 0x22,
DBG_BLOCK_ID_UNUSED3 = 0x23,
DBG_BLOCK_ID_SCT0 = 0x24,
DBG_BLOCK_ID_SCT1 = 0x25,
DBG_BLOCK_ID_SPM0 = 0x26,
DBG_BLOCK_ID_SPM1 = 0x27,
DBG_BLOCK_ID_TCAA = 0x28,
DBG_BLOCK_ID_TCAB = 0x29,
DBG_BLOCK_ID_TCCA = 0x2a,
DBG_BLOCK_ID_TCCB = 0x2b,
DBG_BLOCK_ID_MCC0 = 0x2c,
DBG_BLOCK_ID_MCC1 = 0x2d,
DBG_BLOCK_ID_MCC2 = 0x2e,
DBG_BLOCK_ID_MCC3 = 0x2f,
DBG_BLOCK_ID_SX0 = 0x30,
DBG_BLOCK_ID_SX1 = 0x31,
DBG_BLOCK_ID_SX2 = 0x32,
DBG_BLOCK_ID_SX3 = 0x33,
DBG_BLOCK_ID_UNUSED4 = 0x34,
DBG_BLOCK_ID_UNUSED5 = 0x35,
DBG_BLOCK_ID_UNUSED6 = 0x36,
DBG_BLOCK_ID_UNUSED7 = 0x37,
DBG_BLOCK_ID_PC0 = 0x38,
DBG_BLOCK_ID_PC1 = 0x39,
DBG_BLOCK_ID_UNUSED8 = 0x3a,
DBG_BLOCK_ID_UNUSED9 = 0x3b,
DBG_BLOCK_ID_UNUSED10 = 0x3c,
DBG_BLOCK_ID_UNUSED11 = 0x3d,
DBG_BLOCK_ID_MCB = 0x3e,
DBG_BLOCK_ID_UNUSED12 = 0x3f,
DBG_BLOCK_ID_SCB0 = 0x40,
DBG_BLOCK_ID_SCB1 = 0x41,
DBG_BLOCK_ID_UNUSED13 = 0x42,
DBG_BLOCK_ID_UNUSED14 = 0x43,
DBG_BLOCK_ID_SCF0 = 0x44,
DBG_BLOCK_ID_SCF1 = 0x45,
DBG_BLOCK_ID_UNUSED15 = 0x46,
DBG_BLOCK_ID_UNUSED16 = 0x47,
DBG_BLOCK_ID_BCI0 = 0x48,
DBG_BLOCK_ID_BCI1 = 0x49,
DBG_BLOCK_ID_BCI2 = 0x4a,
DBG_BLOCK_ID_BCI3 = 0x4b,
DBG_BLOCK_ID_UNUSED17 = 0x4c,
DBG_BLOCK_ID_UNUSED18 = 0x4d,
DBG_BLOCK_ID_UNUSED19 = 0x4e,
DBG_BLOCK_ID_UNUSED20 = 0x4f,
DBG_BLOCK_ID_CB00 = 0x50,
DBG_BLOCK_ID_CB01 = 0x51,
DBG_BLOCK_ID_CB02 = 0x52,
DBG_BLOCK_ID_CB03 = 0x53,
DBG_BLOCK_ID_CB04 = 0x54,
DBG_BLOCK_ID_UNUSED21 = 0x55,
DBG_BLOCK_ID_UNUSED22 = 0x56,
DBG_BLOCK_ID_UNUSED23 = 0x57,
DBG_BLOCK_ID_CB10 = 0x58,
DBG_BLOCK_ID_CB11 = 0x59,
DBG_BLOCK_ID_CB12 = 0x5a,
DBG_BLOCK_ID_CB13 = 0x5b,
DBG_BLOCK_ID_CB14 = 0x5c,
DBG_BLOCK_ID_UNUSED24 = 0x5d,
DBG_BLOCK_ID_UNUSED25 = 0x5e,
DBG_BLOCK_ID_UNUSED26 = 0x5f,
DBG_BLOCK_ID_TCP0 = 0x60,
DBG_BLOCK_ID_TCP1 = 0x61,
DBG_BLOCK_ID_TCP2 = 0x62,
DBG_BLOCK_ID_TCP3 = 0x63,
DBG_BLOCK_ID_TCP4 = 0x64,
DBG_BLOCK_ID_TCP5 = 0x65,
DBG_BLOCK_ID_TCP6 = 0x66,
DBG_BLOCK_ID_TCP7 = 0x67,
DBG_BLOCK_ID_TCP8 = 0x68,
DBG_BLOCK_ID_TCP9 = 0x69,
DBG_BLOCK_ID_TCP10 = 0x6a,
DBG_BLOCK_ID_TCP11 = 0x6b,
DBG_BLOCK_ID_TCP12 = 0x6c,
DBG_BLOCK_ID_TCP13 = 0x6d,
DBG_BLOCK_ID_TCP14 = 0x6e,
DBG_BLOCK_ID_TCP15 = 0x6f,
DBG_BLOCK_ID_TCP16 = 0x70,
DBG_BLOCK_ID_TCP17 = 0x71,
DBG_BLOCK_ID_TCP18 = 0x72,
DBG_BLOCK_ID_TCP19 = 0x73,
DBG_BLOCK_ID_TCP20 = 0x74,
DBG_BLOCK_ID_TCP21 = 0x75,
DBG_BLOCK_ID_TCP22 = 0x76,
DBG_BLOCK_ID_TCP23 = 0x77,
DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
DBG_BLOCK_ID_DB00 = 0x80,
DBG_BLOCK_ID_DB01 = 0x81,
DBG_BLOCK_ID_DB02 = 0x82,
DBG_BLOCK_ID_DB03 = 0x83,
DBG_BLOCK_ID_DB04 = 0x84,
DBG_BLOCK_ID_UNUSED27 = 0x85,
DBG_BLOCK_ID_UNUSED28 = 0x86,
DBG_BLOCK_ID_UNUSED29 = 0x87,
DBG_BLOCK_ID_DB10 = 0x88,
DBG_BLOCK_ID_DB11 = 0x89,
DBG_BLOCK_ID_DB12 = 0x8a,
DBG_BLOCK_ID_DB13 = 0x8b,
DBG_BLOCK_ID_DB14 = 0x8c,
DBG_BLOCK_ID_UNUSED30 = 0x8d,
DBG_BLOCK_ID_UNUSED31 = 0x8e,
DBG_BLOCK_ID_UNUSED32 = 0x8f,
DBG_BLOCK_ID_TCC0 = 0x90,
DBG_BLOCK_ID_TCC1 = 0x91,
DBG_BLOCK_ID_TCC2 = 0x92,
DBG_BLOCK_ID_TCC3 = 0x93,
DBG_BLOCK_ID_TCC4 = 0x94,
DBG_BLOCK_ID_TCC5 = 0x95,
DBG_BLOCK_ID_TCC6 = 0x96,
DBG_BLOCK_ID_TCC7 = 0x97,
DBG_BLOCK_ID_SPS00 = 0x98,
DBG_BLOCK_ID_SPS01 = 0x99,
DBG_BLOCK_ID_SPS02 = 0x9a,
DBG_BLOCK_ID_SPS10 = 0x9b,
DBG_BLOCK_ID_SPS11 = 0x9c,
DBG_BLOCK_ID_SPS12 = 0x9d,
DBG_BLOCK_ID_UNUSED33 = 0x9e,
DBG_BLOCK_ID_UNUSED34 = 0x9f,
DBG_BLOCK_ID_TA00 = 0xa0,
DBG_BLOCK_ID_TA01 = 0xa1,
DBG_BLOCK_ID_TA02 = 0xa2,
DBG_BLOCK_ID_TA03 = 0xa3,
DBG_BLOCK_ID_TA04 = 0xa4,
DBG_BLOCK_ID_TA05 = 0xa5,
DBG_BLOCK_ID_TA06 = 0xa6,
DBG_BLOCK_ID_TA07 = 0xa7,
DBG_BLOCK_ID_TA08 = 0xa8,
DBG_BLOCK_ID_TA09 = 0xa9,
DBG_BLOCK_ID_TA0A = 0xaa,
DBG_BLOCK_ID_TA0B = 0xab,
DBG_BLOCK_ID_UNUSED35 = 0xac,
DBG_BLOCK_ID_UNUSED36 = 0xad,
DBG_BLOCK_ID_UNUSED37 = 0xae,
DBG_BLOCK_ID_UNUSED38 = 0xaf,
DBG_BLOCK_ID_TA10 = 0xb0,
DBG_BLOCK_ID_TA11 = 0xb1,
DBG_BLOCK_ID_TA12 = 0xb2,
DBG_BLOCK_ID_TA13 = 0xb3,
DBG_BLOCK_ID_TA14 = 0xb4,
DBG_BLOCK_ID_TA15 = 0xb5,
DBG_BLOCK_ID_TA16 = 0xb6,
DBG_BLOCK_ID_TA17 = 0xb7,
DBG_BLOCK_ID_TA18 = 0xb8,
DBG_BLOCK_ID_TA19 = 0xb9,
DBG_BLOCK_ID_TA1A = 0xba,
DBG_BLOCK_ID_TA1B = 0xbb,
DBG_BLOCK_ID_UNUSED39 = 0xbc,
DBG_BLOCK_ID_UNUSED40 = 0xbd,
DBG_BLOCK_ID_UNUSED41 = 0xbe,
DBG_BLOCK_ID_UNUSED42 = 0xbf,
DBG_BLOCK_ID_TD00 = 0xc0,
DBG_BLOCK_ID_TD01 = 0xc1,
DBG_BLOCK_ID_TD02 = 0xc2,
DBG_BLOCK_ID_TD03 = 0xc3,
DBG_BLOCK_ID_TD04 = 0xc4,
DBG_BLOCK_ID_TD05 = 0xc5,
DBG_BLOCK_ID_TD06 = 0xc6,
DBG_BLOCK_ID_TD07 = 0xc7,
DBG_BLOCK_ID_TD08 = 0xc8,
DBG_BLOCK_ID_TD09 = 0xc9,
DBG_BLOCK_ID_TD0A = 0xca,
DBG_BLOCK_ID_TD0B = 0xcb,
DBG_BLOCK_ID_UNUSED43 = 0xcc,
DBG_BLOCK_ID_UNUSED44 = 0xcd,
DBG_BLOCK_ID_UNUSED45 = 0xce,
DBG_BLOCK_ID_UNUSED46 = 0xcf,
DBG_BLOCK_ID_TD10 = 0xd0,
DBG_BLOCK_ID_TD11 = 0xd1,
DBG_BLOCK_ID_TD12 = 0xd2,
DBG_BLOCK_ID_TD13 = 0xd3,
DBG_BLOCK_ID_TD14 = 0xd4,
DBG_BLOCK_ID_TD15 = 0xd5,
DBG_BLOCK_ID_TD16 = 0xd6,
DBG_BLOCK_ID_TD17 = 0xd7,
DBG_BLOCK_ID_TD18 = 0xd8,
DBG_BLOCK_ID_TD19 = 0xd9,
DBG_BLOCK_ID_TD1A = 0xda,
DBG_BLOCK_ID_TD1B = 0xdb,
DBG_BLOCK_ID_UNUSED47 = 0xdc,
DBG_BLOCK_ID_UNUSED48 = 0xdd,
DBG_BLOCK_ID_UNUSED49 = 0xde,
DBG_BLOCK_ID_UNUSED50 = 0xdf,
DBG_BLOCK_ID_MCD0 = 0xe0,
DBG_BLOCK_ID_MCD1 = 0xe1,
DBG_BLOCK_ID_MCD2 = 0xe2,
DBG_BLOCK_ID_MCD3 = 0xe3,
DBG_BLOCK_ID_MCD4 = 0xe4,
DBG_BLOCK_ID_MCD5 = 0xe5,
DBG_BLOCK_ID_UNUSED51 = 0xe6,
DBG_BLOCK_ID_UNUSED52 = 0xe7,
} DebugBlockId_OLD;
typedef enum DebugBlockId_BY2 {
DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
DBG_BLOCK_ID_VMC_BY2 = 0x1,
DBG_BLOCK_ID_CG_BY2 = 0x2,
DBG_BLOCK_ID_GRBM_BY2 = 0x3,
DBG_BLOCK_ID_CSC_BY2 = 0x4,
DBG_BLOCK_ID_IH_BY2 = 0x5,
DBG_BLOCK_ID_SQ_BY2 = 0x6,
DBG_BLOCK_ID_GMCON_BY2 = 0x7,
DBG_BLOCK_ID_DMA0_BY2 = 0x8,
DBG_BLOCK_ID_SPIM_BY2 = 0x9,
DBG_BLOCK_ID_SPIS_BY2 = 0xa,
DBG_BLOCK_ID_PA0_BY2 = 0xb,
DBG_BLOCK_ID_CP0_BY2 = 0xc,
DBG_BLOCK_ID_CP2_BY2 = 0xd,
DBG_BLOCK_ID_UVDU_BY2 = 0xe,
DBG_BLOCK_ID_VCE_BY2 = 0xf,
DBG_BLOCK_ID_VGT0_BY2 = 0x10,
DBG_BLOCK_ID_IA_BY2 = 0x11,
DBG_BLOCK_ID_SCT0_BY2 = 0x12,
DBG_BLOCK_ID_SPM0_BY2 = 0x13,
DBG_BLOCK_ID_TCAA_BY2 = 0x14,
DBG_BLOCK_ID_TCCA_BY2 = 0x15,
DBG_BLOCK_ID_MCC0_BY2 = 0x16,
DBG_BLOCK_ID_MCC2_BY2 = 0x17,
DBG_BLOCK_ID_SX0_BY2 = 0x18,
DBG_BLOCK_ID_SX2_BY2 = 0x19,
DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
DBG_BLOCK_ID_PC0_BY2 = 0x1c,
DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
DBG_BLOCK_ID_MCB_BY2 = 0x1f,
DBG_BLOCK_ID_SCB0_BY2 = 0x20,
DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
DBG_BLOCK_ID_SCF0_BY2 = 0x22,
DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
DBG_BLOCK_ID_BCI0_BY2 = 0x24,
DBG_BLOCK_ID_BCI2_BY2 = 0x25,
DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
DBG_BLOCK_ID_CB00_BY2 = 0x28,
DBG_BLOCK_ID_CB02_BY2 = 0x29,
DBG_BLOCK_ID_CB04_BY2 = 0x2a,
DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
DBG_BLOCK_ID_CB10_BY2 = 0x2c,
DBG_BLOCK_ID_CB12_BY2 = 0x2d,
DBG_BLOCK_ID_CB14_BY2 = 0x2e,
DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
DBG_BLOCK_ID_TCP0_BY2 = 0x30,
DBG_BLOCK_ID_TCP2_BY2 = 0x31,
DBG_BLOCK_ID_TCP4_BY2 = 0x32,
DBG_BLOCK_ID_TCP6_BY2 = 0x33,
DBG_BLOCK_ID_TCP8_BY2 = 0x34,
DBG_BLOCK_ID_TCP10_BY2 = 0x35,
DBG_BLOCK_ID_TCP12_BY2 = 0x36,
DBG_BLOCK_ID_TCP14_BY2 = 0x37,
DBG_BLOCK_ID_TCP16_BY2 = 0x38,
DBG_BLOCK_ID_TCP18_BY2 = 0x39,
DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
DBG_BLOCK_ID_DB00_BY2 = 0x40,
DBG_BLOCK_ID_DB02_BY2 = 0x41,
DBG_BLOCK_ID_DB04_BY2 = 0x42,
DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
DBG_BLOCK_ID_DB10_BY2 = 0x44,
DBG_BLOCK_ID_DB12_BY2 = 0x45,
DBG_BLOCK_ID_DB14_BY2 = 0x46,
DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
DBG_BLOCK_ID_TCC0_BY2 = 0x48,
DBG_BLOCK_ID_TCC2_BY2 = 0x49,
DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
DBG_BLOCK_ID_TA00_BY2 = 0x50,
DBG_BLOCK_ID_TA02_BY2 = 0x51,
DBG_BLOCK_ID_TA04_BY2 = 0x52,
DBG_BLOCK_ID_TA06_BY2 = 0x53,
DBG_BLOCK_ID_TA08_BY2 = 0x54,
DBG_BLOCK_ID_TA0A_BY2 = 0x55,
DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
DBG_BLOCK_ID_TA10_BY2 = 0x58,
DBG_BLOCK_ID_TA12_BY2 = 0x59,
DBG_BLOCK_ID_TA14_BY2 = 0x5a,
DBG_BLOCK_ID_TA16_BY2 = 0x5b,
DBG_BLOCK_ID_TA18_BY2 = 0x5c,
DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
DBG_BLOCK_ID_TD00_BY2 = 0x60,
DBG_BLOCK_ID_TD02_BY2 = 0x61,
DBG_BLOCK_ID_TD04_BY2 = 0x62,
DBG_BLOCK_ID_TD06_BY2 = 0x63,
DBG_BLOCK_ID_TD08_BY2 = 0x64,
DBG_BLOCK_ID_TD0A_BY2 = 0x65,
DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
DBG_BLOCK_ID_TD10_BY2 = 0x68,
DBG_BLOCK_ID_TD12_BY2 = 0x69,
DBG_BLOCK_ID_TD14_BY2 = 0x6a,
DBG_BLOCK_ID_TD16_BY2 = 0x6b,
DBG_BLOCK_ID_TD18_BY2 = 0x6c,
DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
DBG_BLOCK_ID_MCD0_BY2 = 0x70,
DBG_BLOCK_ID_MCD2_BY2 = 0x71,
DBG_BLOCK_ID_MCD4_BY2 = 0x72,
DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
} DebugBlockId_BY2;
typedef enum DebugBlockId_BY4 {
DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
DBG_BLOCK_ID_CG_BY4 = 0x1,
DBG_BLOCK_ID_CSC_BY4 = 0x2,
DBG_BLOCK_ID_SQ_BY4 = 0x3,
DBG_BLOCK_ID_DMA0_BY4 = 0x4,
DBG_BLOCK_ID_SPIS_BY4 = 0x5,
DBG_BLOCK_ID_CP0_BY4 = 0x6,
DBG_BLOCK_ID_UVDU_BY4 = 0x7,
DBG_BLOCK_ID_VGT0_BY4 = 0x8,
DBG_BLOCK_ID_SCT0_BY4 = 0x9,
DBG_BLOCK_ID_TCAA_BY4 = 0xa,
DBG_BLOCK_ID_MCC0_BY4 = 0xb,
DBG_BLOCK_ID_SX0_BY4 = 0xc,
DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
DBG_BLOCK_ID_PC0_BY4 = 0xe,
DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
DBG_BLOCK_ID_SCB0_BY4 = 0x10,
DBG_BLOCK_ID_SCF0_BY4 = 0x11,
DBG_BLOCK_ID_BCI0_BY4 = 0x12,
DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
DBG_BLOCK_ID_CB00_BY4 = 0x14,
DBG_BLOCK_ID_CB04_BY4 = 0x15,
DBG_BLOCK_ID_CB10_BY4 = 0x16,
DBG_BLOCK_ID_CB14_BY4 = 0x17,
DBG_BLOCK_ID_TCP0_BY4 = 0x18,
DBG_BLOCK_ID_TCP4_BY4 = 0x19,
DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
DBG_BLOCK_ID_DB_BY4 = 0x20,
DBG_BLOCK_ID_DB04_BY4 = 0x21,
DBG_BLOCK_ID_DB10_BY4 = 0x22,
DBG_BLOCK_ID_DB14_BY4 = 0x23,
DBG_BLOCK_ID_TCC0_BY4 = 0x24,
DBG_BLOCK_ID_TCC4_BY4 = 0x25,
DBG_BLOCK_ID_SPS00_BY4 = 0x26,
DBG_BLOCK_ID_SPS11_BY4 = 0x27,
DBG_BLOCK_ID_TA00_BY4 = 0x28,
DBG_BLOCK_ID_TA04_BY4 = 0x29,
DBG_BLOCK_ID_TA08_BY4 = 0x2a,
DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
DBG_BLOCK_ID_TA10_BY4 = 0x2c,
DBG_BLOCK_ID_TA14_BY4 = 0x2d,
DBG_BLOCK_ID_TA18_BY4 = 0x2e,
DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
DBG_BLOCK_ID_TD00_BY4 = 0x30,
DBG_BLOCK_ID_TD04_BY4 = 0x31,
DBG_BLOCK_ID_TD08_BY4 = 0x32,
DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
DBG_BLOCK_ID_TD10_BY4 = 0x34,
DBG_BLOCK_ID_TD14_BY4 = 0x35,
DBG_BLOCK_ID_TD18_BY4 = 0x36,
DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
DBG_BLOCK_ID_MCD0_BY4 = 0x38,
DBG_BLOCK_ID_MCD4_BY4 = 0x39,
} DebugBlockId_BY4;
typedef enum DebugBlockId_BY8 {
DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
DBG_BLOCK_ID_CSC_BY8 = 0x1,
DBG_BLOCK_ID_DMA0_BY8 = 0x2,
DBG_BLOCK_ID_CP0_BY8 = 0x3,
DBG_BLOCK_ID_VGT0_BY8 = 0x4,
DBG_BLOCK_ID_TCAA_BY8 = 0x5,
DBG_BLOCK_ID_SX0_BY8 = 0x6,
DBG_BLOCK_ID_PC0_BY8 = 0x7,
DBG_BLOCK_ID_SCB0_BY8 = 0x8,
DBG_BLOCK_ID_BCI0_BY8 = 0x9,
DBG_BLOCK_ID_CB00_BY8 = 0xa,
DBG_BLOCK_ID_CB10_BY8 = 0xb,
DBG_BLOCK_ID_TCP0_BY8 = 0xc,
DBG_BLOCK_ID_TCP8_BY8 = 0xd,
DBG_BLOCK_ID_TCP16_BY8 = 0xe,
DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
DBG_BLOCK_ID_DB00_BY8 = 0x10,
DBG_BLOCK_ID_DB10_BY8 = 0x11,
DBG_BLOCK_ID_TCC0_BY8 = 0x12,
DBG_BLOCK_ID_SPS00_BY8 = 0x13,
DBG_BLOCK_ID_TA00_BY8 = 0x14,
DBG_BLOCK_ID_TA08_BY8 = 0x15,
DBG_BLOCK_ID_TA10_BY8 = 0x16,
DBG_BLOCK_ID_TA18_BY8 = 0x17,
DBG_BLOCK_ID_TD00_BY8 = 0x18,
DBG_BLOCK_ID_TD08_BY8 = 0x19,
DBG_BLOCK_ID_TD10_BY8 = 0x1a,
DBG_BLOCK_ID_TD18_BY8 = 0x1b,
DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
} DebugBlockId_BY8;
typedef enum DebugBlockId_BY16 {
DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
DBG_BLOCK_ID_DMA0_BY16 = 0x1,
DBG_BLOCK_ID_VGT0_BY16 = 0x2,
DBG_BLOCK_ID_SX0_BY16 = 0x3,
DBG_BLOCK_ID_SCB0_BY16 = 0x4,
DBG_BLOCK_ID_CB00_BY16 = 0x5,
DBG_BLOCK_ID_TCP0_BY16 = 0x6,
DBG_BLOCK_ID_TCP16_BY16 = 0x7,
DBG_BLOCK_ID_DB00_BY16 = 0x8,
DBG_BLOCK_ID_TCC0_BY16 = 0x9,
DBG_BLOCK_ID_TA00_BY16 = 0xa,
DBG_BLOCK_ID_TA10_BY16 = 0xb,
DBG_BLOCK_ID_TD00_BY16 = 0xc,
DBG_BLOCK_ID_TD10_BY16 = 0xd,
DBG_BLOCK_ID_MCD0_BY16 = 0xe,
} DebugBlockId_BY16;
typedef enum ColorTransform {
DCC_CT_AUTO = 0x0,
DCC_CT_NONE = 0x1,
ABGR_TO_A_BG_G_RB = 0x2,
BGRA_TO_BG_G_RB_A = 0x3,
} ColorTransform;
typedef enum CompareRef {
REF_NEVER = 0x0,
REF_LESS = 0x1,
REF_EQUAL = 0x2,
REF_LEQUAL = 0x3,
REF_GREATER = 0x4,
REF_NOTEQUAL = 0x5,
REF_GEQUAL = 0x6,
REF_ALWAYS = 0x7,
} CompareRef;
typedef enum ReadSize {
READ_256_BITS = 0x0,
READ_512_BITS = 0x1,
} ReadSize;
typedef enum DepthFormat {
DEPTH_INVALID = 0x0,
DEPTH_16 = 0x1,
DEPTH_X8_24 = 0x2,
DEPTH_8_24 = 0x3,
DEPTH_X8_24_FLOAT = 0x4,
DEPTH_8_24_FLOAT = 0x5,
DEPTH_32_FLOAT = 0x6,
DEPTH_X24_8_32_FLOAT = 0x7,
} DepthFormat;
typedef enum ZFormat {
Z_INVALID = 0x0,
Z_16 = 0x1,
Z_24 = 0x2,
Z_32_FLOAT = 0x3,
} ZFormat;
typedef enum StencilFormat {
STENCIL_INVALID = 0x0,
STENCIL_8 = 0x1,
} StencilFormat;
typedef enum CmaskMode {
CMASK_CLEAR_NONE = 0x0,
CMASK_CLEAR_ONE = 0x1,
CMASK_CLEAR_ALL = 0x2,
CMASK_ANY_EXPANDED = 0x3,
CMASK_ALPHA0_FRAG1 = 0x4,
CMASK_ALPHA0_FRAG2 = 0x5,
CMASK_ALPHA0_FRAG4 = 0x6,
CMASK_ALPHA0_FRAGS = 0x7,
CMASK_ALPHA1_FRAG1 = 0x8,
CMASK_ALPHA1_FRAG2 = 0x9,
CMASK_ALPHA1_FRAG4 = 0xa,
CMASK_ALPHA1_FRAGS = 0xb,
CMASK_ALPHAX_FRAG1 = 0xc,
CMASK_ALPHAX_FRAG2 = 0xd,
CMASK_ALPHAX_FRAG4 = 0xe,
CMASK_ALPHAX_FRAGS = 0xf,
} CmaskMode;
typedef enum QuadExportFormat {
EXPORT_UNUSED = 0x0,
EXPORT_32_R = 0x1,
EXPORT_32_GR = 0x2,
EXPORT_32_AR = 0x3,
EXPORT_FP16_ABGR = 0x4,
EXPORT_UNSIGNED16_ABGR = 0x5,
EXPORT_SIGNED16_ABGR = 0x6,
EXPORT_32_ABGR = 0x7,
} QuadExportFormat;
typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR = 0x0,
EXPORT_4P_16BPC_ABGR = 0x1,
EXPORT_4P_32BPC_GR = 0x2,
EXPORT_4P_32BPC_AR = 0x3,
EXPORT_2P_32BPC_ABGR = 0x4,
EXPORT_8P_32BPC_R = 0x5,
} QuadExportFormatOld;
typedef enum ColorFormat {
COLOR_INVALID = 0x0,
COLOR_8 = 0x1,
COLOR_16 = 0x2,
COLOR_8_8 = 0x3,
COLOR_32 = 0x4,
COLOR_16_16 = 0x5,
COLOR_10_11_11 = 0x6,
COLOR_11_11_10 = 0x7,
COLOR_10_10_10_2 = 0x8,
COLOR_2_10_10_10 = 0x9,
COLOR_8_8_8_8 = 0xa,
COLOR_32_32 = 0xb,
COLOR_16_16_16_16 = 0xc,
COLOR_RESERVED_13 = 0xd,
COLOR_32_32_32_32 = 0xe,
COLOR_RESERVED_15 = 0xf,
COLOR_5_6_5 = 0x10,
COLOR_1_5_5_5 = 0x11,
COLOR_5_5_5_1 = 0x12,
COLOR_4_4_4_4 = 0x13,
COLOR_8_24 = 0x14,
COLOR_24_8 = 0x15,
COLOR_X24_8_32_FLOAT = 0x16,
COLOR_RESERVED_23 = 0x17,
} ColorFormat;
typedef enum SurfaceFormat {
FMT_INVALID = 0x0,
FMT_8 = 0x1,
FMT_16 = 0x2,
FMT_8_8 = 0x3,
FMT_32 = 0x4,
FMT_16_16 = 0x5,
FMT_10_11_11 = 0x6,
FMT_11_11_10 = 0x7,
FMT_10_10_10_2 = 0x8,
FMT_2_10_10_10 = 0x9,
FMT_8_8_8_8 = 0xa,
FMT_32_32 = 0xb,
FMT_16_16_16_16 = 0xc,
FMT_32_32_32 = 0xd,
FMT_32_32_32_32 = 0xe,
FMT_RESERVED_4 = 0xf,
FMT_5_6_5 = 0x10,
FMT_1_5_5_5 = 0x11,
FMT_5_5_5_1 = 0x12,
FMT_4_4_4_4 = 0x13,
FMT_8_24 = 0x14,
FMT_24_8 = 0x15,
FMT_X24_8_32_FLOAT = 0x16,
FMT_RESERVED_33 = 0x17,
FMT_11_11_10_FLOAT = 0x18,
FMT_16_FLOAT = 0x19,
FMT_32_FLOAT = 0x1a,
FMT_16_16_FLOAT = 0x1b,
FMT_8_24_FLOAT = 0x1c,
FMT_24_8_FLOAT = 0x1d,
FMT_32_32_FLOAT = 0x1e,
FMT_10_11_11_FLOAT = 0x1f,
FMT_16_16_16_16_FLOAT = 0x20,
FMT_3_3_2 = 0x21,
FMT_6_5_5 = 0x22,
FMT_32_32_32_32_FLOAT = 0x23,
FMT_RESERVED_36 = 0x24,
FMT_1 = 0x25,
FMT_1_REVERSED = 0x26,
FMT_GB_GR = 0x27,
FMT_BG_RG = 0x28,
FMT_32_AS_8 = 0x29,
FMT_32_AS_8_8 = 0x2a,
FMT_5_9_9_9_SHAREDEXP = 0x2b,
FMT_8_8_8 = 0x2c,
FMT_16_16_16 = 0x2d,
FMT_16_16_16_FLOAT = 0x2e,
FMT_4_4 = 0x2f,
FMT_32_32_32_FLOAT = 0x30,
FMT_BC1 = 0x31,
FMT_BC2 = 0x32,
FMT_BC3 = 0x33,
FMT_BC4 = 0x34,
FMT_BC5 = 0x35,
FMT_BC6 = 0x36,
FMT_BC7 = 0x37,
FMT_32_AS_32_32_32_32 = 0x38,
FMT_APC3 = 0x39,
FMT_APC4 = 0x3a,
FMT_APC5 = 0x3b,
FMT_APC6 = 0x3c,
FMT_APC7 = 0x3d,
FMT_CTX1 = 0x3e,
FMT_RESERVED_63 = 0x3f,
} SurfaceFormat;
typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID = 0x0,
BUF_DATA_FORMAT_8 = 0x1,
BUF_DATA_FORMAT_16 = 0x2,
BUF_DATA_FORMAT_8_8 = 0x3,
BUF_DATA_FORMAT_32 = 0x4,
BUF_DATA_FORMAT_16_16 = 0x5,
BUF_DATA_FORMAT_10_11_11 = 0x6,
BUF_DATA_FORMAT_11_11_10 = 0x7,
BUF_DATA_FORMAT_10_10_10_2 = 0x8,
BUF_DATA_FORMAT_2_10_10_10 = 0x9,
BUF_DATA_FORMAT_8_8_8_8 = 0xa,
BUF_DATA_FORMAT_32_32 = 0xb,
BUF_DATA_FORMAT_16_16_16_16 = 0xc,
BUF_DATA_FORMAT_32_32_32 = 0xd,
BUF_DATA_FORMAT_32_32_32_32 = 0xe,
BUF_DATA_FORMAT_RESERVED_15 = 0xf,
} BUF_DATA_FORMAT;
typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID = 0x0,
IMG_DATA_FORMAT_8 = 0x1,
IMG_DATA_FORMAT_16 = 0x2,
IMG_DATA_FORMAT_8_8 = 0x3,
IMG_DATA_FORMAT_32 = 0x4,
IMG_DATA_FORMAT_16_16 = 0x5,
IMG_DATA_FORMAT_10_11_11 = 0x6,
IMG_DATA_FORMAT_11_11_10 = 0x7,
IMG_DATA_FORMAT_10_10_10_2 = 0x8,
IMG_DATA_FORMAT_2_10_10_10 = 0x9,
IMG_DATA_FORMAT_8_8_8_8 = 0xa,
IMG_DATA_FORMAT_32_32 = 0xb,
IMG_DATA_FORMAT_16_16_16_16 = 0xc,
IMG_DATA_FORMAT_32_32_32 = 0xd,
IMG_DATA_FORMAT_32_32_32_32 = 0xe,
IMG_DATA_FORMAT_RESERVED_15 = 0xf,
IMG_DATA_FORMAT_5_6_5 = 0x10,
IMG_DATA_FORMAT_1_5_5_5 = 0x11,
IMG_DATA_FORMAT_5_5_5_1 = 0x12,
IMG_DATA_FORMAT_4_4_4_4 = 0x13,
IMG_DATA_FORMAT_8_24 = 0x14,
IMG_DATA_FORMAT_24_8 = 0x15,
IMG_DATA_FORMAT_X24_8_32 = 0x16,
IMG_DATA_FORMAT_RESERVED_23 = 0x17,
IMG_DATA_FORMAT_RESERVED_24 = 0x18,
IMG_DATA_FORMAT_RESERVED_25 = 0x19,
IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
IMG_DATA_FORMAT_GB_GR = 0x20,
IMG_DATA_FORMAT_BG_RG = 0x21,
IMG_DATA_FORMAT_5_9_9_9 = 0x22,
IMG_DATA_FORMAT_BC1 = 0x23,
IMG_DATA_FORMAT_BC2 = 0x24,
IMG_DATA_FORMAT_BC3 = 0x25,
IMG_DATA_FORMAT_BC4 = 0x26,
IMG_DATA_FORMAT_BC5 = 0x27,
IMG_DATA_FORMAT_BC6 = 0x28,
IMG_DATA_FORMAT_BC7 = 0x29,
IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
IMG_DATA_FORMAT_4_4 = 0x39,
IMG_DATA_FORMAT_6_5_5 = 0x3a,
IMG_DATA_FORMAT_1 = 0x3b,
IMG_DATA_FORMAT_1_REVERSED = 0x3c,
IMG_DATA_FORMAT_32_AS_8 = 0x3d,
IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
} IMG_DATA_FORMAT;
typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM = 0x0,
BUF_NUM_FORMAT_SNORM = 0x1,
BUF_NUM_FORMAT_USCALED = 0x2,
BUF_NUM_FORMAT_SSCALED = 0x3,
BUF_NUM_FORMAT_UINT = 0x4,
BUF_NUM_FORMAT_SINT = 0x5,
BUF_NUM_FORMAT_RESERVED_6 = 0x6,
BUF_NUM_FORMAT_FLOAT = 0x7,
} BUF_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM = 0x0,
IMG_NUM_FORMAT_SNORM = 0x1,
IMG_NUM_FORMAT_USCALED = 0x2,
IMG_NUM_FORMAT_SSCALED = 0x3,
IMG_NUM_FORMAT_UINT = 0x4,
IMG_NUM_FORMAT_SINT = 0x5,
IMG_NUM_FORMAT_RESERVED_6 = 0x6,
IMG_NUM_FORMAT_FLOAT = 0x7,
IMG_NUM_FORMAT_RESERVED_8 = 0x8,
IMG_NUM_FORMAT_SRGB = 0x9,
IMG_NUM_FORMAT_RESERVED_10 = 0xa,
IMG_NUM_FORMAT_RESERVED_11 = 0xb,
IMG_NUM_FORMAT_RESERVED_12 = 0xc,
IMG_NUM_FORMAT_RESERVED_13 = 0xd,
IMG_NUM_FORMAT_RESERVED_14 = 0xe,
IMG_NUM_FORMAT_RESERVED_15 = 0xf,
} IMG_NUM_FORMAT;
typedef enum TileType {
ARRAY_COLOR_TILE = 0x0,
ARRAY_DEPTH_TILE = 0x1,
} TileType;
typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
} NonDispTilingOrder;
typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
ADDR_SURF_THIN_MICRO_TILING = 0x1,
ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
ADDR_SURF_THICK_MICRO_TILING = 0x4,
} MicroTileMode;
typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B = 0x0,
ADDR_SURF_TILE_SPLIT_128B = 0x1,
ADDR_SURF_TILE_SPLIT_256B = 0x2,
ADDR_SURF_TILE_SPLIT_512B = 0x3,
ADDR_SURF_TILE_SPLIT_1KB = 0x4,
ADDR_SURF_TILE_SPLIT_2KB = 0x5,
ADDR_SURF_TILE_SPLIT_4KB = 0x6,
} TileSplit;
typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
} SampleSplit;
typedef enum PipeConfig {
ADDR_SURF_P2 = 0x0,
ADDR_SURF_P2_RESERVED0 = 0x1,
ADDR_SURF_P2_RESERVED1 = 0x2,
ADDR_SURF_P2_RESERVED2 = 0x3,
ADDR_SURF_P4_8x16 = 0x4,
ADDR_SURF_P4_16x16 = 0x5,
ADDR_SURF_P4_16x32 = 0x6,
ADDR_SURF_P4_32x32 = 0x7,
ADDR_SURF_P8_16x16_8x16 = 0x8,
ADDR_SURF_P8_16x32_8x16 = 0x9,
ADDR_SURF_P8_32x32_8x16 = 0xa,
ADDR_SURF_P8_16x32_16x16 = 0xb,
ADDR_SURF_P8_32x32_16x16 = 0xc,
ADDR_SURF_P8_32x32_16x32 = 0xd,
ADDR_SURF_P8_32x64_32x32 = 0xe,
ADDR_SURF_P8_RESERVED0 = 0xf,
ADDR_SURF_P16_32x32_8x16 = 0x10,
ADDR_SURF_P16_32x32_16x16 = 0x11,
} PipeConfig;
typedef enum NumBanks {
ADDR_SURF_2_BANK = 0x0,
ADDR_SURF_4_BANK = 0x1,
ADDR_SURF_8_BANK = 0x2,
ADDR_SURF_16_BANK = 0x3,
} NumBanks;
typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1 = 0x0,
ADDR_SURF_BANK_WIDTH_2 = 0x1,
ADDR_SURF_BANK_WIDTH_4 = 0x2,
ADDR_SURF_BANK_WIDTH_8 = 0x3,
} BankWidth;
typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1 = 0x0,
ADDR_SURF_BANK_HEIGHT_2 = 0x1,
ADDR_SURF_BANK_HEIGHT_4 = 0x2,
ADDR_SURF_BANK_HEIGHT_8 = 0x3,
} BankHeight;
typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1 = 0x0,
ADDR_SURF_BANK_WH_2 = 0x1,
ADDR_SURF_BANK_WH_4 = 0x2,
ADDR_SURF_BANK_WH_8 = 0x3,
} BankWidthHeight;
typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1 = 0x0,
ADDR_SURF_MACRO_ASPECT_2 = 0x1,
ADDR_SURF_MACRO_ASPECT_4 = 0x2,
ADDR_SURF_MACRO_ASPECT_8 = 0x3,
} MacroTileAspect;
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x0,
GATCL1_TYPE_SHOOTDOWN = 0x1,
GATCL1_TYPE_BYPASS = 0x2,
} GATCL1RequestType;
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x0,
TCC_CACHE_POLICY_STREAM = 0x1,
} TCC_CACHE_POLICIES;
typedef enum MTYPE {
MTYPE_NC_NV = 0x0,
MTYPE_NC = 0x1,
MTYPE_CC = 0x2,
MTYPE_UC = 0x3,
} MTYPE;
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x0,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
PERFMON_COUNTER_MODE_MAX = 0x2,
PERFMON_COUNTER_MODE_DIRTY = 0x3,
PERFMON_COUNTER_MODE_SAMPLE = 0x4,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
PERFMON_COUNTER_MODE_RESERVED = 0xf,
} PERFMON_COUNTER_MODE;
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x0,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
PERFMON_SPM_MODE_RESERVED_5 = 0x5,
PERFMON_SPM_MODE_RESERVED_6 = 0x6,
PERFMON_SPM_MODE_RESERVED_7 = 0x7,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
} PERFMON_SPM_MODE;
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x0,
ARRAY_TILED = 0x1,
} SurfaceTiling;
typedef enum SurfaceArray {
ARRAY_1D = 0x0,
ARRAY_2D = 0x1,
ARRAY_3D = 0x2,
ARRAY_3D_SLICE = 0x3,
} SurfaceArray;
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x0,
ARRAY_2D_COLOR = 0x1,
ARRAY_3D_SLICE_COLOR = 0x3,
} ColorArray;
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x0,
ARRAY_2D_DEPTH = 0x1,
} DepthArray;
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x4,
} ENUM_NUM_SIMD_PER_CU;
typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST = 0x0,
FORCE_LIGHT_SLEEP_REQUEST = 0x1,
FORCE_DEEP_SLEEP_REQUEST = 0x2,
FORCE_SHUT_DOWN_REQUEST = 0x3,
} MEM_PWR_FORCE_CTRL;
typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ = 0x0,
FORCE_LIGHT_SLEEP_REQ = 0x1,
} MEM_PWR_FORCE_CTRL2;
typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL = 0x0,
DISABLE_MEM_PWR_CTRL = 0x1,
} MEM_PWR_DIS_CTRL;
typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
} MEM_PWR_SEL_CTRL;
typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN = 0x0,
DYNAMIC_LIGHT_SLEEP_EN = 0x1,
} MEM_PWR_SEL_CTRL2;
#endif /* BIF_5_0_ENUM_H */
drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h 0 → 100644
View file @ 848ebfd7
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