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Commit 85ed41a7 authored by Viresh Kumar's avatar Viresh Kumar Committed by Arnd Bergmann
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pinctrl: Add SPEAr13xx pinctrl drivers 

This adds pinctrl driver for SPEAr13xx family. SPEAr13xx family supports two
machines: SPEAr1310 and SPEAr1340.
Signed-off-by: default avatarViresh Kumar <viresh.kumar@st.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d1e77afe
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Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
View file @ 85ed41a7
......@@ -4,6 +4,8 @@ Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
: "st,spear1310-pinmux"
: "st,spear1340-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
- Its values for SPEAr300:
......@@ -89,6 +91,37 @@ For SPEAr320 machines:
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
For SPEAr1310 machines:
"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
For SPEAr1340 machines:
"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
"miphy_dbg_grp", "pcie_grp", "sata_grp"
Valid values for function names are:
For All SPEAr3xx machines:
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
......@@ -106,3 +139,17 @@ For SPEAr320 machines:
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
"mii0_1", "i2c1", "i2c2"
For SPEAr1310 machines:
"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
For SPEAr1340 machines:
"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
arch/arm/mach-spear13xx/Kconfig
View file @ 85ed41a7
......@@ -7,11 +7,13 @@ if ARCH_SPEAR13XX
menu "SPEAr13xx Implementations"
config MACH_SPEAR1310
bool "SPEAr1310 Machine support with Device Tree"
select PINCTRL_SPEAR1310
help
Supports ST SPEAr1310 machine configured via the device-tree
config MACH_SPEAR1340
bool "SPEAr1340 Machine support with Device Tree"
select PINCTRL_SPEAR1340
help
Supports ST SPEAr1340 machine configured via the device-tree
endmenu
......
drivers/pinctrl/spear/Kconfig
View file @ 85ed41a7
......@@ -31,4 +31,14 @@ config PINCTRL_SPEAR320
depends on MACH_SPEAR320
select PINCTRL_SPEAR3XX
config PINCTRL_SPEAR1310
bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
depends on MACH_SPEAR1310
select PINCTRL_SPEAR
config PINCTRL_SPEAR1340
bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
depends on MACH_SPEAR1340
select PINCTRL_SPEAR
endif
drivers/pinctrl/spear/Makefile
View file @ 85ed41a7
......@@ -5,3 +5,5 @@ obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
obj-$(CONFIG_PINCTRL_SPEAR1310) += pinctrl-spear1310.o
obj-$(CONFIG_PINCTRL_SPEAR1340) += pinctrl-spear1340.o
drivers/pinctrl/spear/pinctrl-spear.h
View file @ 85ed41a7
......@@ -244,4 +244,150 @@ int __devexit spear_pinctrl_remove(struct platform_device *pdev);
PINCTRL_PIN(100, "PLGPIO100"), \
PINCTRL_PIN(101, "PLGPIO101")
#define SPEAR_PIN_102_TO_245 \
PINCTRL_PIN(102, "PLGPIO102"), \
PINCTRL_PIN(103, "PLGPIO103"), \
PINCTRL_PIN(104, "PLGPIO104"), \
PINCTRL_PIN(105, "PLGPIO105"), \
PINCTRL_PIN(106, "PLGPIO106"), \
PINCTRL_PIN(107, "PLGPIO107"), \
PINCTRL_PIN(108, "PLGPIO108"), \
PINCTRL_PIN(109, "PLGPIO109"), \
PINCTRL_PIN(110, "PLGPIO110"), \
PINCTRL_PIN(111, "PLGPIO111"), \
PINCTRL_PIN(112, "PLGPIO112"), \
PINCTRL_PIN(113, "PLGPIO113"), \
PINCTRL_PIN(114, "PLGPIO114"), \
PINCTRL_PIN(115, "PLGPIO115"), \
PINCTRL_PIN(116, "PLGPIO116"), \
PINCTRL_PIN(117, "PLGPIO117"), \
PINCTRL_PIN(118, "PLGPIO118"), \
PINCTRL_PIN(119, "PLGPIO119"), \
PINCTRL_PIN(120, "PLGPIO120"), \
PINCTRL_PIN(121, "PLGPIO121"), \
PINCTRL_PIN(122, "PLGPIO122"), \
PINCTRL_PIN(123, "PLGPIO123"), \
PINCTRL_PIN(124, "PLGPIO124"), \
PINCTRL_PIN(125, "PLGPIO125"), \
PINCTRL_PIN(126, "PLGPIO126"), \
PINCTRL_PIN(127, "PLGPIO127"), \
PINCTRL_PIN(128, "PLGPIO128"), \
PINCTRL_PIN(129, "PLGPIO129"), \
PINCTRL_PIN(130, "PLGPIO130"), \
PINCTRL_PIN(131, "PLGPIO131"), \
PINCTRL_PIN(132, "PLGPIO132"), \
PINCTRL_PIN(133, "PLGPIO133"), \
PINCTRL_PIN(134, "PLGPIO134"), \
PINCTRL_PIN(135, "PLGPIO135"), \
PINCTRL_PIN(136, "PLGPIO136"), \
PINCTRL_PIN(137, "PLGPIO137"), \
PINCTRL_PIN(138, "PLGPIO138"), \
PINCTRL_PIN(139, "PLGPIO139"), \
PINCTRL_PIN(140, "PLGPIO140"), \
PINCTRL_PIN(141, "PLGPIO141"), \
PINCTRL_PIN(142, "PLGPIO142"), \
PINCTRL_PIN(143, "PLGPIO143"), \
PINCTRL_PIN(144, "PLGPIO144"), \
PINCTRL_PIN(145, "PLGPIO145"), \
PINCTRL_PIN(146, "PLGPIO146"), \
PINCTRL_PIN(147, "PLGPIO147"), \
PINCTRL_PIN(148, "PLGPIO148"), \
PINCTRL_PIN(149, "PLGPIO149"), \
PINCTRL_PIN(150, "PLGPIO150"), \
PINCTRL_PIN(151, "PLGPIO151"), \
PINCTRL_PIN(152, "PLGPIO152"), \
PINCTRL_PIN(153, "PLGPIO153"), \
PINCTRL_PIN(154, "PLGPIO154"), \
PINCTRL_PIN(155, "PLGPIO155"), \
PINCTRL_PIN(156, "PLGPIO156"), \
PINCTRL_PIN(157, "PLGPIO157"), \
PINCTRL_PIN(158, "PLGPIO158"), \
PINCTRL_PIN(159, "PLGPIO159"), \
PINCTRL_PIN(160, "PLGPIO160"), \
PINCTRL_PIN(161, "PLGPIO161"), \
PINCTRL_PIN(162, "PLGPIO162"), \
PINCTRL_PIN(163, "PLGPIO163"), \
PINCTRL_PIN(164, "PLGPIO164"), \
PINCTRL_PIN(165, "PLGPIO165"), \
PINCTRL_PIN(166, "PLGPIO166"), \
PINCTRL_PIN(167, "PLGPIO167"), \
PINCTRL_PIN(168, "PLGPIO168"), \
PINCTRL_PIN(169, "PLGPIO169"), \
PINCTRL_PIN(170, "PLGPIO170"), \
PINCTRL_PIN(171, "PLGPIO171"), \
PINCTRL_PIN(172, "PLGPIO172"), \
PINCTRL_PIN(173, "PLGPIO173"), \
PINCTRL_PIN(174, "PLGPIO174"), \
PINCTRL_PIN(175, "PLGPIO175"), \
PINCTRL_PIN(176, "PLGPIO176"), \
PINCTRL_PIN(177, "PLGPIO177"), \
PINCTRL_PIN(178, "PLGPIO178"), \
PINCTRL_PIN(179, "PLGPIO179"), \
PINCTRL_PIN(180, "PLGPIO180"), \
PINCTRL_PIN(181, "PLGPIO181"), \
PINCTRL_PIN(182, "PLGPIO182"), \
PINCTRL_PIN(183, "PLGPIO183"), \
PINCTRL_PIN(184, "PLGPIO184"), \
PINCTRL_PIN(185, "PLGPIO185"), \
PINCTRL_PIN(186, "PLGPIO186"), \
PINCTRL_PIN(187, "PLGPIO187"), \
PINCTRL_PIN(188, "PLGPIO188"), \
PINCTRL_PIN(189, "PLGPIO189"), \
PINCTRL_PIN(190, "PLGPIO190"), \
PINCTRL_PIN(191, "PLGPIO191"), \
PINCTRL_PIN(192, "PLGPIO192"), \
PINCTRL_PIN(193, "PLGPIO193"), \
PINCTRL_PIN(194, "PLGPIO194"), \
PINCTRL_PIN(195, "PLGPIO195"), \
PINCTRL_PIN(196, "PLGPIO196"), \
PINCTRL_PIN(197, "PLGPIO197"), \
PINCTRL_PIN(198, "PLGPIO198"), \
PINCTRL_PIN(199, "PLGPIO199"), \
PINCTRL_PIN(200, "PLGPIO200"), \
PINCTRL_PIN(201, "PLGPIO201"), \
PINCTRL_PIN(202, "PLGPIO202"), \
PINCTRL_PIN(203, "PLGPIO203"), \
PINCTRL_PIN(204, "PLGPIO204"), \
PINCTRL_PIN(205, "PLGPIO205"), \
PINCTRL_PIN(206, "PLGPIO206"), \
PINCTRL_PIN(207, "PLGPIO207"), \
PINCTRL_PIN(208, "PLGPIO208"), \
PINCTRL_PIN(209, "PLGPIO209"), \
PINCTRL_PIN(210, "PLGPIO210"), \
PINCTRL_PIN(211, "PLGPIO211"), \
PINCTRL_PIN(212, "PLGPIO212"), \
PINCTRL_PIN(213, "PLGPIO213"), \
PINCTRL_PIN(214, "PLGPIO214"), \
PINCTRL_PIN(215, "PLGPIO215"), \
PINCTRL_PIN(216, "PLGPIO216"), \
PINCTRL_PIN(217, "PLGPIO217"), \
PINCTRL_PIN(218, "PLGPIO218"), \
PINCTRL_PIN(219, "PLGPIO219"), \
PINCTRL_PIN(220, "PLGPIO220"), \
PINCTRL_PIN(221, "PLGPIO221"), \
PINCTRL_PIN(222, "PLGPIO222"), \
PINCTRL_PIN(223, "PLGPIO223"), \
PINCTRL_PIN(224, "PLGPIO224"), \
PINCTRL_PIN(225, "PLGPIO225"), \
PINCTRL_PIN(226, "PLGPIO226"), \
PINCTRL_PIN(227, "PLGPIO227"), \
PINCTRL_PIN(228, "PLGPIO228"), \
PINCTRL_PIN(229, "PLGPIO229"), \
PINCTRL_PIN(230, "PLGPIO230"), \
PINCTRL_PIN(231, "PLGPIO231"), \
PINCTRL_PIN(232, "PLGPIO232"), \
PINCTRL_PIN(233, "PLGPIO233"), \
PINCTRL_PIN(234, "PLGPIO234"), \
PINCTRL_PIN(235, "PLGPIO235"), \
PINCTRL_PIN(236, "PLGPIO236"), \
PINCTRL_PIN(237, "PLGPIO237"), \
PINCTRL_PIN(238, "PLGPIO238"), \
PINCTRL_PIN(239, "PLGPIO239"), \
PINCTRL_PIN(240, "PLGPIO240"), \
PINCTRL_PIN(241, "PLGPIO241"), \
PINCTRL_PIN(242, "PLGPIO242"), \
PINCTRL_PIN(243, "PLGPIO243"), \
PINCTRL_PIN(244, "PLGPIO244"), \
PINCTRL_PIN(245, "PLGPIO245")
#endif /* __PINMUX_SPEAR_H__ */
drivers/pinctrl/spear/pinctrl-spear1310.c 0 → 100644
View file @ 85ed41a7
/*
* Driver for the ST Microelectronics SPEAr1310 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear1310-pinmux"
/* pins */
static const struct pinctrl_pin_desc spear1310_pins[] = {
SPEAR_PIN_0_TO_101,
SPEAR_PIN_102_TO_245,
};
/* registers */
#define PERIP_CFG 0x32C
#define MCIF_SEL_SHIFT 3
#define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
#define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
#define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
#define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
#define PCIE_SATA_CFG 0x3A4
#define PCIE_SATA2_SEL_PCIE (0 << 31)
#define PCIE_SATA1_SEL_PCIE (0 << 30)
#define PCIE_SATA0_SEL_PCIE (0 << 29)
#define PCIE_SATA2_SEL_SATA (1 << 31)
#define PCIE_SATA1_SEL_SATA (1 << 30)
#define PCIE_SATA0_SEL_SATA (1 << 29)
#define SATA2_CFG_TX_CLK_EN (1 << 27)
#define SATA2_CFG_RX_CLK_EN (1 << 26)
#define SATA2_CFG_POWERUP_RESET (1 << 25)
#define SATA2_CFG_PM_CLK_EN (1 << 24)
#define SATA1_CFG_TX_CLK_EN (1 << 23)
#define SATA1_CFG_RX_CLK_EN (1 << 22)
#define SATA1_CFG_POWERUP_RESET (1 << 21)
#define SATA1_CFG_PM_CLK_EN (1 << 20)
#define SATA0_CFG_TX_CLK_EN (1 << 19)
#define SATA0_CFG_RX_CLK_EN (1 << 18)
#define SATA0_CFG_POWERUP_RESET (1 << 17)
#define SATA0_CFG_PM_CLK_EN (1 << 16)
#define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
#define PCIE2_CFG_POWERUP_RESET (1 << 10)
#define PCIE2_CFG_CORE_CLK_EN (1 << 9)
#define PCIE2_CFG_AUX_CLK_EN (1 << 8)
#define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
#define PCIE1_CFG_POWERUP_RESET (1 << 6)
#define PCIE1_CFG_CORE_CLK_EN (1 << 5)
#define PCIE1_CFG_AUX_CLK_EN (1 << 4)
#define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
#define PCIE0_CFG_POWERUP_RESET (1 << 2)
#define PCIE0_CFG_CORE_CLK_EN (1 << 1)
#define PCIE0_CFG_AUX_CLK_EN (1 << 0)
#define PAD_FUNCTION_EN_0 0x650
#define PMX_UART0_MASK (1 << 1)
#define PMX_I2C0_MASK (1 << 2)
#define PMX_I2S0_MASK (1 << 3)
#define PMX_SSP0_MASK (1 << 4)
#define PMX_CLCD1_MASK (1 << 5)
#define PMX_EGPIO00_MASK (1 << 6)
#define PMX_EGPIO01_MASK (1 << 7)
#define PMX_EGPIO02_MASK (1 << 8)
#define PMX_EGPIO03_MASK (1 << 9)
#define PMX_EGPIO04_MASK (1 << 10)
#define PMX_EGPIO05_MASK (1 << 11)
#define PMX_EGPIO06_MASK (1 << 12)
#define PMX_EGPIO07_MASK (1 << 13)
#define PMX_EGPIO08_MASK (1 << 14)
#define PMX_EGPIO09_MASK (1 << 15)
#define PMX_SMI_MASK (1 << 16)
#define PMX_NAND8_MASK (1 << 17)
#define PMX_GMIICLK_MASK (1 << 18)
#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
#define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
#define PMX_GMIID47_MASK (1 << 21)
#define PMX_MDC_MDIO_MASK (1 << 22)
#define PMX_MCI_DATA8_15_MASK (1 << 23)
#define PMX_NFAD23_MASK (1 << 24)
#define PMX_NFAD24_MASK (1 << 25)
#define PMX_NFAD25_MASK (1 << 26)
#define PMX_NFCE3_MASK (1 << 27)
#define PMX_NFWPRT3_MASK (1 << 28)
#define PMX_NFRSTPWDWN0_MASK (1 << 29)
#define PMX_NFRSTPWDWN1_MASK (1 << 30)
#define PMX_NFRSTPWDWN2_MASK (1 << 31)
#define PAD_FUNCTION_EN_1 0x654
#define PMX_NFRSTPWDWN3_MASK (1 << 0)
#define PMX_SMINCS2_MASK (1 << 1)
#define PMX_SMINCS3_MASK (1 << 2)
#define PMX_CLCD2_MASK (1 << 3)
#define PMX_KBD_ROWCOL68_MASK (1 << 4)
#define PMX_EGPIO10_MASK (1 << 5)
#define PMX_EGPIO11_MASK (1 << 6)
#define PMX_EGPIO12_MASK (1 << 7)
#define PMX_EGPIO13_MASK (1 << 8)
#define PMX_EGPIO14_MASK (1 << 9)
#define PMX_EGPIO15_MASK (1 << 10)
#define PMX_UART0_MODEM_MASK (1 << 11)
#define PMX_GPT0_TMR0_MASK (1 << 12)
#define PMX_GPT0_TMR1_MASK (1 << 13)
#define PMX_GPT1_TMR0_MASK (1 << 14)
#define PMX_GPT1_TMR1_MASK (1 << 15)
#define PMX_I2S1_MASK (1 << 16)
#define PMX_KBD_ROWCOL25_MASK (1 << 17)
#define PMX_NFIO8_15_MASK (1 << 18)
#define PMX_KBD_COL1_MASK (1 << 19)
#define PMX_NFCE1_MASK (1 << 20)
#define PMX_KBD_COL0_MASK (1 << 21)
#define PMX_NFCE2_MASK (1 << 22)
#define PMX_KBD_ROW1_MASK (1 << 23)
#define PMX_NFWPRT1_MASK (1 << 24)
#define PMX_KBD_ROW0_MASK (1 << 25)
#define PMX_NFWPRT2_MASK (1 << 26)
#define PMX_MCIDATA0_MASK (1 << 27)
#define PMX_MCIDATA1_MASK (1 << 28)
#define PMX_MCIDATA2_MASK (1 << 29)
#define PMX_MCIDATA3_MASK (1 << 30)
#define PMX_MCIDATA4_MASK (1 << 31)
#define PAD_FUNCTION_EN_2 0x658
#define PMX_MCIDATA5_MASK (1 << 0)
#define PMX_MCIDATA6_MASK (1 << 1)
#define PMX_MCIDATA7_MASK (1 << 2)
#define PMX_MCIDATA1SD_MASK (1 << 3)
#define PMX_MCIDATA2SD_MASK (1 << 4)
#define PMX_MCIDATA3SD_MASK (1 << 5)
#define PMX_MCIADDR0ALE_MASK (1 << 6)
#define PMX_MCIADDR1CLECLK_MASK (1 << 7)
#define PMX_MCIADDR2_MASK (1 << 8)
#define PMX_MCICECF_MASK (1 << 9)
#define PMX_MCICEXD_MASK (1 << 10)
#define PMX_MCICESDMMC_MASK (1 << 11)
#define PMX_MCICDCF1_MASK (1 << 12)
#define PMX_MCICDCF2_MASK (1 << 13)
#define PMX_MCICDXD_MASK (1 << 14)
#define PMX_MCICDSDMMC_MASK (1 << 15)
#define PMX_MCIDATADIR_MASK (1 << 16)
#define PMX_MCIDMARQWP_MASK (1 << 17)
#define PMX_MCIIORDRE_MASK (1 << 18)
#define PMX_MCIIOWRWE_MASK (1 << 19)
#define PMX_MCIRESETCF_MASK (1 << 20)
#define PMX_MCICS0CE_MASK (1 << 21)
#define PMX_MCICFINTR_MASK (1 << 22)
#define PMX_MCIIORDY_MASK (1 << 23)
#define PMX_MCICS1_MASK (1 << 24)
#define PMX_MCIDMAACK_MASK (1 << 25)
#define PMX_MCISDCMD_MASK (1 << 26)
#define PMX_MCILEDS_MASK (1 << 27)
#define PMX_TOUCH_XY_MASK (1 << 28)
#define PMX_SSP0_CS0_MASK (1 << 29)
#define PMX_SSP0_CS1_2_MASK (1 << 30)
/* combined macros */
#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
PMX_RXCLK_RDV_TXEN_D03_MASK | \
PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
PMX_EGPIO02_MASK | \
PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
PMX_EGPIO09_MASK)
#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
PMX_KBD_COL1_MASK)
#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
PMX_NFCE3_MASK)
#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
#define PMX_MCIFALL_1_MASK 0xF8000000
#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
PMX_NFCE2_MASK)
#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
PMX_SSP0_CS1_2_MASK)
#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
PMX_GMIID47_MASK)
#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
PMX_SSP0_CS1_2_MASK)
#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
PCIE##x##_CFG_AUX_CLK_EN | \
PCIE##x##_CFG_CORE_CLK_EN | \
PCIE##x##_CFG_POWERUP_RESET | \
PCIE##x##_CFG_DEVICE_PRESENT)
#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
SATA##x##_CFG_PM_CLK_EN | \
SATA##x##_CFG_POWERUP_RESET | \
SATA##x##_CFG_RX_CLK_EN | \
SATA##x##_CFG_TX_CLK_EN)
/* Pad multiplexing for i2c0 device */
static const unsigned i2c0_pins[] = { 102, 103 };
static struct spear_muxreg i2c0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2C0_MASK,
.val = PMX_I2C0_MASK,
},
};
static struct spear_modemux i2c0_modemux[] = {
{
.muxregs = i2c0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
},
};
static struct spear_pingroup i2c0_pingroup = {
.name = "i2c0_grp",
.pins = i2c0_pins,
.npins = ARRAY_SIZE(i2c0_pins),
.modemuxs = i2c0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
};
static const char *const i2c0_grps[] = { "i2c0_grp" };
static struct spear_function i2c0_function = {
.name = "i2c0",
.groups = i2c0_grps,
.ngroups = ARRAY_SIZE(i2c0_grps),
};
/* Pad multiplexing for ssp0 device */
static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
static struct spear_muxreg ssp0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SSP0_MASK,
.val = PMX_SSP0_MASK,
},
};
static struct spear_modemux ssp0_modemux[] = {
{
.muxregs = ssp0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
},
};
static struct spear_pingroup ssp0_pingroup = {
.name = "ssp0_grp",
.pins = ssp0_pins,
.npins = ARRAY_SIZE(ssp0_pins),
.modemuxs = ssp0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
};
/* Pad multiplexing for ssp0_cs0 device */
static const unsigned ssp0_cs0_pins[] = { 96 };
static struct spear_muxreg ssp0_cs0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_SSP0_CS0_MASK,
.val = PMX_SSP0_CS0_MASK,
},
};
static struct spear_modemux ssp0_cs0_modemux[] = {
{
.muxregs = ssp0_cs0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
},
};
static struct spear_pingroup ssp0_cs0_pingroup = {
.name = "ssp0_cs0_grp",
.pins = ssp0_cs0_pins,
.npins = ARRAY_SIZE(ssp0_cs0_pins),
.modemuxs = ssp0_cs0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
};
/* ssp0_cs1_2 device */
static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_SSP0_CS1_2_MASK,
.val = PMX_SSP0_CS1_2_MASK,
},
};
static struct spear_modemux ssp0_cs1_2_modemux[] = {
{
.muxregs = ssp0_cs1_2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
},
};
static struct spear_pingroup ssp0_cs1_2_pingroup = {
.name = "ssp0_cs1_2_grp",
.pins = ssp0_cs1_2_pins,
.npins = ARRAY_SIZE(ssp0_cs1_2_pins),
.modemuxs = ssp0_cs1_2_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
};
static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
"ssp0_cs1_2_grp" };
static struct spear_function ssp0_function = {
.name = "ssp0",
.groups = ssp0_grps,
.ngroups = ARRAY_SIZE(ssp0_grps),
};
/* Pad multiplexing for i2s0 device */
static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
static struct spear_muxreg i2s0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK,
.val = PMX_I2S0_MASK,
},
};
static struct spear_modemux i2s0_modemux[] = {
{
.muxregs = i2s0_muxreg,
.nmuxregs = ARRAY_SIZE(i2s0_muxreg),
},
};
static struct spear_pingroup i2s0_pingroup = {
.name = "i2s0_grp",
.pins = i2s0_pins,
.npins = ARRAY_SIZE(i2s0_pins),
.modemuxs = i2s0_modemux,
.nmodemuxs = ARRAY_SIZE(i2s0_modemux),
};
static const char *const i2s0_grps[] = { "i2s0_grp" };
static struct spear_function i2s0_function = {
.name = "i2s0",
.groups = i2s0_grps,
.ngroups = ARRAY_SIZE(i2s0_grps),
};
/* Pad multiplexing for i2s1 device */
static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
static struct spear_muxreg i2s1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_I2S1_MASK,
.val = PMX_I2S1_MASK,
},
};
static struct spear_modemux i2s1_modemux[] = {
{
.muxregs = i2s1_muxreg,
.nmuxregs = ARRAY_SIZE(i2s1_muxreg),
},
};
static struct spear_pingroup i2s1_pingroup = {
.name = "i2s1_grp",
.pins = i2s1_pins,
.npins = ARRAY_SIZE(i2s1_pins),
.modemuxs = i2s1_modemux,
.nmodemuxs = ARRAY_SIZE(i2s1_modemux),
};
static const char *const i2s1_grps[] = { "i2s1_grp" };
static struct spear_function i2s1_function = {
.name = "i2s1",
.groups = i2s1_grps,
.ngroups = ARRAY_SIZE(i2s1_grps),
};
/* Pad multiplexing for clcd device */
static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
135, 136, 137, 138, 139, 140, 141, 142 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 };
static struct spear_muxreg clcd_high_res_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_CLCD2_MASK,
.val = PMX_CLCD2_MASK,
},
};
static struct spear_modemux clcd_high_res_modemux[] = {
{
.muxregs = clcd_high_res_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
},
};
static struct spear_pingroup clcd_high_res_pingroup = {
.name = "clcd_high_res_grp",
.pins = clcd_high_res_pins,
.npins = ARRAY_SIZE(clcd_high_res_pins),
.modemuxs = clcd_high_res_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
146, 147, 148, 149, 150, 151, 152 };
static struct spear_muxreg arm_gpio_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_EGPIO_0_GRP_MASK,
.val = PMX_EGPIO_0_GRP_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_EGPIO_1_GRP_MASK,
.val = PMX_EGPIO_1_GRP_MASK,
},
};
static struct spear_modemux arm_gpio_modemux[] = {
{
.muxregs = arm_gpio_muxreg,
.nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
},
};
static struct spear_pingroup arm_gpio_pingroup = {
.name = "arm_gpio_grp",
.pins = arm_gpio_pins,
.npins = ARRAY_SIZE(arm_gpio_pins),
.modemuxs = arm_gpio_modemux,
.nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
};
static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
static struct spear_function arm_gpio_function = {
.name = "arm_gpio",
.groups = arm_gpio_grps,
.ngroups = ARRAY_SIZE(arm_gpio_grps),
};
/* Pad multiplexing for smi 2 chips device */
static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
static struct spear_muxreg smi_2_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
},
};
static struct spear_modemux smi_2_chips_modemux[] = {
{
.muxregs = smi_2_chips_muxreg,
.nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
},
};
static struct spear_pingroup smi_2_chips_pingroup = {
.name = "smi_2_chips_grp",
.pins = smi_2_chips_pins,
.npins = ARRAY_SIZE(smi_2_chips_pins),
.modemuxs = smi_2_chips_modemux,
.nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
};
static const unsigned smi_4_chips_pins[] = { 54, 55 };
static struct spear_muxreg smi_4_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
},
};
static struct spear_modemux smi_4_chips_modemux[] = {
{
.muxregs = smi_4_chips_muxreg,
.nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
},
};
static struct spear_pingroup smi_4_chips_pingroup = {
.name = "smi_4_chips_grp",
.pins = smi_4_chips_pins,
.npins = ARRAY_SIZE(smi_4_chips_pins),
.modemuxs = smi_4_chips_modemux,
.nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
};
static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
static struct spear_function smi_function = {
.name = "smi",
.groups = smi_grps,
.ngroups = ARRAY_SIZE(smi_grps),
};
/* Pad multiplexing for gmii device */
static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
195, 196, 197, 198, 199, 200 };
static struct spear_muxreg gmii_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_GMII_MASK,
.val = PMX_GMII_MASK,
},
};
static struct spear_modemux gmii_modemux[] = {
{
.muxregs = gmii_muxreg,
.nmuxregs = ARRAY_SIZE(gmii_muxreg),
},
};
static struct spear_pingroup gmii_pingroup = {
.name = "gmii_grp",
.pins = gmii_pins,
.npins = ARRAY_SIZE(gmii_pins),
.modemuxs = gmii_modemux,
.nmodemuxs = ARRAY_SIZE(gmii_modemux),
};
static const char *const gmii_grps[] = { "gmii_grp" };
static struct spear_function gmii_function = {
.name = "gmii",
.groups = gmii_grps,
.ngroups = ARRAY_SIZE(gmii_grps),
};
/* Pad multiplexing for rgmii device */
static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
static struct spear_muxreg rgmii_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_RGMII_REG0_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_RGMII_REG1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_RGMII_REG2_MASK,
.val = 0,
},
};
static struct spear_modemux rgmii_modemux[] = {
{
.muxregs = rgmii_muxreg,
.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
},
};
static struct spear_pingroup rgmii_pingroup = {
.name = "rgmii_grp",
.pins = rgmii_pins,
.npins = ARRAY_SIZE(rgmii_pins),
.modemuxs = rgmii_modemux,
.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
};
static const char *const rgmii_grps[] = { "rgmii_grp" };
static struct spear_function rgmii_function = {
.name = "rgmii",
.groups = rgmii_grps,
.ngroups = ARRAY_SIZE(rgmii_grps),
};
/* Pad multiplexing for smii_0_1_2 device */
static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53, 54, 55 };
static struct spear_muxreg smii_0_1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_SMII_0_1_2_MASK,
.val = 0,
},
};
static struct spear_modemux smii_0_1_2_modemux[] = {
{
.muxregs = smii_0_1_2_muxreg,
.nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
},
};
static struct spear_pingroup smii_0_1_2_pingroup = {
.name = "smii_0_1_2_grp",
.pins = smii_0_1_2_pins,
.npins = ARRAY_SIZE(smii_0_1_2_pins),
.modemuxs = smii_0_1_2_modemux,
.nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
};
static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
static struct spear_function smii_0_1_2_function = {
.name = "smii_0_1_2",
.groups = smii_0_1_2_grps,
.ngroups = ARRAY_SIZE(smii_0_1_2_grps),
};
/* Pad multiplexing for ras_mii_txclk device */
static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
static struct spear_muxreg ras_mii_txclk_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NFCE2_MASK,
.val = 0,
},
};
static struct spear_modemux ras_mii_txclk_modemux[] = {
{
.muxregs = ras_mii_txclk_muxreg,
.nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
},
};
static struct spear_pingroup ras_mii_txclk_pingroup = {
.name = "ras_mii_txclk_grp",
.pins = ras_mii_txclk_pins,
.npins = ARRAY_SIZE(ras_mii_txclk_pins),
.modemuxs = ras_mii_txclk_modemux,
.nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
};
static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
static struct spear_function ras_mii_txclk_function = {
.name = "ras_mii_txclk",
.groups = ras_mii_txclk_grps,
.ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
};
/* Pad multiplexing for nand 8bit device (cs0 only) */
static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
212 };
static struct spear_muxreg nand_8bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_NAND8BIT_0_MASK,
.val = PMX_NAND8BIT_0_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND8BIT_1_MASK,
.val = PMX_NAND8BIT_1_MASK,
},
};
static struct spear_modemux nand_8bit_modemux[] = {
{
.muxregs = nand_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
},
};
static struct spear_pingroup nand_8bit_pingroup = {
.name = "nand_8bit_grp",
.pins = nand_8bit_pins,
.npins = ARRAY_SIZE(nand_8bit_pins),
.modemuxs = nand_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
};
/* Pad multiplexing for nand 16bit device */
static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
210 };
static struct spear_muxreg nand_16bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND16BIT_1_MASK,
.val = PMX_NAND16BIT_1_MASK,
},
};
static struct spear_modemux nand_16bit_modemux[] = {
{
.muxregs = nand_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
},
};
static struct spear_pingroup nand_16bit_pingroup = {
.name = "nand_16bit_grp",
.pins = nand_16bit_pins,
.npins = ARRAY_SIZE(nand_16bit_pins),
.modemuxs = nand_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
};
/* Pad multiplexing for nand 4 chips */
static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
static struct spear_muxreg nand_4_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND_4CHIPS_MASK,
.val = PMX_NAND_4CHIPS_MASK,
},
};
static struct spear_modemux nand_4_chips_modemux[] = {
{
.muxregs = nand_4_chips_muxreg,
.nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
},
};
static struct spear_pingroup nand_4_chips_pingroup = {
.name = "nand_4_chips_grp",
.pins = nand_4_chips_pins,
.npins = ARRAY_SIZE(nand_4_chips_pins),
.modemuxs = nand_4_chips_modemux,
.nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
};
static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
"nand_4_chips_grp" };
static struct spear_function nand_function = {
.name = "nand",
.groups = nand_grps,
.ngroups = ARRAY_SIZE(nand_grps),
};
/* Pad multiplexing for keyboard_6x6 device */
static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
208, 209, 210, 211, 212 };
static struct spear_muxreg keyboard_6x6_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
PMX_NFWPRT2_MASK,
.val = PMX_KEYBOARD_6X6_MASK,
},
};
static struct spear_modemux keyboard_6x6_modemux[] = {
{
.muxregs = keyboard_6x6_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
},
};
static struct spear_pingroup keyboard_6x6_pingroup = {
.name = "keyboard_6x6_grp",
.pins = keyboard_6x6_pins,
.npins = ARRAY_SIZE(keyboard_6x6_pins),
.modemuxs = keyboard_6x6_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
};
/* Pad multiplexing for keyboard_rowcol6_8 device */
static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL68_MASK,
.val = PMX_KBD_ROWCOL68_MASK,
},
};
static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
{
.muxregs = keyboard_rowcol6_8_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
},
};
static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
.name = "keyboard_rowcol6_8_grp",
.pins = keyboard_rowcol6_8_pins,
.npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
.modemuxs = keyboard_rowcol6_8_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
};
static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp" };
static struct spear_function keyboard_function = {
.name = "keyboard",
.groups = keyboard_grps,
.ngroups = ARRAY_SIZE(keyboard_grps),
};
/* Pad multiplexing for uart0 device */
static const unsigned uart0_pins[] = { 100, 101 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_UART0_MASK,
.val = PMX_UART0_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
static struct spear_pingroup uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
/* Pad multiplexing for uart0_modem device */
static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
static struct spear_muxreg uart0_modem_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_UART0_MODEM_MASK,
.val = PMX_UART0_MODEM_MASK,
},
};
static struct spear_modemux uart0_modem_modemux[] = {
{
.muxregs = uart0_modem_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
},
};
static struct spear_pingroup uart0_modem_pingroup = {
.name = "uart0_modem_grp",
.pins = uart0_modem_pins,
.npins = ARRAY_SIZE(uart0_modem_pins),
.modemuxs = uart0_modem_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
static struct spear_function uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* Pad multiplexing for gpt0_tmr0 device */
static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
static struct spear_muxreg gpt0_tmr0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT0_TMR0_MASK,
.val = PMX_GPT0_TMR0_MASK,
},
};
static struct spear_modemux gpt0_tmr0_modemux[] = {
{
.muxregs = gpt0_tmr0_muxreg,
.nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
},
};
static struct spear_pingroup gpt0_tmr0_pingroup = {
.name = "gpt0_tmr0_grp",
.pins = gpt0_tmr0_pins,
.npins = ARRAY_SIZE(gpt0_tmr0_pins),
.modemuxs = gpt0_tmr0_modemux,
.nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
};
/* Pad multiplexing for gpt0_tmr1 device */
static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
static struct spear_muxreg gpt0_tmr1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT0_TMR1_MASK,
.val = PMX_GPT0_TMR1_MASK,
},
};
static struct spear_modemux gpt0_tmr1_modemux[] = {
{
.muxregs = gpt0_tmr1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
},
};
static struct spear_pingroup gpt0_tmr1_pingroup = {
.name = "gpt0_tmr1_grp",
.pins = gpt0_tmr1_pins,
.npins = ARRAY_SIZE(gpt0_tmr1_pins),
.modemuxs = gpt0_tmr1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
};
static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
static struct spear_function gpt0_function = {
.name = "gpt0",
.groups = gpt0_grps,
.ngroups = ARRAY_SIZE(gpt0_grps),
};
/* Pad multiplexing for gpt1_tmr0 device */
static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
static struct spear_muxreg gpt1_tmr0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT1_TMR0_MASK,
.val = PMX_GPT1_TMR0_MASK,
},
};
static struct spear_modemux gpt1_tmr0_modemux[] = {
{
.muxregs = gpt1_tmr0_muxreg,
.nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
},
};
static struct spear_pingroup gpt1_tmr0_pingroup = {
.name = "gpt1_tmr0_grp",
.pins = gpt1_tmr0_pins,
.npins = ARRAY_SIZE(gpt1_tmr0_pins),
.modemuxs = gpt1_tmr0_modemux,
.nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
};
/* Pad multiplexing for gpt1_tmr1 device */
static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
static struct spear_muxreg gpt1_tmr1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT1_TMR1_MASK,
.val = PMX_GPT1_TMR1_MASK,
},
};
static struct spear_modemux gpt1_tmr1_modemux[] = {
{
.muxregs = gpt1_tmr1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
},
};
static struct spear_pingroup gpt1_tmr1_pingroup = {
.name = "gpt1_tmr1_grp",
.pins = gpt1_tmr1_pins,
.npins = ARRAY_SIZE(gpt1_tmr1_pins),
.modemuxs = gpt1_tmr1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
};
static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
static struct spear_function gpt1_function = {
.name = "gpt1",
.groups = gpt1_grps,
.ngroups = ARRAY_SIZE(gpt1_grps),
};
/* Pad multiplexing for mcif device */
static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
243, 244, 245 };
#define MCIF_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = PMX_MCI_DATA8_15_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_1, \
.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
PMX_NFWPRT2_MASK, \
.val = PMX_MCIFALL_1_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_2, \
.mask = PMX_MCIFALL_2_MASK, \
.val = PMX_MCIFALL_2_MASK, \
}
/* sdhci device */
static struct spear_muxreg sdhci_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_SD,
},
};
static struct spear_modemux sdhci_modemux[] = {
{
.muxregs = sdhci_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
},
};
static struct spear_pingroup sdhci_pingroup = {
.name = "sdhci_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = sdhci_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* cf device */
static struct spear_muxreg cf_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_CF,
},
};
static struct spear_modemux cf_modemux[] = {
{
.muxregs = cf_muxreg,
.nmuxregs = ARRAY_SIZE(cf_muxreg),
},
};
static struct spear_pingroup cf_pingroup = {
.name = "cf_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = cf_modemux,
.nmodemuxs = ARRAY_SIZE(cf_modemux),
};
static const char *const cf_grps[] = { "cf_grp" };
static struct spear_function cf_function = {
.name = "cf",
.groups = cf_grps,
.ngroups = ARRAY_SIZE(cf_grps),
};
/* xd device */
static struct spear_muxreg xd_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_XD,
},
};
static struct spear_modemux xd_modemux[] = {
{
.muxregs = xd_muxreg,
.nmuxregs = ARRAY_SIZE(xd_muxreg),
},
};
static struct spear_pingroup xd_pingroup = {
.name = "xd_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = xd_modemux,
.nmodemuxs = ARRAY_SIZE(xd_modemux),
};
static const char *const xd_grps[] = { "xd_grp" };
static struct spear_function xd_function = {
.name = "xd",
.groups = xd_grps,
.ngroups = ARRAY_SIZE(xd_grps),
};
/* Pad multiplexing for touch_xy device */
static const unsigned touch_xy_pins[] = { 97 };
static struct spear_muxreg touch_xy_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_TOUCH_XY_MASK,
.val = PMX_TOUCH_XY_MASK,
},
};
static struct spear_modemux touch_xy_modemux[] = {
{
.muxregs = touch_xy_muxreg,
.nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
},
};
static struct spear_pingroup touch_xy_pingroup = {
.name = "touch_xy_grp",
.pins = touch_xy_pins,
.npins = ARRAY_SIZE(touch_xy_pins),
.modemuxs = touch_xy_modemux,
.nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
};
static const char *const touch_xy_grps[] = { "touch_xy_grp" };
static struct spear_function touch_xy_function = {
.name = "touchscreen",
.groups = touch_xy_grps,
.ngroups = ARRAY_SIZE(touch_xy_grps),
};
/* Pad multiplexing for uart1 device */
/* Muxed with I2C */
static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2C0_MASK,
.val = 0,
},
};
static struct spear_modemux uart1_dis_i2c_modemux[] = {
{
.muxregs = uart1_dis_i2c_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
},
};
static struct spear_pingroup uart_1_dis_i2c_pingroup = {
.name = "uart1_disable_i2c_grp",
.pins = uart1_dis_i2c_pins,
.npins = ARRAY_SIZE(uart1_dis_i2c_pins),
.modemuxs = uart1_dis_i2c_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
};
/* Muxed with SD/MMC */
static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
static struct spear_muxreg uart1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_MCIDATA1_MASK |
PMX_MCIDATA2_MASK,
.val = 0,
},
};
static struct spear_modemux uart1_dis_sd_modemux[] = {
{
.muxregs = uart1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
},
};
static struct spear_pingroup uart_1_dis_sd_pingroup = {
.name = "uart1_disable_sd_grp",
.pins = uart1_dis_sd_pins,
.npins = ARRAY_SIZE(uart1_dis_sd_pins),
.modemuxs = uart1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
};
static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
"uart1_disable_sd_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* Pad multiplexing for uart2_3 device */
static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
static struct spear_muxreg uart2_3_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK,
.val = 0,
},
};
static struct spear_modemux uart2_3_modemux[] = {
{
.muxregs = uart2_3_muxreg,
.nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
},
};
static struct spear_pingroup uart_2_3_pingroup = {
.name = "uart2_3_grp",
.pins = uart2_3_pins,
.npins = ARRAY_SIZE(uart2_3_pins),
.modemuxs = uart2_3_modemux,
.nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
};
static const char *const uart2_3_grps[] = { "uart2_3_grp" };
static struct spear_function uart2_3_function = {
.name = "uart2_3",
.groups = uart2_3_grps,
.ngroups = ARRAY_SIZE(uart2_3_grps),
};
/* Pad multiplexing for uart4 device */
static const unsigned uart4_pins[] = { 108, 113 };
static struct spear_muxreg uart4_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux uart4_modemux[] = {
{
.muxregs = uart4_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_muxreg),
},
};
static struct spear_pingroup uart_4_pingroup = {
.name = "uart4_grp",
.pins = uart4_pins,
.npins = ARRAY_SIZE(uart4_pins),
.modemuxs = uart4_modemux,
.nmodemuxs = ARRAY_SIZE(uart4_modemux),
};
static const char *const uart4_grps[] = { "uart4_grp" };
static struct spear_function uart4_function = {
.name = "uart4",
.groups = uart4_grps,
.ngroups = ARRAY_SIZE(uart4_grps),
};
/* Pad multiplexing for uart5 device */
static const unsigned uart5_pins[] = { 114, 115 };
static struct spear_muxreg uart5_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux uart5_modemux[] = {
{
.muxregs = uart5_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_muxreg),
},
};
static struct spear_pingroup uart_5_pingroup = {
.name = "uart5_grp",
.pins = uart5_pins,
.npins = ARRAY_SIZE(uart5_pins),
.modemuxs = uart5_modemux,
.nmodemuxs = ARRAY_SIZE(uart5_modemux),
};
static const char *const uart5_grps[] = { "uart5_grp" };
static struct spear_function uart5_function = {
.name = "uart5",
.groups = uart5_grps,
.ngroups = ARRAY_SIZE(uart5_grps),
};
/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
136, 137 };
static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
{
.muxregs = rs485_0_1_tdm_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
},
};
static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
.name = "rs485_0_1_tdm_0_1_grp",
.pins = rs485_0_1_tdm_0_1_pins,
.npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
.modemuxs = rs485_0_1_tdm_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
};
static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
static struct spear_function rs485_0_1_tdm_0_1_function = {
.name = "rs485_0_1_tdm_0_1",
.groups = rs485_0_1_tdm_0_1_grps,
.ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
};
/* Pad multiplexing for i2c_1_2 device */
static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
static struct spear_muxreg i2c_1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_1_2_modemux[] = {
{
.muxregs = i2c_1_2_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
},
};
static struct spear_pingroup i2c_1_2_pingroup = {
.name = "i2c_1_2_grp",
.pins = i2c_1_2_pins,
.npins = ARRAY_SIZE(i2c_1_2_pins),
.modemuxs = i2c_1_2_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
};
static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
static struct spear_function i2c_1_2_function = {
.name = "i2c_1_2",
.groups = i2c_1_2_grps,
.ngroups = ARRAY_SIZE(i2c_1_2_grps),
};
/* Pad multiplexing for i2c3_dis_smi_clcd device */
/* Muxed with SMI & CLCD */
static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
.val = 0,
},
};
static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
{
.muxregs = i2c3_dis_smi_clcd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
},
};
static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
.name = "i2c3_dis_smi_clcd_grp",
.pins = i2c3_dis_smi_clcd_pins,
.npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
.modemuxs = i2c3_dis_smi_clcd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
};
/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
/* Muxed with SD/MMC & I2S1 */
static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
.val = 0,
},
};
static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
{
.muxregs = i2c3_dis_sd_i2s0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
},
};
static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
.name = "i2c3_dis_sd_i2s0_grp",
.pins = i2c3_dis_sd_i2s0_pins,
.npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
.modemuxs = i2c3_dis_sd_i2s0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
};
static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
"i2c3_dis_sd_i2s0_grp" };
static struct spear_function i2c3_unction = {
.name = "i2c3_i2s1",
.groups = i2c3_grps,
.ngroups = ARRAY_SIZE(i2c3_grps),
};
/* Pad multiplexing for i2c_4_5_dis_smi device */
/* Muxed with SMI */
static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
{
.muxregs = i2c_4_5_dis_smi_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
},
};
static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
.name = "i2c_4_5_dis_smi_grp",
.pins = i2c_4_5_dis_smi_pins,
.npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
.modemuxs = i2c_4_5_dis_smi_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
};
/* Pad multiplexing for i2c4_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_MCIDATA4_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIDATA5_MASK,
.val = 0,
},
};
static struct spear_modemux i2c4_dis_sd_modemux[] = {
{
.muxregs = i2c4_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c4_dis_sd_pingroup = {
.name = "i2c4_dis_sd_grp",
.pins = i2c4_dis_sd_pins,
.npins = ARRAY_SIZE(i2c4_dis_sd_pins),
.modemuxs = i2c4_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
};
/* Pad multiplexing for i2c5_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIDATA6_MASK |
PMX_MCIDATA7_MASK,
.val = 0,
},
};
static struct spear_modemux i2c5_dis_sd_modemux[] = {
{
.muxregs = i2c5_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c5_dis_sd_pingroup = {
.name = "i2c5_dis_sd_grp",
.pins = i2c5_dis_sd_pins,
.npins = ARRAY_SIZE(i2c5_dis_sd_pins),
.modemuxs = i2c5_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
};
static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
"i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
static struct spear_function i2c_4_5_function = {
.name = "i2c_4_5",
.groups = i2c_4_5_grps,
.ngroups = ARRAY_SIZE(i2c_4_5_grps),
};
/* Pad multiplexing for i2c_6_7_dis_kbd device */
/* Muxed with KBD */
static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
{
.muxregs = i2c_6_7_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
},
};
static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
.name = "i2c_6_7_dis_kbd_grp",
.pins = i2c_6_7_dis_kbd_pins,
.npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
.modemuxs = i2c_6_7_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
};
/* Pad multiplexing for i2c6_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIIORDRE_MASK |
PMX_MCIIOWRWE_MASK,
.val = 0,
},
};
static struct spear_modemux i2c6_dis_sd_modemux[] = {
{
.muxregs = i2c6_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c6_dis_sd_pingroup = {
.name = "i2c6_dis_sd_grp",
.pins = i2c6_dis_sd_pins,
.npins = ARRAY_SIZE(i2c6_dis_sd_pins),
.modemuxs = i2c6_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
};
/* Pad multiplexing for i2c7_dis_sd device */
static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIRESETCF_MASK |
PMX_MCICS0CE_MASK,
.val = 0,
},
};
static struct spear_modemux i2c7_dis_sd_modemux[] = {
{
.muxregs = i2c7_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c7_dis_sd_pingroup = {
.name = "i2c7_dis_sd_grp",
.pins = i2c7_dis_sd_pins,
.npins = ARRAY_SIZE(i2c7_dis_sd_pins),
.modemuxs = i2c7_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
};
static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
"i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
static struct spear_function i2c_6_7_function = {
.name = "i2c_6_7",
.groups = i2c_6_7_grps,
.ngroups = ARRAY_SIZE(i2c_6_7_grps),
};
/* Pad multiplexing for can0_dis_nor device */
/* Muxed with NOR */
static const unsigned can0_dis_nor_pins[] = { 56, 57 };
static struct spear_muxreg can0_dis_nor_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_NFRSTPWDWN2_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NFRSTPWDWN3_MASK,
.val = 0,
},
};
static struct spear_modemux can0_dis_nor_modemux[] = {
{
.muxregs = can0_dis_nor_muxreg,
.nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
},
};
static struct spear_pingroup can0_dis_nor_pingroup = {
.name = "can0_dis_nor_grp",
.pins = can0_dis_nor_pins,
.npins = ARRAY_SIZE(can0_dis_nor_pins),
.modemuxs = can0_dis_nor_modemux,
.nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
};
/* Pad multiplexing for can0_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned can0_dis_sd_pins[] = { 240, 241 };
static struct spear_muxreg can0_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
.val = 0,
},
};
static struct spear_modemux can0_dis_sd_modemux[] = {
{
.muxregs = can0_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
},
};
static struct spear_pingroup can0_dis_sd_pingroup = {
.name = "can0_dis_sd_grp",
.pins = can0_dis_sd_pins,
.npins = ARRAY_SIZE(can0_dis_sd_pins),
.modemuxs = can0_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
};
static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
};
static struct spear_function can0_function = {
.name = "can0",
.groups = can0_grps,
.ngroups = ARRAY_SIZE(can0_grps),
};
/* Pad multiplexing for can1_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned can1_dis_sd_pins[] = { 242, 243 };
static struct spear_muxreg can1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
.val = 0,
},
};
static struct spear_modemux can1_dis_sd_modemux[] = {
{
.muxregs = can1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
},
};
static struct spear_pingroup can1_dis_sd_pingroup = {
.name = "can1_dis_sd_grp",
.pins = can1_dis_sd_pins,
.npins = ARRAY_SIZE(can1_dis_sd_pins),
.modemuxs = can1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
};
/* Pad multiplexing for can1_dis_kbd device */
/* Muxed with KBD */
static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
static struct spear_muxreg can1_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = 0,
},
};
static struct spear_modemux can1_dis_kbd_modemux[] = {
{
.muxregs = can1_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
},
};
static struct spear_pingroup can1_dis_kbd_pingroup = {
.name = "can1_dis_kbd_grp",
.pins = can1_dis_kbd_pins,
.npins = ARRAY_SIZE(can1_dis_kbd_pins),
.modemuxs = can1_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
};
static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
};
static struct spear_function can1_function = {
.name = "can1",
.groups = can1_grps,
.ngroups = ARRAY_SIZE(can1_grps),
};
/* Pad multiplexing for pci device */
static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
#define PCI_SATA_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = 0, \
}, { \
.reg = PAD_FUNCTION_EN_1, \
.mask = PMX_PCI_REG1_MASK, \
.val = 0, \
}, { \
.reg = PAD_FUNCTION_EN_2, \
.mask = PMX_PCI_REG2_MASK, \
.val = 0, \
}
/* pad multiplexing for pcie0 device */
static struct spear_muxreg pcie0_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(0),
.val = PCIE_CFG_VAL(0),
},
};
static struct spear_modemux pcie0_modemux[] = {
{
.muxregs = pcie0_muxreg,
.nmuxregs = ARRAY_SIZE(pcie0_muxreg),
},
};
static struct spear_pingroup pcie0_pingroup = {
.name = "pcie0_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie0_modemux,
.nmodemuxs = ARRAY_SIZE(pcie0_modemux),
};
/* pad multiplexing for pcie1 device */
static struct spear_muxreg pcie1_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(1),
.val = PCIE_CFG_VAL(1),
},
};
static struct spear_modemux pcie1_modemux[] = {
{
.muxregs = pcie1_muxreg,
.nmuxregs = ARRAY_SIZE(pcie1_muxreg),
},
};
static struct spear_pingroup pcie1_pingroup = {
.name = "pcie1_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie1_modemux,
.nmodemuxs = ARRAY_SIZE(pcie1_modemux),
};
/* pad multiplexing for pcie2 device */
static struct spear_muxreg pcie2_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(2),
.val = PCIE_CFG_VAL(2),
},
};
static struct spear_modemux pcie2_modemux[] = {
{
.muxregs = pcie2_muxreg,
.nmuxregs = ARRAY_SIZE(pcie2_muxreg),
},
};
static struct spear_pingroup pcie2_pingroup = {
.name = "pcie2_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie2_modemux,
.nmodemuxs = ARRAY_SIZE(pcie2_modemux),
};
static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
static struct spear_function pci_function = {
.name = "pci",
.groups = pci_grps,
.ngroups = ARRAY_SIZE(pci_grps),
};
/* pad multiplexing for sata0 device */
static struct spear_muxreg sata0_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(0),
.val = SATA_CFG_VAL(0),
},
};
static struct spear_modemux sata0_modemux[] = {
{
.muxregs = sata0_muxreg,
.nmuxregs = ARRAY_SIZE(sata0_muxreg),
},
};
static struct spear_pingroup sata0_pingroup = {
.name = "sata0_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata0_modemux,
.nmodemuxs = ARRAY_SIZE(sata0_modemux),
};
/* pad multiplexing for sata1 device */
static struct spear_muxreg sata1_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(1),
.val = SATA_CFG_VAL(1),
},
};
static struct spear_modemux sata1_modemux[] = {
{
.muxregs = sata1_muxreg,
.nmuxregs = ARRAY_SIZE(sata1_muxreg),
},
};
static struct spear_pingroup sata1_pingroup = {
.name = "sata1_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata1_modemux,
.nmodemuxs = ARRAY_SIZE(sata1_modemux),
};
/* pad multiplexing for sata2 device */
static struct spear_muxreg sata2_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(2),
.val = SATA_CFG_VAL(2),
},
};
static struct spear_modemux sata2_modemux[] = {
{
.muxregs = sata2_muxreg,
.nmuxregs = ARRAY_SIZE(sata2_muxreg),
},
};
static struct spear_pingroup sata2_pingroup = {
.name = "sata2_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata2_modemux,
.nmodemuxs = ARRAY_SIZE(sata2_modemux),
};
static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
};
static struct spear_function sata_function = {
.name = "sata",
.groups = sata_grps,
.ngroups = ARRAY_SIZE(sata_grps),
};
/* Pad multiplexing for ssp1_dis_kbd device */
static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
PMX_NFCE2_MASK,
.val = 0,
},
};
static struct spear_modemux ssp1_dis_kbd_modemux[] = {
{
.muxregs = ssp1_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
},
};
static struct spear_pingroup ssp1_dis_kbd_pingroup = {
.name = "ssp1_dis_kbd_grp",
.pins = ssp1_dis_kbd_pins,
.npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
.modemuxs = ssp1_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
};
/* Pad multiplexing for ssp1_dis_sd device */
static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
.val = 0,
},
};
static struct spear_modemux ssp1_dis_sd_modemux[] = {
{
.muxregs = ssp1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
},
};
static struct spear_pingroup ssp1_dis_sd_pingroup = {
.name = "ssp1_dis_sd_grp",
.pins = ssp1_dis_sd_pins,
.npins = ARRAY_SIZE(ssp1_dis_sd_pins),
.modemuxs = ssp1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
};
static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
"ssp1_dis_sd_grp" };
static struct spear_function ssp1_function = {
.name = "ssp1",
.groups = ssp1_grps,
.ngroups = ARRAY_SIZE(ssp1_grps),
};
/* Pad multiplexing for gpt64 device */
static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
static struct spear_muxreg gpt64_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
| PMX_MCILEDS_MASK,
.val = 0,
},
};
static struct spear_modemux gpt64_modemux[] = {
{
.muxregs = gpt64_muxreg,
.nmuxregs = ARRAY_SIZE(gpt64_muxreg),
},
};
static struct spear_pingroup gpt64_pingroup = {
.name = "gpt64_grp",
.pins = gpt64_pins,
.npins = ARRAY_SIZE(gpt64_pins),
.modemuxs = gpt64_modemux,
.nmodemuxs = ARRAY_SIZE(gpt64_modemux),
};
static const char *const gpt64_grps[] = { "gpt64_grp" };
static struct spear_function gpt64_function = {
.name = "gpt64",
.groups = gpt64_grps,
.ngroups = ARRAY_SIZE(gpt64_grps),
};
/* pingroups */
static struct spear_pingroup *spear1310_pingroups[] = {
&i2c0_pingroup,
&ssp0_pingroup,
&i2s0_pingroup,
&i2s1_pingroup,
&clcd_pingroup,
&clcd_high_res_pingroup,
&arm_gpio_pingroup,
&smi_2_chips_pingroup,
&smi_4_chips_pingroup,
&gmii_pingroup,
&rgmii_pingroup,
&smii_0_1_2_pingroup,
&ras_mii_txclk_pingroup,
&nand_8bit_pingroup,
&nand_16bit_pingroup,
&nand_4_chips_pingroup,
&keyboard_6x6_pingroup,
&keyboard_rowcol6_8_pingroup,
&uart0_pingroup,
&uart0_modem_pingroup,
&gpt0_tmr0_pingroup,
&gpt0_tmr1_pingroup,
&gpt1_tmr0_pingroup,
&gpt1_tmr1_pingroup,
&sdhci_pingroup,
&cf_pingroup,
&xd_pingroup,
&touch_xy_pingroup,
&ssp0_cs0_pingroup,
&ssp0_cs1_2_pingroup,
&uart_1_dis_i2c_pingroup,
&uart_1_dis_sd_pingroup,
&uart_2_3_pingroup,
&uart_4_pingroup,
&uart_5_pingroup,
&rs485_0_1_tdm_0_1_pingroup,
&i2c_1_2_pingroup,
&i2c3_dis_smi_clcd_pingroup,
&i2c3_dis_sd_i2s0_pingroup,
&i2c_4_5_dis_smi_pingroup,
&i2c4_dis_sd_pingroup,
&i2c5_dis_sd_pingroup,
&i2c_6_7_dis_kbd_pingroup,
&i2c6_dis_sd_pingroup,
&i2c7_dis_sd_pingroup,
&can0_dis_nor_pingroup,
&can0_dis_sd_pingroup,
&can1_dis_sd_pingroup,
&can1_dis_kbd_pingroup,
&pcie0_pingroup,
&pcie1_pingroup,
&pcie2_pingroup,
&sata0_pingroup,
&sata1_pingroup,
&sata2_pingroup,
&ssp1_dis_kbd_pingroup,
&ssp1_dis_sd_pingroup,
&gpt64_pingroup,
};
/* functions */
static struct spear_function *spear1310_functions[] = {
&i2c0_function,
&ssp0_function,
&i2s0_function,
&i2s1_function,
&clcd_function,
&arm_gpio_function,
&smi_function,
&gmii_function,
&rgmii_function,
&smii_0_1_2_function,
&ras_mii_txclk_function,
&nand_function,
&keyboard_function,
&uart0_function,
&gpt0_function,
&gpt1_function,
&sdhci_function,
&cf_function,
&xd_function,
&touch_xy_function,
&uart1_function,
&uart2_3_function,
&uart4_function,
&uart5_function,
&rs485_0_1_tdm_0_1_function,
&i2c_1_2_function,
&i2c3_unction,
&i2c_4_5_function,
&i2c_6_7_function,
&can0_function,
&can1_function,
&pci_function,
&sata_function,
&ssp1_function,
&gpt64_function,
};
static struct spear_pinctrl_machdata spear1310_machdata = {
.pins = spear1310_pins,
.npins = ARRAY_SIZE(spear1310_pins),
.groups = spear1310_pingroups,
.ngroups = ARRAY_SIZE(spear1310_pingroups),
.functions = spear1310_functions,
.nfunctions = ARRAY_SIZE(spear1310_functions),
.modes_supported = false,
};
static struct of_device_id spear1310_pinctrl_of_match[] __devinitdata = {
{
.compatible = "st,spear1310-pinmux",
},
{},
};
static int __devinit spear1310_pinctrl_probe(struct platform_device *pdev)
{
return spear_pinctrl_probe(pdev, &spear1310_machdata);
}
static int __devexit spear1310_pinctrl_remove(struct platform_device *pdev)
{
return spear_pinctrl_remove(pdev);
}
static struct platform_driver spear1310_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = spear1310_pinctrl_of_match,
},
.probe = spear1310_pinctrl_probe,
.remove = __devexit_p(spear1310_pinctrl_remove),
};
static int __init spear1310_pinctrl_init(void)
{
return platform_driver_register(&spear1310_pinctrl_driver);
}
arch_initcall(spear1310_pinctrl_init);
static void __exit spear1310_pinctrl_exit(void)
{
platform_driver_unregister(&spear1310_pinctrl_driver);
}
module_exit(spear1310_pinctrl_exit);
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
drivers/pinctrl/spear/pinctrl-spear1340.c 0 → 100644
View file @ 85ed41a7
/*
* Driver for the ST Microelectronics SPEAr1340 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear1340-pinmux"
/* pins */
static const struct pinctrl_pin_desc spear1340_pins[] = {
SPEAR_PIN_0_TO_101,
SPEAR_PIN_102_TO_245,
PINCTRL_PIN(246, "PLGPIO246"),
PINCTRL_PIN(247, "PLGPIO247"),
PINCTRL_PIN(248, "PLGPIO248"),
PINCTRL_PIN(249, "PLGPIO249"),
PINCTRL_PIN(250, "PLGPIO250"),
PINCTRL_PIN(251, "PLGPIO251"),
};
/* In SPEAr1340 there are two levels of pad muxing */
/* - pads as gpio OR peripherals */
#define PAD_FUNCTION_EN_1 0x668
#define PAD_FUNCTION_EN_2 0x66C
#define PAD_FUNCTION_EN_3 0x670
#define PAD_FUNCTION_EN_4 0x674
#define PAD_FUNCTION_EN_5 0x690
#define PAD_FUNCTION_EN_6 0x694
#define PAD_FUNCTION_EN_7 0x698
#define PAD_FUNCTION_EN_8 0x69C
/* - If peripherals, then primary OR alternate peripheral */
#define PAD_SHARED_IP_EN_1 0x6A0
#define PAD_SHARED_IP_EN_2 0x6A4
/*
* Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
* registers with 32 bits each for handling gpio pads, register 8 has only 26
* relevant bits.
*/
/* macro's for making pads as gpio's */
#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
/* macro's for making pads as peripherals */
#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
#define I2C1_REG0_MASK 0x01080000
#define SPDIF_IN_REG0_MASK 0x00100000
#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
#define VIP_AND_CAM3_REG0_MASK 0xFC200000
#define VIP_AND_CAM3_REG1_MASK 0x0000000F
#define VIP_REG1_MASK 0x00001EF0
#define VIP_AND_CAM2_REG1_MASK 0x007FE100
#define VIP_AND_CAM1_REG1_MASK 0xFF800000
#define VIP_AND_CAM1_REG2_MASK 0x00000003
#define VIP_AND_CAM0_REG2_MASK 0x00001FFC
#define SMI_REG2_MASK 0x0021E000
#define SSP0_REG2_MASK 0x001E0000
#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
#define UART0_REG2_MASK 0x01800000
#define UART1_REG2_MASK 0x06000000
#define I2S_IN_REG2_MASK 0xF8000000
#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
#define I2S_OUT_REG3_MASK 0x000001EF
#define I2S_IN_REG3_MASK 0x00000010
#define GMAC_REG3_MASK 0xFFFFFE00
#define GMAC_REG4_MASK 0x0000001F
#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
#define SSP0_CS3_REG4_MASK 0x00000020
#define I2C0_REG4_MASK 0x000000C0
#define CEC0_REG4_MASK 0x00000100
#define CEC1_REG4_MASK 0x00000200
#define SPDIF_OUT_REG4_MASK 0x00000400
#define CLCD_REG4_MASK 0x7FFFF800
#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
#define MCIF_REG6_MASK 0xF8C00000
#define MCIF_REG7_MASK 0x000043FF
#define FSMC_8BIT_REG7_MASK 0x07FFBC00
/* other registers */
#define PERIP_CFG 0x42C
/* PERIP_CFG register masks */
#define SSP_CS_CTL_HW 0
#define SSP_CS_CTL_SW 1
#define SSP_CS_CTL_MASK 1
#define SSP_CS_CTL_SHIFT 21
#define SSP_CS_VAL_MASK 1
#define SSP_CS_VAL_SHIFT 20
#define SSP_CS_SEL_CS0 0
#define SSP_CS_SEL_CS1 1
#define SSP_CS_SEL_CS2 2
#define SSP_CS_SEL_MASK 3
#define SSP_CS_SEL_SHIFT 18
#define I2S_CHNL_2_0 (0)
#define I2S_CHNL_3_1 (1)
#define I2S_CHNL_5_1 (2)
#define I2S_CHNL_7_1 (3)
#define I2S_CHNL_PLAY_SHIFT (4)
#define I2S_CHNL_PLAY_MASK (3 << 4)
#define I2S_CHNL_REC_SHIFT (6)
#define I2S_CHNL_REC_MASK (3 << 6)
#define SPDIF_OUT_ENB_MASK (1 << 2)
#define SPDIF_OUT_ENB_SHIFT 2
#define MCIF_SEL_SD 1
#define MCIF_SEL_CF 2
#define MCIF_SEL_XD 3
#define MCIF_SEL_MASK 3
#define MCIF_SEL_SHIFT 0
#define GMAC_CLK_CFG 0x248
#define GMAC_PHY_IF_GMII_VAL (0 << 3)
#define GMAC_PHY_IF_RGMII_VAL (1 << 3)
#define GMAC_PHY_IF_SGMII_VAL (2 << 3)
#define GMAC_PHY_IF_RMII_VAL (4 << 3)
#define GMAC_PHY_IF_SEL_MASK (7 << 3)
#define GMAC_PHY_INPUT_ENB_VAL 0
#define GMAC_PHY_SYNT_ENB_VAL 1
#define GMAC_PHY_CLK_MASK 1
#define GMAC_PHY_CLK_SHIFT 2
#define GMAC_PHY_125M_PAD_VAL 0
#define GMAC_PHY_PLL2_VAL 1
#define GMAC_PHY_OSC3_VAL 2
#define GMAC_PHY_INPUT_CLK_MASK 3
#define GMAC_PHY_INPUT_CLK_SHIFT 0
#define PCIE_SATA_CFG 0x424
/* PCIE CFG MASks */
#define PCIE_CFG_DEVICE_PRESENT (1 << 11)
#define PCIE_CFG_POWERUP_RESET (1 << 10)
#define PCIE_CFG_CORE_CLK_EN (1 << 9)
#define PCIE_CFG_AUX_CLK_EN (1 << 8)
#define SATA_CFG_TX_CLK_EN (1 << 4)
#define SATA_CFG_RX_CLK_EN (1 << 3)
#define SATA_CFG_POWERUP_RESET (1 << 2)
#define SATA_CFG_PM_CLK_EN (1 << 1)
#define PCIE_SATA_SEL_PCIE (0)
#define PCIE_SATA_SEL_SATA (1)
#define SATA_PCIE_CFG_MASK 0xF1F
#define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
PCIE_CFG_DEVICE_PRESENT)
#define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
SATA_CFG_TX_CLK_EN)
/* Macro's for second level of pmx - pads as primary OR alternate peripheral */
/* Write 0 to enable FSMC_16_BIT */
#define KBD_ROW_COL_MASK (1 << 0)
/* Write 0 to enable UART0_ENH */
#define GPT_MASK (1 << 1) /* Only clk & cpt */
/* Write 0 to enable PWM1 */
#define KBD_COL5_MASK (1 << 2)
/* Write 0 to enable PWM2 */
#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
/* Write 0 to enable PWM3 */
#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
/* Write 0 to enable PWM0 */
#define SSP0_CS1_MASK (1 << 5)
/* Write 0 to enable VIP */
#define CAM3_MASK (1 << 6)
/* Write 0 to enable VIP */
#define CAM2_MASK (1 << 7)
/* Write 0 to enable VIP */
#define CAM1_MASK (1 << 8)
/* Write 0 to enable VIP */
#define CAM0_MASK (1 << 9)
/* Write 0 to enable TS */
#define SSP0_CS2_MASK (1 << 10)
/* Write 0 to enable FSMC PNOR */
#define MCIF_MASK (1 << 11)
/* Write 0 to enable CLCD */
#define ARM_TRACE_MASK (1 << 12)
/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
#define MIPHY_DBG_MASK (1 << 13)
/*
* Pad multiplexing for making all pads as gpio's. This is done to override the
* values passed from bootloader and start from scratch.
*/
static const unsigned pads_as_gpio_pins[] = { 251 };
static struct spear_muxreg pads_as_gpio_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PADS_AS_GPIO_REG0_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_4,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_8,
.mask = PADS_AS_GPIO_REG7_MASK,
.val = 0x0,
},
};
static struct spear_modemux pads_as_gpio_modemux[] = {
{
.muxregs = pads_as_gpio_muxreg,
.nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
},
};
static struct spear_pingroup pads_as_gpio_pingroup = {
.name = "pads_as_gpio_grp",
.pins = pads_as_gpio_pins,
.npins = ARRAY_SIZE(pads_as_gpio_pins),
.modemuxs = pads_as_gpio_modemux,
.nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
};
static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
static struct spear_function pads_as_gpio_function = {
.name = "pads_as_gpio",
.groups = pads_as_gpio_grps,
.ngroups = ARRAY_SIZE(pads_as_gpio_grps),
};
/* Pad multiplexing for fsmc_8bit device */
static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
241, 242, 243, 244, 245, 246, 247, 248, 249 };
static struct spear_muxreg fsmc_8bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_8,
.mask = FSMC_8BIT_REG7_MASK,
.val = FSMC_8BIT_REG7_MASK,
}
};
static struct spear_modemux fsmc_8bit_modemux[] = {
{
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
},
};
static struct spear_pingroup fsmc_8bit_pingroup = {
.name = "fsmc_8bit_grp",
.pins = fsmc_8bit_pins,
.npins = ARRAY_SIZE(fsmc_8bit_pins),
.modemuxs = fsmc_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
};
/* Pad multiplexing for fsmc_16bit device */
static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
static struct spear_muxreg fsmc_16bit_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_ROW_COL_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
.val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
},
};
static struct spear_modemux fsmc_16bit_modemux[] = {
{
.muxregs = fsmc_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
},
};
static struct spear_pingroup fsmc_16bit_pingroup = {
.name = "fsmc_16bit_grp",
.pins = fsmc_16bit_pins,
.npins = ARRAY_SIZE(fsmc_16bit_pins),
.modemuxs = fsmc_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
};
/* pad multiplexing for fsmc_pnor device */
static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
215, 216, 217 };
static struct spear_muxreg fsmc_pnor_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = MCIF_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
.val = FSMC_PNOR_AND_MCIF_REG6_MASK,
},
};
static struct spear_modemux fsmc_pnor_modemux[] = {
{
.muxregs = fsmc_pnor_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
},
};
static struct spear_pingroup fsmc_pnor_pingroup = {
.name = "fsmc_pnor_grp",
.pins = fsmc_pnor_pins,
.npins = ARRAY_SIZE(fsmc_pnor_pins),
.modemuxs = fsmc_pnor_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
"fsmc_pnor_grp" };
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* pad multiplexing for keyboard rows-cols device */
static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10 };
static struct spear_muxreg keyboard_row_col_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_ROW_COL_MASK,
.val = KBD_ROW_COL_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
.val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
},
};
static struct spear_modemux keyboard_row_col_modemux[] = {
{
.muxregs = keyboard_row_col_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
},
};
static struct spear_pingroup keyboard_row_col_pingroup = {
.name = "keyboard_row_col_grp",
.pins = keyboard_row_col_pins,
.npins = ARRAY_SIZE(keyboard_row_col_pins),
.modemuxs = keyboard_row_col_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
};
/* pad multiplexing for keyboard col5 device */
static const unsigned keyboard_col5_pins[] = { 17 };
static struct spear_muxreg keyboard_col5_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_COL5_MASK,
.val = KBD_COL5_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM1_AND_KBD_COL5_REG0_MASK,
.val = PWM1_AND_KBD_COL5_REG0_MASK,
},
};
static struct spear_modemux keyboard_col5_modemux[] = {
{
.muxregs = keyboard_col5_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
},
};
static struct spear_pingroup keyboard_col5_pingroup = {
.name = "keyboard_col5_grp",
.pins = keyboard_col5_pins,
.npins = ARRAY_SIZE(keyboard_col5_pins),
.modemuxs = keyboard_col5_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
};
static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
"keyboard_col5_grp" };
static struct spear_function keyboard_function = {
.name = "keyboard",
.groups = keyboard_grps,
.ngroups = ARRAY_SIZE(keyboard_grps),
};
/* pad multiplexing for spdif_in device */
static const unsigned spdif_in_pins[] = { 19 };
static struct spear_muxreg spdif_in_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = SPDIF_IN_REG0_MASK,
.val = SPDIF_IN_REG0_MASK,
},
};
static struct spear_modemux spdif_in_modemux[] = {
{
.muxregs = spdif_in_muxreg,
.nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
},
};
static struct spear_pingroup spdif_in_pingroup = {
.name = "spdif_in_grp",
.pins = spdif_in_pins,
.npins = ARRAY_SIZE(spdif_in_pins),
.modemuxs = spdif_in_modemux,
.nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
};
static const char *const spdif_in_grps[] = { "spdif_in_grp" };
static struct spear_function spdif_in_function = {
.name = "spdif_in",
.groups = spdif_in_grps,
.ngroups = ARRAY_SIZE(spdif_in_grps),
};
/* pad multiplexing for spdif_out device */
static const unsigned spdif_out_pins[] = { 137 };
static struct spear_muxreg spdif_out_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = SPDIF_OUT_REG4_MASK,
.val = SPDIF_OUT_REG4_MASK,
}, {
.reg = PERIP_CFG,
.mask = SPDIF_OUT_ENB_MASK,
.val = SPDIF_OUT_ENB_MASK,
}
};
static struct spear_modemux spdif_out_modemux[] = {
{
.muxregs = spdif_out_muxreg,
.nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
},
};
static struct spear_pingroup spdif_out_pingroup = {
.name = "spdif_out_grp",
.pins = spdif_out_pins,
.npins = ARRAY_SIZE(spdif_out_pins),
.modemuxs = spdif_out_modemux,
.nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
};
static const char *const spdif_out_grps[] = { "spdif_out_grp" };
static struct spear_function spdif_out_function = {
.name = "spdif_out",
.groups = spdif_out_grps,
.ngroups = ARRAY_SIZE(spdif_out_grps),
};
/* pad multiplexing for gpt_0_1 device */
static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
static struct spear_muxreg gpt_0_1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
.val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = UART0_ENH_AND_GPT_REG0_MASK |
PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
.val = UART0_ENH_AND_GPT_REG0_MASK |
PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
},
};
static struct spear_modemux gpt_0_1_modemux[] = {
{
.muxregs = gpt_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
},
};
static struct spear_pingroup gpt_0_1_pingroup = {
.name = "gpt_0_1_grp",
.pins = gpt_0_1_pins,
.npins = ARRAY_SIZE(gpt_0_1_pins),
.modemuxs = gpt_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
};
static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
static struct spear_function gpt_0_1_function = {
.name = "gpt_0_1",
.groups = gpt_0_1_grps,
.ngroups = ARRAY_SIZE(gpt_0_1_grps),
};
/* pad multiplexing for pwm0 device */
static const unsigned pwm0_pins[] = { 24 };
static struct spear_muxreg pwm0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM0_AND_SSP0_CS1_REG0_MASK,
.val = PWM0_AND_SSP0_CS1_REG0_MASK,
},
};
static struct spear_modemux pwm0_modemux[] = {
{
.muxregs = pwm0_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_muxreg),
},
};
static struct spear_pingroup pwm0_pingroup = {
.name = "pwm0_grp",
.pins = pwm0_pins,
.npins = ARRAY_SIZE(pwm0_pins),
.modemuxs = pwm0_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_modemux),
};
/* pad multiplexing for pwm1 device */
static const unsigned pwm1_pins[] = { 17 };
static struct spear_muxreg pwm1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_COL5_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM1_AND_KBD_COL5_REG0_MASK,
.val = PWM1_AND_KBD_COL5_REG0_MASK,
},
};
static struct spear_modemux pwm1_modemux[] = {
{
.muxregs = pwm1_muxreg,
.nmuxregs = ARRAY_SIZE(pwm1_muxreg),
},
};
static struct spear_pingroup pwm1_pingroup = {
.name = "pwm1_grp",
.pins = pwm1_pins,
.npins = ARRAY_SIZE(pwm1_pins),
.modemuxs = pwm1_modemux,
.nmodemuxs = ARRAY_SIZE(pwm1_modemux),
};
/* pad multiplexing for pwm2 device */
static const unsigned pwm2_pins[] = { 21 };
static struct spear_muxreg pwm2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT0_TMR0_CPT_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
.val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
},
};
static struct spear_modemux pwm2_modemux[] = {
{
.muxregs = pwm2_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_muxreg),
},
};
static struct spear_pingroup pwm2_pingroup = {
.name = "pwm2_grp",
.pins = pwm2_pins,
.npins = ARRAY_SIZE(pwm2_pins),
.modemuxs = pwm2_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_modemux),
};
/* pad multiplexing for pwm3 device */
static const unsigned pwm3_pins[] = { 22 };
static struct spear_muxreg pwm3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT0_TMR1_CLK_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
.val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
},
};
static struct spear_modemux pwm3_modemux[] = {
{
.muxregs = pwm3_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
},
};
static struct spear_pingroup pwm3_pingroup = {
.name = "pwm3_grp",
.pins = pwm3_pins,
.npins = ARRAY_SIZE(pwm3_pins),
.modemuxs = pwm3_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_modemux),
};
static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp" };
static struct spear_function pwm_function = {
.name = "pwm",
.groups = pwm_grps,
.ngroups = ARRAY_SIZE(pwm_grps),
};
/* pad multiplexing for vip_mux device */
static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
static struct spear_muxreg vip_mux_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_REG1_MASK,
.val = VIP_REG1_MASK,
},
};
static struct spear_modemux vip_mux_modemux[] = {
{
.muxregs = vip_mux_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
},
};
static struct spear_pingroup vip_mux_pingroup = {
.name = "vip_mux_grp",
.pins = vip_mux_pins,
.npins = ARRAY_SIZE(vip_mux_pins),
.modemuxs = vip_mux_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
};
/* pad multiplexing for vip_mux_cam0 (disables cam0) device */
static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
73, 74, 75 };
static struct spear_muxreg vip_mux_cam0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM0_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM0_REG2_MASK,
.val = VIP_AND_CAM0_REG2_MASK,
},
};
static struct spear_modemux vip_mux_cam0_modemux[] = {
{
.muxregs = vip_mux_cam0_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
},
};
static struct spear_pingroup vip_mux_cam0_pingroup = {
.name = "vip_mux_cam0_grp",
.pins = vip_mux_cam0_pins,
.npins = ARRAY_SIZE(vip_mux_cam0_pins),
.modemuxs = vip_mux_cam0_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
};
/* pad multiplexing for vip_mux_cam1 (disables cam1) device */
static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
62, 63, 64 };
static struct spear_muxreg vip_mux_cam1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM1_REG1_MASK,
.val = VIP_AND_CAM1_REG1_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM1_REG2_MASK,
.val = VIP_AND_CAM1_REG2_MASK,
},
};
static struct spear_modemux vip_mux_cam1_modemux[] = {
{
.muxregs = vip_mux_cam1_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
},
};
static struct spear_pingroup vip_mux_cam1_pingroup = {
.name = "vip_mux_cam1_grp",
.pins = vip_mux_cam1_pins,
.npins = ARRAY_SIZE(vip_mux_cam1_pins),
.modemuxs = vip_mux_cam1_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
};
/* pad multiplexing for vip_mux_cam2 (disables cam2) device */
static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53 };
static struct spear_muxreg vip_mux_cam2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM2_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM2_REG1_MASK,
.val = VIP_AND_CAM2_REG1_MASK,
},
};
static struct spear_modemux vip_mux_cam2_modemux[] = {
{
.muxregs = vip_mux_cam2_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
},
};
static struct spear_pingroup vip_mux_cam2_pingroup = {
.name = "vip_mux_cam2_grp",
.pins = vip_mux_cam2_pins,
.npins = ARRAY_SIZE(vip_mux_cam2_pins),
.modemuxs = vip_mux_cam2_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
};
/* pad multiplexing for vip_mux_cam3 (disables cam3) device */
static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34 };
static struct spear_muxreg vip_mux_cam3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM3_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = VIP_AND_CAM3_REG0_MASK,
.val = VIP_AND_CAM3_REG0_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM3_REG1_MASK,
.val = VIP_AND_CAM3_REG1_MASK,
},
};
static struct spear_modemux vip_mux_cam3_modemux[] = {
{
.muxregs = vip_mux_cam3_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
},
};
static struct spear_pingroup vip_mux_cam3_pingroup = {
.name = "vip_mux_cam3_grp",
.pins = vip_mux_cam3_pins,
.npins = ARRAY_SIZE(vip_mux_cam3_pins),
.modemuxs = vip_mux_cam3_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
};
static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
"vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
static struct spear_function vip_function = {
.name = "vip",
.groups = vip_grps,
.ngroups = ARRAY_SIZE(vip_grps),
};
/* pad multiplexing for cam0 device */
static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
};
static struct spear_muxreg cam0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM0_MASK,
.val = CAM0_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM0_REG2_MASK,
.val = VIP_AND_CAM0_REG2_MASK,
},
};
static struct spear_modemux cam0_modemux[] = {
{
.muxregs = cam0_muxreg,
.nmuxregs = ARRAY_SIZE(cam0_muxreg),
},
};
static struct spear_pingroup cam0_pingroup = {
.name = "cam0_grp",
.pins = cam0_pins,
.npins = ARRAY_SIZE(cam0_pins),
.modemuxs = cam0_modemux,
.nmodemuxs = ARRAY_SIZE(cam0_modemux),
};
static const char *const cam0_grps[] = { "cam0_grp" };
static struct spear_function cam0_function = {
.name = "cam0",
.groups = cam0_grps,
.ngroups = ARRAY_SIZE(cam0_grps),
};
/* pad multiplexing for cam1 device */
static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
};
static struct spear_muxreg cam1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM1_MASK,
.val = CAM1_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM1_REG1_MASK,
.val = VIP_AND_CAM1_REG1_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM1_REG2_MASK,
.val = VIP_AND_CAM1_REG2_MASK,
},
};
static struct spear_modemux cam1_modemux[] = {
{
.muxregs = cam1_muxreg,
.nmuxregs = ARRAY_SIZE(cam1_muxreg),
},
};
static struct spear_pingroup cam1_pingroup = {
.name = "cam1_grp",
.pins = cam1_pins,
.npins = ARRAY_SIZE(cam1_pins),
.modemuxs = cam1_modemux,
.nmodemuxs = ARRAY_SIZE(cam1_modemux),
};
static const char *const cam1_grps[] = { "cam1_grp" };
static struct spear_function cam1_function = {
.name = "cam1",
.groups = cam1_grps,
.ngroups = ARRAY_SIZE(cam1_grps),
};
/* pad multiplexing for cam2 device */
static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
};
static struct spear_muxreg cam2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM2_MASK,
.val = CAM2_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM2_REG1_MASK,
.val = VIP_AND_CAM2_REG1_MASK,
},
};
static struct spear_modemux cam2_modemux[] = {
{
.muxregs = cam2_muxreg,
.nmuxregs = ARRAY_SIZE(cam2_muxreg),
},
};
static struct spear_pingroup cam2_pingroup = {
.name = "cam2_grp",
.pins = cam2_pins,
.npins = ARRAY_SIZE(cam2_pins),
.modemuxs = cam2_modemux,
.nmodemuxs = ARRAY_SIZE(cam2_modemux),
};
static const char *const cam2_grps[] = { "cam2_grp" };
static struct spear_function cam2_function = {
.name = "cam2",
.groups = cam2_grps,
.ngroups = ARRAY_SIZE(cam2_grps),
};
/* pad multiplexing for cam3 device */
static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
};
static struct spear_muxreg cam3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM3_MASK,
.val = CAM3_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = VIP_AND_CAM3_REG0_MASK,
.val = VIP_AND_CAM3_REG0_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM3_REG1_MASK,
.val = VIP_AND_CAM3_REG1_MASK,
},
};
static struct spear_modemux cam3_modemux[] = {
{
.muxregs = cam3_muxreg,
.nmuxregs = ARRAY_SIZE(cam3_muxreg),
},
};
static struct spear_pingroup cam3_pingroup = {
.name = "cam3_grp",
.pins = cam3_pins,
.npins = ARRAY_SIZE(cam3_pins),
.modemuxs = cam3_modemux,
.nmodemuxs = ARRAY_SIZE(cam3_modemux),
};
static const char *const cam3_grps[] = { "cam3_grp" };
static struct spear_function cam3_function = {
.name = "cam3",
.groups = cam3_grps,
.ngroups = ARRAY_SIZE(cam3_grps),
};
/* pad multiplexing for smi device */
static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
static struct spear_muxreg smi_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = SMI_REG2_MASK,
.val = SMI_REG2_MASK,
},
};
static struct spear_modemux smi_modemux[] = {
{
.muxregs = smi_muxreg,
.nmuxregs = ARRAY_SIZE(smi_muxreg),
},
};
static struct spear_pingroup smi_pingroup = {
.name = "smi_grp",
.pins = smi_pins,
.npins = ARRAY_SIZE(smi_pins),
.modemuxs = smi_modemux,
.nmodemuxs = ARRAY_SIZE(smi_modemux),
};
static const char *const smi_grps[] = { "smi_grp" };
static struct spear_function smi_function = {
.name = "smi",
.groups = smi_grps,
.ngroups = ARRAY_SIZE(smi_grps),
};
/* pad multiplexing for ssp0 device */
static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
static struct spear_muxreg ssp0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = SSP0_REG2_MASK,
.val = SSP0_REG2_MASK,
},
};
static struct spear_modemux ssp0_modemux[] = {
{
.muxregs = ssp0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
},
};
static struct spear_pingroup ssp0_pingroup = {
.name = "ssp0_grp",
.pins = ssp0_pins,
.npins = ARRAY_SIZE(ssp0_pins),
.modemuxs = ssp0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
};
/* pad multiplexing for ssp0_cs1 device */
static const unsigned ssp0_cs1_pins[] = { 24 };
static struct spear_muxreg ssp0_cs1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS1_MASK,
.val = SSP0_CS1_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM0_AND_SSP0_CS1_REG0_MASK,
.val = PWM0_AND_SSP0_CS1_REG0_MASK,
},
};
static struct spear_modemux ssp0_cs1_modemux[] = {
{
.muxregs = ssp0_cs1_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
},
};
static struct spear_pingroup ssp0_cs1_pingroup = {
.name = "ssp0_cs1_grp",
.pins = ssp0_cs1_pins,
.npins = ARRAY_SIZE(ssp0_cs1_pins),
.modemuxs = ssp0_cs1_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
};
/* pad multiplexing for ssp0_cs2 device */
static const unsigned ssp0_cs2_pins[] = { 85 };
static struct spear_muxreg ssp0_cs2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS2_MASK,
.val = SSP0_CS2_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = TS_AND_SSP0_CS2_REG2_MASK,
.val = TS_AND_SSP0_CS2_REG2_MASK,
},
};
static struct spear_modemux ssp0_cs2_modemux[] = {
{
.muxregs = ssp0_cs2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
},
};
static struct spear_pingroup ssp0_cs2_pingroup = {
.name = "ssp0_cs2_grp",
.pins = ssp0_cs2_pins,
.npins = ARRAY_SIZE(ssp0_cs2_pins),
.modemuxs = ssp0_cs2_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
};
/* pad multiplexing for ssp0_cs3 device */
static const unsigned ssp0_cs3_pins[] = { 132 };
static struct spear_muxreg ssp0_cs3_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = SSP0_CS3_REG4_MASK,
.val = SSP0_CS3_REG4_MASK,
},
};
static struct spear_modemux ssp0_cs3_modemux[] = {
{
.muxregs = ssp0_cs3_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
},
};
static struct spear_pingroup ssp0_cs3_pingroup = {
.name = "ssp0_cs3_grp",
.pins = ssp0_cs3_pins,
.npins = ARRAY_SIZE(ssp0_cs3_pins),
.modemuxs = ssp0_cs3_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
};
static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp" };
static struct spear_function ssp0_function = {
.name = "ssp0",
.groups = ssp0_grps,
.ngroups = ARRAY_SIZE(ssp0_grps),
};
/* pad multiplexing for uart0 device */
static const unsigned uart0_pins[] = { 86, 87 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = UART0_REG2_MASK,
.val = UART0_REG2_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
static struct spear_pingroup uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
/* pad multiplexing for uart0_enh device */
static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
static struct spear_muxreg uart0_enh_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = UART0_ENH_AND_GPT_REG0_MASK,
.val = UART0_ENH_AND_GPT_REG0_MASK,
},
};
static struct spear_modemux uart0_enh_modemux[] = {
{
.muxregs = uart0_enh_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
},
};
static struct spear_pingroup uart0_enh_pingroup = {
.name = "uart0_enh_grp",
.pins = uart0_enh_pins,
.npins = ARRAY_SIZE(uart0_enh_pins),
.modemuxs = uart0_enh_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
static struct spear_function uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* pad multiplexing for uart1 device */
static const unsigned uart1_pins[] = { 88, 89 };
static struct spear_muxreg uart1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = UART1_REG2_MASK,
.val = UART1_REG2_MASK,
},
};
static struct spear_modemux uart1_modemux[] = {
{
.muxregs = uart1_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
},
};
static struct spear_pingroup uart1_pingroup = {
.name = "uart1_grp",
.pins = uart1_pins,
.npins = ARRAY_SIZE(uart1_pins),
.modemuxs = uart1_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
};
static const char *const uart1_grps[] = { "uart1_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* pad multiplexing for i2s_in device */
static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
static struct spear_muxreg i2s_in_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = I2S_IN_REG2_MASK,
.val = I2S_IN_REG2_MASK,
}, {
.reg = PAD_FUNCTION_EN_4,
.mask = I2S_IN_REG3_MASK,
.val = I2S_IN_REG3_MASK,
},
};
static struct spear_modemux i2s_in_modemux[] = {
{
.muxregs = i2s_in_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
},
};
static struct spear_pingroup i2s_in_pingroup = {
.name = "i2s_in_grp",
.pins = i2s_in_pins,
.npins = ARRAY_SIZE(i2s_in_pins),
.modemuxs = i2s_in_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
};
/* pad multiplexing for i2s_out device */
static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
static struct spear_muxreg i2s_out_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_4,
.mask = I2S_OUT_REG3_MASK,
.val = I2S_OUT_REG3_MASK,
},
};
static struct spear_modemux i2s_out_modemux[] = {
{
.muxregs = i2s_out_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
},
};
static struct spear_pingroup i2s_out_pingroup = {
.name = "i2s_out_grp",
.pins = i2s_out_pins,
.npins = ARRAY_SIZE(i2s_out_pins),
.modemuxs = i2s_out_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
};
static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
static struct spear_function i2s_function = {
.name = "i2s",
.groups = i2s_grps,
.ngroups = ARRAY_SIZE(i2s_grps),
};
/* pad multiplexing for gmac device */
static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
126, 127, 128, 129, 130, 131 };
#define GMAC_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_4, \
.mask = GMAC_REG3_MASK, \
.val = GMAC_REG3_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_5, \
.mask = GMAC_REG4_MASK, \
.val = GMAC_REG4_MASK, \
}
/* pad multiplexing for gmii device */
static struct spear_muxreg gmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_GMII_VAL,
},
};
static struct spear_modemux gmii_modemux[] = {
{
.muxregs = gmii_muxreg,
.nmuxregs = ARRAY_SIZE(gmii_muxreg),
},
};
static struct spear_pingroup gmii_pingroup = {
.name = "gmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = gmii_modemux,
.nmodemuxs = ARRAY_SIZE(gmii_modemux),
};
/* pad multiplexing for rgmii device */
static struct spear_muxreg rgmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_RGMII_VAL,
},
};
static struct spear_modemux rgmii_modemux[] = {
{
.muxregs = rgmii_muxreg,
.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
},
};
static struct spear_pingroup rgmii_pingroup = {
.name = "rgmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = rgmii_modemux,
.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
};
/* pad multiplexing for rmii device */
static struct spear_muxreg rmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_RMII_VAL,
},
};
static struct spear_modemux rmii_modemux[] = {
{
.muxregs = rmii_muxreg,
.nmuxregs = ARRAY_SIZE(rmii_muxreg),
},
};
static struct spear_pingroup rmii_pingroup = {
.name = "rmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = rmii_modemux,
.nmodemuxs = ARRAY_SIZE(rmii_modemux),
};
/* pad multiplexing for sgmii device */
static struct spear_muxreg sgmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_SGMII_VAL,
},
};
static struct spear_modemux sgmii_modemux[] = {
{
.muxregs = sgmii_muxreg,
.nmuxregs = ARRAY_SIZE(sgmii_muxreg),
},
};
static struct spear_pingroup sgmii_pingroup = {
.name = "sgmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = sgmii_modemux,
.nmodemuxs = ARRAY_SIZE(sgmii_modemux),
};
static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
"sgmii_grp" };
static struct spear_function gmac_function = {
.name = "gmac",
.groups = gmac_grps,
.ngroups = ARRAY_SIZE(gmac_grps),
};
/* pad multiplexing for i2c0 device */
static const unsigned i2c0_pins[] = { 133, 134 };
static struct spear_muxreg i2c0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = I2C0_REG4_MASK,
.val = I2C0_REG4_MASK,
},
};
static struct spear_modemux i2c0_modemux[] = {
{
.muxregs = i2c0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
},
};
static struct spear_pingroup i2c0_pingroup = {
.name = "i2c0_grp",
.pins = i2c0_pins,
.npins = ARRAY_SIZE(i2c0_pins),
.modemuxs = i2c0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
};
static const char *const i2c0_grps[] = { "i2c0_grp" };
static struct spear_function i2c0_function = {
.name = "i2c0",
.groups = i2c0_grps,
.ngroups = ARRAY_SIZE(i2c0_grps),
};
/* pad multiplexing for i2c1 device */
static const unsigned i2c1_pins[] = { 18, 23 };
static struct spear_muxreg i2c1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = I2C1_REG0_MASK,
.val = I2C1_REG0_MASK,
},
};
static struct spear_modemux i2c1_modemux[] = {
{
.muxregs = i2c1_muxreg,
.nmuxregs = ARRAY_SIZE(i2c1_muxreg),
},
};
static struct spear_pingroup i2c1_pingroup = {
.name = "i2c1_grp",
.pins = i2c1_pins,
.npins = ARRAY_SIZE(i2c1_pins),
.modemuxs = i2c1_modemux,
.nmodemuxs = ARRAY_SIZE(i2c1_modemux),
};
static const char *const i2c1_grps[] = { "i2c1_grp" };
static struct spear_function i2c1_function = {
.name = "i2c1",
.groups = i2c1_grps,
.ngroups = ARRAY_SIZE(i2c1_grps),
};
/* pad multiplexing for cec0 device */
static const unsigned cec0_pins[] = { 135 };
static struct spear_muxreg cec0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = CEC0_REG4_MASK,
.val = CEC0_REG4_MASK,
},
};
static struct spear_modemux cec0_modemux[] = {
{
.muxregs = cec0_muxreg,
.nmuxregs = ARRAY_SIZE(cec0_muxreg),
},
};
static struct spear_pingroup cec0_pingroup = {
.name = "cec0_grp",
.pins = cec0_pins,
.npins = ARRAY_SIZE(cec0_pins),
.modemuxs = cec0_modemux,
.nmodemuxs = ARRAY_SIZE(cec0_modemux),
};
static const char *const cec0_grps[] = { "cec0_grp" };
static struct spear_function cec0_function = {
.name = "cec0",
.groups = cec0_grps,
.ngroups = ARRAY_SIZE(cec0_grps),
};
/* pad multiplexing for cec1 device */
static const unsigned cec1_pins[] = { 136 };
static struct spear_muxreg cec1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = CEC1_REG4_MASK,
.val = CEC1_REG4_MASK,
},
};
static struct spear_modemux cec1_modemux[] = {
{
.muxregs = cec1_muxreg,
.nmuxregs = ARRAY_SIZE(cec1_muxreg),
},
};
static struct spear_pingroup cec1_pingroup = {
.name = "cec1_grp",
.pins = cec1_pins,
.npins = ARRAY_SIZE(cec1_pins),
.modemuxs = cec1_modemux,
.nmodemuxs = ARRAY_SIZE(cec1_modemux),
};
static const char *const cec1_grps[] = { "cec1_grp" };
static struct spear_function cec1_function = {
.name = "cec1",
.groups = cec1_grps,
.ngroups = ARRAY_SIZE(cec1_grps),
};
/* pad multiplexing for mcif devices */
static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 237 };
#define MCIF_MUXREG \
{ \
.reg = PAD_SHARED_IP_EN_1, \
.mask = MCIF_MASK, \
.val = MCIF_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_7, \
.mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
.val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_8, \
.mask = MCIF_REG7_MASK, \
.val = MCIF_REG7_MASK, \
}
/* Pad multiplexing for sdhci device */
static struct spear_muxreg sdhci_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_SD,
},
};
static struct spear_modemux sdhci_modemux[] = {
{
.muxregs = sdhci_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
},
};
static struct spear_pingroup sdhci_pingroup = {
.name = "sdhci_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = sdhci_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* Pad multiplexing for cf device */
static struct spear_muxreg cf_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_CF,
},
};
static struct spear_modemux cf_modemux[] = {
{
.muxregs = cf_muxreg,
.nmuxregs = ARRAY_SIZE(cf_muxreg),
},
};
static struct spear_pingroup cf_pingroup = {
.name = "cf_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = cf_modemux,
.nmodemuxs = ARRAY_SIZE(cf_modemux),
};
static const char *const cf_grps[] = { "cf_grp" };
static struct spear_function cf_function = {
.name = "cf",
.groups = cf_grps,
.ngroups = ARRAY_SIZE(cf_grps),
};
/* Pad multiplexing for xd device */
static struct spear_muxreg xd_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_XD,
},
};
static struct spear_modemux xd_modemux[] = {
{
.muxregs = xd_muxreg,
.nmuxregs = ARRAY_SIZE(xd_muxreg),
},
};
static struct spear_pingroup xd_pingroup = {
.name = "xd_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = xd_modemux,
.nmodemuxs = ARRAY_SIZE(xd_modemux),
};
static const char *const xd_grps[] = { "xd_grp" };
static struct spear_function xd_function = {
.name = "xd",
.groups = xd_grps,
.ngroups = ARRAY_SIZE(xd_grps),
};
/* pad multiplexing for clcd device */
static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
188, 189, 190, 191 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
.val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = CLCD_AND_ARM_TRACE_REG5_MASK,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = CLCD_AND_ARM_TRACE_REG6_MASK,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
/* pad multiplexing for arm_trace device */
static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
193, 194, 195, 196, 197, 198, 199, 200 };
static struct spear_muxreg arm_trace_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK,
.val = ARM_TRACE_MASK,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_AND_ARM_TRACE_REG4_MASK,
.val = CLCD_AND_ARM_TRACE_REG4_MASK,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = CLCD_AND_ARM_TRACE_REG5_MASK,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = CLCD_AND_ARM_TRACE_REG6_MASK,
},
};
static struct spear_modemux arm_trace_modemux[] = {
{
.muxregs = arm_trace_muxreg,
.nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
},
};
static struct spear_pingroup arm_trace_pingroup = {
.name = "arm_trace_grp",
.pins = arm_trace_pins,
.npins = ARRAY_SIZE(arm_trace_pins),
.modemuxs = arm_trace_modemux,
.nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
};
static const char *const arm_trace_grps[] = { "arm_trace_grp" };
static struct spear_function arm_trace_function = {
.name = "arm_trace",
.groups = arm_trace_grps,
.ngroups = ARRAY_SIZE(arm_trace_grps),
};
/* pad multiplexing for miphy_dbg device */
static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
static struct spear_muxreg miphy_dbg_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = MIPHY_DBG_MASK,
.val = MIPHY_DBG_MASK,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
.val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
},
};
static struct spear_modemux miphy_dbg_modemux[] = {
{
.muxregs = miphy_dbg_muxreg,
.nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
},
};
static struct spear_pingroup miphy_dbg_pingroup = {
.name = "miphy_dbg_grp",
.pins = miphy_dbg_pins,
.npins = ARRAY_SIZE(miphy_dbg_pins),
.modemuxs = miphy_dbg_modemux,
.nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
};
static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
static struct spear_function miphy_dbg_function = {
.name = "miphy_dbg",
.groups = miphy_dbg_grps,
.ngroups = ARRAY_SIZE(miphy_dbg_grps),
};
/* pad multiplexing for pcie device */
static const unsigned pcie_pins[] = { 250 };
static struct spear_muxreg pcie_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_PCIE_CFG_MASK,
.val = PCIE_CFG_VAL,
},
};
static struct spear_modemux pcie_modemux[] = {
{
.muxregs = pcie_muxreg,
.nmuxregs = ARRAY_SIZE(pcie_muxreg),
},
};
static struct spear_pingroup pcie_pingroup = {
.name = "pcie_grp",
.pins = pcie_pins,
.npins = ARRAY_SIZE(pcie_pins),
.modemuxs = pcie_modemux,
.nmodemuxs = ARRAY_SIZE(pcie_modemux),
};
static const char *const pcie_grps[] = { "pcie_grp" };
static struct spear_function pcie_function = {
.name = "pcie",
.groups = pcie_grps,
.ngroups = ARRAY_SIZE(pcie_grps),
};
/* pad multiplexing for sata device */
static const unsigned sata_pins[] = { 250 };
static struct spear_muxreg sata_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_PCIE_CFG_MASK,
.val = SATA_CFG_VAL,
},
};
static struct spear_modemux sata_modemux[] = {
{
.muxregs = sata_muxreg,
.nmuxregs = ARRAY_SIZE(sata_muxreg),
},
};
static struct spear_pingroup sata_pingroup = {
.name = "sata_grp",
.pins = sata_pins,
.npins = ARRAY_SIZE(sata_pins),
.modemuxs = sata_modemux,
.nmodemuxs = ARRAY_SIZE(sata_modemux),
};
static const char *const sata_grps[] = { "sata_grp" };
static struct spear_function sata_function = {
.name = "sata",
.groups = sata_grps,
.ngroups = ARRAY_SIZE(sata_grps),
};
/* pingroups */
static struct spear_pingroup *spear1340_pingroups[] = {
&pads_as_gpio_pingroup,
&fsmc_8bit_pingroup,
&fsmc_16bit_pingroup,
&fsmc_pnor_pingroup,
&keyboard_row_col_pingroup,
&keyboard_col5_pingroup,
&spdif_in_pingroup,
&spdif_out_pingroup,
&gpt_0_1_pingroup,
&pwm0_pingroup,
&pwm1_pingroup,
&pwm2_pingroup,
&pwm3_pingroup,
&vip_mux_pingroup,
&vip_mux_cam0_pingroup,
&vip_mux_cam1_pingroup,
&vip_mux_cam2_pingroup,
&vip_mux_cam3_pingroup,
&cam0_pingroup,
&cam1_pingroup,
&cam2_pingroup,
&cam3_pingroup,
&smi_pingroup,
&ssp0_pingroup,
&ssp0_cs1_pingroup,
&ssp0_cs2_pingroup,
&ssp0_cs3_pingroup,
&uart0_pingroup,
&uart0_enh_pingroup,
&uart1_pingroup,
&i2s_in_pingroup,
&i2s_out_pingroup,
&gmii_pingroup,
&rgmii_pingroup,
&rmii_pingroup,
&sgmii_pingroup,
&i2c0_pingroup,
&i2c1_pingroup,
&cec0_pingroup,
&cec1_pingroup,
&sdhci_pingroup,
&cf_pingroup,
&xd_pingroup,
&clcd_pingroup,
&arm_trace_pingroup,
&miphy_dbg_pingroup,
&pcie_pingroup,
&sata_pingroup,
};
/* functions */
static struct spear_function *spear1340_functions[] = {
&pads_as_gpio_function,
&fsmc_function,
&keyboard_function,
&spdif_in_function,
&spdif_out_function,
&gpt_0_1_function,
&pwm_function,
&vip_function,
&cam0_function,
&cam1_function,
&cam2_function,
&cam3_function,
&smi_function,
&ssp0_function,
&uart0_function,
&uart1_function,
&i2s_function,
&gmac_function,
&i2c0_function,
&i2c1_function,
&cec0_function,
&cec1_function,
&sdhci_function,
&cf_function,
&xd_function,
&clcd_function,
&arm_trace_function,
&miphy_dbg_function,
&pcie_function,
&sata_function,
};
static struct spear_pinctrl_machdata spear1340_machdata = {
.pins = spear1340_pins,
.npins = ARRAY_SIZE(spear1340_pins),
.groups = spear1340_pingroups,
.ngroups = ARRAY_SIZE(spear1340_pingroups),
.functions = spear1340_functions,
.nfunctions = ARRAY_SIZE(spear1340_functions),
.modes_supported = false,
};
static struct of_device_id spear1340_pinctrl_of_match[] __devinitdata = {
{
.compatible = "st,spear1340-pinmux",
},
{},
};
static int __devinit spear1340_pinctrl_probe(struct platform_device *pdev)
{
return spear_pinctrl_probe(pdev, &spear1340_machdata);
}
static int __devexit spear1340_pinctrl_remove(struct platform_device *pdev)
{
return spear_pinctrl_remove(pdev);
}
static struct platform_driver spear1340_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = spear1340_pinctrl_of_match,
},
.probe = spear1340_pinctrl_probe,
.remove = __devexit_p(spear1340_pinctrl_remove),
};
static int __init spear1340_pinctrl_init(void)
{
return platform_driver_register(&spear1340_pinctrl_driver);
}
arch_initcall(spear1340_pinctrl_init);
static void __exit spear1340_pinctrl_exit(void)
{
platform_driver_unregister(&spear1340_pinctrl_driver);
}
module_exit(spear1340_pinctrl_exit);
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match);
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