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Commit 87a87657 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/msppp: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e3332c20
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Inline Side-by-side
Showing with 104 additions and 107 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
View file @ 87a87657
#ifndef __NOUVEAU_MSPPP_H__ #ifndef __NVKM_MSPPP_H__
#define __NOUVEAU_MSPPP_H__ #define __NVKM_MSPPP_H__
#include <core/engine.h>
extern struct nouveau_oclass nv98_msppp_oclass; extern struct nvkm_oclass g98_msppp_oclass;
extern struct nouveau_oclass nvc0_msppp_oclass; extern struct nvkm_oclass gf100_msppp_oclass;
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View file @ 87a87657
...@@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device) ...@@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device)
#if 0 #if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif #endif
break; break;
case 0x124: case 0x124:
...@@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device) ...@@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif #endif
break; break;
default: default:
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 87a87657
...@@ -257,7 +257,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -257,7 +257,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break; break;
...@@ -315,7 +315,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -315,7 +315,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break; break;
...@@ -344,7 +344,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -344,7 +344,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break; break;
...@@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
...@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
...@@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
...@@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View file @ 87a87657
...@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
...@@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
...@@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
...@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
...@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
...@@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
...@@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
...@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
...@@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View file @ 87a87657
...@@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break; break;
case 0xe7: case 0xe7:
...@@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break; break;
case 0xe6: case 0xe6:
...@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break; break;
case 0xea: case 0xea:
...@@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break; break;
case 0xf1: case 0xf1:
...@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break; break;
case 0x106: case 0x106:
...@@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break; break;
case 0x108: case 0x108:
device->cname = "GK208"; device->cname = "GK208";
...@@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break; break;
default: default:
nv_fatal(device, "unknown Kepler chipset\n"); nv_fatal(device, "unknown Kepler chipset\n");
......
drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
View file @ 87a87657
nvkm-y += nvkm/engine/msppp/nv98.o nvkm-y += nvkm/engine/msppp/g98.o
nvkm-y += nvkm/engine/msppp/nvc0.o nvkm-y += nvkm/engine/msppp/gf100.o
drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c → drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
View file @ 87a87657
...@@ -21,22 +21,21 @@ ...@@ -21,22 +21,21 @@
* *
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/ */
#include <engine/falcon.h>
#include <engine/msppp.h> #include <engine/msppp.h>
#include <engine/falcon.h>
struct nv98_msppp_priv { struct g98_msppp_priv {
struct nouveau_falcon base; struct nvkm_falcon base;
}; };
/******************************************************************************* /*******************************************************************************
* MSPPP object classes * MSPPP object classes
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nvkm_oclass
nv98_msppp_sclass[] = { g98_msppp_sclass[] = {
{ 0x88b3, &nouveau_object_ofuncs }, { 0x88b3, &nvkm_object_ofuncs },
{ 0x85b3, &nouveau_object_ofuncs }, { 0x85b3, &nvkm_object_ofuncs },
{}, {},
}; };
...@@ -44,16 +43,16 @@ nv98_msppp_sclass[] = { ...@@ -44,16 +43,16 @@ nv98_msppp_sclass[] = {
* PMSPPP context * PMSPPP context
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nvkm_oclass
nv98_msppp_cclass = { g98_msppp_cclass = {
.handle = NV_ENGCTX(MSPPP, 0x98), .handle = NV_ENGCTX(MSPPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nouveau_falcon_context_ctor, .ctor = _nvkm_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor, .dtor = _nvkm_falcon_context_dtor,
.init = _nouveau_falcon_context_init, .init = _nvkm_falcon_context_init,
.fini = _nouveau_falcon_context_fini, .fini = _nvkm_falcon_context_fini,
.rd32 = _nouveau_falcon_context_rd32, .rd32 = _nvkm_falcon_context_rd32,
.wr32 = _nouveau_falcon_context_wr32, .wr32 = _nvkm_falcon_context_wr32,
}, },
}; };
...@@ -62,12 +61,12 @@ nv98_msppp_cclass = { ...@@ -62,12 +61,12 @@ nv98_msppp_cclass = {
******************************************************************************/ ******************************************************************************/
static int static int
nv98_msppp_init(struct nouveau_object *object) g98_msppp_init(struct nvkm_object *object)
{ {
struct nv98_msppp_priv *priv = (void *)object; struct g98_msppp_priv *priv = (void *)object;
int ret; int ret;
ret = nouveau_falcon_init(&priv->base); ret = nvkm_falcon_init(&priv->base);
if (ret) if (ret)
return ret; return ret;
...@@ -77,34 +76,34 @@ nv98_msppp_init(struct nouveau_object *object) ...@@ -77,34 +76,34 @@ nv98_msppp_init(struct nouveau_object *object)
} }
static int static int
nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nv98_msppp_priv *priv; struct g98_msppp_priv *priv;
int ret; int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true,
"PMSPPP", "msppp", &priv); "PMSPPP", "msppp", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00400002; nv_subdev(priv)->unit = 0x00400002;
nv_engine(priv)->cclass = &nv98_msppp_cclass; nv_engine(priv)->cclass = &g98_msppp_cclass;
nv_engine(priv)->sclass = nv98_msppp_sclass; nv_engine(priv)->sclass = g98_msppp_sclass;
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nv98_msppp_oclass = { g98_msppp_oclass = {
.handle = NV_ENGINE(MSPPP, 0x98), .handle = NV_ENGINE(MSPPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv98_msppp_ctor, .ctor = g98_msppp_ctor,
.dtor = _nouveau_falcon_dtor, .dtor = _nvkm_falcon_dtor,
.init = nv98_msppp_init, .init = g98_msppp_init,
.fini = _nouveau_falcon_fini, .fini = _nvkm_falcon_fini,
.rd32 = _nouveau_falcon_rd32, .rd32 = _nvkm_falcon_rd32,
.wr32 = _nouveau_falcon_wr32, .wr32 = _nvkm_falcon_wr32,
}, },
}; };
drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
View file @ 87a87657
...@@ -21,21 +21,20 @@ ...@@ -21,21 +21,20 @@
* *
* Authors: Maarten Lankhorst * Authors: Maarten Lankhorst
*/ */
#include <engine/falcon.h>
#include <engine/msppp.h> #include <engine/msppp.h>
#include <engine/falcon.h>
struct nvc0_msppp_priv { struct gf100_msppp_priv {
struct nouveau_falcon base; struct nvkm_falcon base;
}; };
/******************************************************************************* /*******************************************************************************
* MSPPP object classes * MSPPP object classes
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nvkm_oclass
nvc0_msppp_sclass[] = { gf100_msppp_sclass[] = {
{ 0x90b3, &nouveau_object_ofuncs }, { 0x90b3, &nvkm_object_ofuncs },
{}, {},
}; };
...@@ -43,16 +42,16 @@ nvc0_msppp_sclass[] = { ...@@ -43,16 +42,16 @@ nvc0_msppp_sclass[] = {
* PMSPPP context * PMSPPP context
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nvkm_oclass
nvc0_msppp_cclass = { gf100_msppp_cclass = {
.handle = NV_ENGCTX(MSPPP, 0xc0), .handle = NV_ENGCTX(MSPPP, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nouveau_falcon_context_ctor, .ctor = _nvkm_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor, .dtor = _nvkm_falcon_context_dtor,
.init = _nouveau_falcon_context_init, .init = _nvkm_falcon_context_init,
.fini = _nouveau_falcon_context_fini, .fini = _nvkm_falcon_context_fini,
.rd32 = _nouveau_falcon_context_rd32, .rd32 = _nvkm_falcon_context_rd32,
.wr32 = _nouveau_falcon_context_wr32, .wr32 = _nvkm_falcon_context_wr32,
}, },
}; };
...@@ -61,12 +60,12 @@ nvc0_msppp_cclass = { ...@@ -61,12 +60,12 @@ nvc0_msppp_cclass = {
******************************************************************************/ ******************************************************************************/
static int static int
nvc0_msppp_init(struct nouveau_object *object) gf100_msppp_init(struct nvkm_object *object)
{ {
struct nvc0_msppp_priv *priv = (void *)object; struct gf100_msppp_priv *priv = (void *)object;
int ret; int ret;
ret = nouveau_falcon_init(&priv->base); ret = nvkm_falcon_init(&priv->base);
if (ret) if (ret)
return ret; return ret;
...@@ -76,35 +75,35 @@ nvc0_msppp_init(struct nouveau_object *object) ...@@ -76,35 +75,35 @@ nvc0_msppp_init(struct nouveau_object *object)
} }
static int static int
nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nvc0_msppp_priv *priv; struct gf100_msppp_priv *priv;
int ret; int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true,
"PMSPPP", "msppp", &priv); "PMSPPP", "msppp", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x00000002; nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nouveau_falcon_intr; nv_subdev(priv)->intr = nvkm_falcon_intr;
nv_engine(priv)->cclass = &nvc0_msppp_cclass; nv_engine(priv)->cclass = &gf100_msppp_cclass;
nv_engine(priv)->sclass = nvc0_msppp_sclass; nv_engine(priv)->sclass = gf100_msppp_sclass;
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nvc0_msppp_oclass = { gf100_msppp_oclass = {
.handle = NV_ENGINE(MSPPP, 0xc0), .handle = NV_ENGINE(MSPPP, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nvc0_msppp_ctor, .ctor = gf100_msppp_ctor,
.dtor = _nouveau_falcon_dtor, .dtor = _nvkm_falcon_dtor,
.init = nvc0_msppp_init, .init = gf100_msppp_init,
.fini = _nouveau_falcon_fini, .fini = _nvkm_falcon_fini,
.rd32 = _nouveau_falcon_rd32, .rd32 = _nvkm_falcon_rd32,
.wr32 = _nouveau_falcon_wr32, .wr32 = _nvkm_falcon_wr32,
}, },
}; };
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