drm/gf100-/gr: split ppc state into its subunits

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c

@@ -511,27 +511,19 @@ nv108_grctx_pack_tpc[] = {
 };
 
 static const struct nvc0_graph_init
-nv108_grctx_init_ppc_0[] = {
-	{ 0x41be24,   1, 0x04, 0x00000006 },
+nv108_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x10000000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
 	{ 0x41bee4,   1, 0x04, 0x00000000 },
 	{ 0x41bef0,   1, 0x04, 0x000003ff },
-	{ 0x41bf00,   1, 0x04, 0x0a418820 },
-	{ 0x41bf04,   1, 0x04, 0x062080e6 },
-	{ 0x41bf08,   1, 0x04, 0x020398a4 },
-	{ 0x41bf0c,   1, 0x04, 0x0e629062 },
-	{ 0x41bf10,   1, 0x04, 0x0a418820 },
-	{ 0x41bf14,   1, 0x04, 0x000000e6 },
-	{ 0x41bfd0,   1, 0x04, 0x00900103 },
-	{ 0x41bfe0,   1, 0x04, 0x00400001 },
-	{ 0x41bfe4,   1, 0x04, 0x00000000 },
 	{}
 };
 
 static const struct nvc0_graph_pack
 nv108_grctx_pack_ppc[] = {
-	{ nv108_grctx_init_ppc_0 },
+	{ nve4_grctx_init_pes_0 },
+	{ nv108_grctx_init_cbm_0 },
+	{ nvd7_grctx_init_wwdx_0 },
 	{}
 };
 

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h

@@ -140,12 +140,16 @@ extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[];
 
 extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[];
 
+extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[];
+
 extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];
 extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];
 extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
 
 extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[];
 
+extern const struct nvc0_graph_init nve4_grctx_init_pes_0[];
+
 extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];
 
 extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c

@@ -138,11 +138,21 @@ nvd7_grctx_pack_tpc[] = {
 };
 
 static const struct nvc0_graph_init
-nvd7_grctx_init_ppc_0[] = {
+nvd7_grctx_init_pes_0[] = {
 	{ 0x41be24,   1, 0x04, 0x00000002 },
+	{}
+};
+
+static const struct nvc0_graph_init
+nvd7_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x12180000 },
 	{ 0x41bec4,   1, 0x04, 0x00003fff },
 	{ 0x41bee4,   1, 0x04, 0x03240218 },
+	{}
+};
+
+const struct nvc0_graph_init
+nvd7_grctx_init_wwdx_0[] = {
 	{ 0x41bf00,   1, 0x04, 0x0a418820 },
 	{ 0x41bf04,   1, 0x04, 0x062080e6 },
 	{ 0x41bf08,   1, 0x04, 0x020398a4 },
@@ -157,7 +167,9 @@ nvd7_grctx_init_ppc_0[] = {
 
 static const struct nvc0_graph_pack
 nvd7_grctx_pack_ppc[] = {
-	{ nvd7_grctx_init_ppc_0 },
+	{ nvd7_grctx_init_pes_0 },
+	{ nvd7_grctx_init_cbm_0 },
+	{ nvd7_grctx_init_wwdx_0 },
 	{}
 };
 

drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c

@@ -812,27 +812,25 @@ nve4_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-nve4_grctx_init_ppc_0[] = {
+const struct nvc0_graph_init
+nve4_grctx_init_pes_0[] = {
 	{ 0x41be24,   1, 0x04, 0x00000006 },
+	{}
+};
+
+static const struct nvc0_graph_init
+nve4_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x12180000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
 	{ 0x41bee4,   1, 0x04, 0x06480430 },
-	{ 0x41bf00,   1, 0x04, 0x0a418820 },
-	{ 0x41bf04,   1, 0x04, 0x062080e6 },
-	{ 0x41bf08,   1, 0x04, 0x020398a4 },
-	{ 0x41bf0c,   1, 0x04, 0x0e629062 },
-	{ 0x41bf10,   1, 0x04, 0x0a418820 },
-	{ 0x41bf14,   1, 0x04, 0x000000e6 },
-	{ 0x41bfd0,   1, 0x04, 0x00900103 },
-	{ 0x41bfe0,   1, 0x04, 0x00400001 },
-	{ 0x41bfe4,   1, 0x04, 0x00000000 },
 	{}
 };
 
 static const struct nvc0_graph_pack
 nve4_grctx_pack_ppc[] = {
-	{ nve4_grctx_init_ppc_0 },
+	{ nve4_grctx_init_pes_0 },
+	{ nve4_grctx_init_cbm_0 },
+	{ nvd7_grctx_init_wwdx_0 },
 	{}
 };
 

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c

@@ -790,26 +790,18 @@ nvf0_grctx_pack_tpc[] = {
 };
 
 static const struct nvc0_graph_init
-nvf0_grctx_init_ppc_0[] = {
-	{ 0x41be24,   1, 0x04, 0x00000006 },
+nvf0_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x10000000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
 	{ 0x41bee4,   1, 0x04, 0x00000000 },
-	{ 0x41bf00,   1, 0x04, 0x0a418820 },
-	{ 0x41bf04,   1, 0x04, 0x062080e6 },
-	{ 0x41bf08,   1, 0x04, 0x020398a4 },
-	{ 0x41bf0c,   1, 0x04, 0x0e629062 },
-	{ 0x41bf10,   1, 0x04, 0x0a418820 },
-	{ 0x41bf14,   1, 0x04, 0x000000e6 },
-	{ 0x41bfd0,   1, 0x04, 0x00900103 },
-	{ 0x41bfe0,   1, 0x04, 0x00400001 },
-	{ 0x41bfe4,   1, 0x04, 0x00000000 },
 	{}
 };
 
 static const struct nvc0_graph_pack
 nvf0_grctx_pack_ppc[] = {
-	{ nvf0_grctx_init_ppc_0 },
+	{ nve4_grctx_init_pes_0 },
+	{ nvf0_grctx_init_cbm_0 },
+	{ nvd7_grctx_init_wwdx_0 },
 	{}
 };
 

drivers/gpu/drm/nouveau/core/engine/graph/nv108.c

@@ -137,7 +137,9 @@ nv108_graph_pack_mmio[] = {
 	{ nv108_graph_init_l1c_0 },
 	{ nvc0_graph_init_mpc_0 },
 	{ nvf0_graph_init_sm_0 },
-	{ nvd7_graph_init_ppc_0 },
+	{ nvd7_graph_init_pes_0 },
+	{ nvd7_graph_init_wwdx_0 },
+	{ nvd7_graph_init_cbm_0 },
 	{ nve4_graph_init_be_0 },
 	{ nvc0_graph_init_fe_1 },
 	{}

drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h

@@ -208,7 +208,9 @@ extern const struct nvc0_graph_init nvd9_graph_init_tex_0[];
 extern const struct nvc0_graph_init nvd9_graph_init_sm_0[];
 extern const struct nvc0_graph_init nvd9_graph_init_fe_1[];
 
-extern const struct nvc0_graph_init nvd7_graph_init_ppc_0[];
+extern const struct nvc0_graph_init nvd7_graph_init_pes_0[];
+extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[];
+extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[];
 
 extern const struct nvc0_graph_init nve4_graph_init_main_0[];
 extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[];

drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c

@@ -39,15 +39,25 @@ nvd7_graph_init_pe_0[] = {
 };
 
 const struct nvc0_graph_init
-nvd7_graph_init_ppc_0[] = {
+nvd7_graph_init_pes_0[] = {
 	{ 0x41be04,   1, 0x04, 0x00000000 },
 	{ 0x41be08,   1, 0x04, 0x00000004 },
 	{ 0x41be0c,   1, 0x04, 0x00000000 },
 	{ 0x41be10,   1, 0x04, 0x003b8bc7 },
 	{ 0x41be14,   2, 0x04, 0x00000000 },
+	{}
+};
+
+const struct nvc0_graph_init
+nvd7_graph_init_wwdx_0[] = {
 	{ 0x41bfd4,   1, 0x04, 0x00800000 },
 	{ 0x41bfdc,   1, 0x04, 0x00000000 },
 	{ 0x41bff8,   2, 0x04, 0x00000000 },
+	{}
+};
+
+const struct nvc0_graph_init
+nvd7_graph_init_cbm_0[] = {
 	{ 0x41becc,   1, 0x04, 0x00000000 },
 	{ 0x41bee8,   2, 0x04, 0x00000000 },
 	{}
@@ -77,7 +87,9 @@ nvd7_graph_pack_mmio[] = {
 	{ nvc0_graph_init_l1c_0 },
 	{ nvc0_graph_init_mpc_0 },
 	{ nvd9_graph_init_sm_0 },
-	{ nvd7_graph_init_ppc_0 },
+	{ nvd7_graph_init_pes_0 },
+	{ nvd7_graph_init_wwdx_0 },
+	{ nvd7_graph_init_cbm_0 },
 	{ nvc0_graph_init_be_0 },
 	{ nvd9_graph_init_fe_1 },
 	{}

drivers/gpu/drm/nouveau/core/engine/graph/nve4.c

@@ -177,7 +177,9 @@ nve4_graph_pack_mmio[] = {
 	{ nve4_graph_init_l1c_0 },
 	{ nvc0_graph_init_mpc_0 },
 	{ nve4_graph_init_sm_0 },
-	{ nvd7_graph_init_ppc_0 },
+	{ nvd7_graph_init_pes_0 },
+	{ nvd7_graph_init_wwdx_0 },
+	{ nvd7_graph_init_cbm_0 },
 	{ nve4_graph_init_be_0 },
 	{ nvc0_graph_init_fe_1 },
 	{}

drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c

@@ -158,7 +158,9 @@ nvf0_graph_pack_mmio[] = {
 	{ nvf0_graph_init_l1c_0 },
 	{ nvc0_graph_init_mpc_0 },
 	{ nvf0_graph_init_sm_0 },
-	{ nvd7_graph_init_ppc_0 },
+	{ nvd7_graph_init_pes_0 },
+	{ nvd7_graph_init_wwdx_0 },
+	{ nvd7_graph_init_cbm_0 },
 	{ nve4_graph_init_be_0 },
 	{ nvc0_graph_init_fe_1 },
 	{}