Commit 89830580 authored by Vince Bridgers's avatar Vince Bridgers Committed by David S. Miller

Altera TSE: Fix sparse errors and warnings

This patch fixes the many sparse errors and warnings contained in the
initial submission of the Altera Triple Speed Ethernet driver, and a
few minor cppcheck warnings. Changes are tested on ARM and NIOS2
example designs, and compile tested against multiple architectures.
Typical issues addressed were as follows:

altera_tse_ethtool.c:136:19: warning: incorrect type in argument
    1 (different address spaces)
altera_tse_ethtool.c:136:19:    expected void const volatile
    [noderef] <asn:2>*addr
altera_tse_ethtool.c:136:19:    got unsigned int *<noident>
...
altera_sgdma.c:129:31: warning: cast removes address space of
    expression
Signed-off-by: default avatarVince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 200b916f
...@@ -5,3 +5,4 @@ ...@@ -5,3 +5,4 @@
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \ altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \
altera_msgdma.o altera_sgdma.o altera_utils.o altera_msgdma.o altera_sgdma.o altera_utils.o
ccflags-y += -D__CHECK_ENDIAN__
...@@ -37,18 +37,16 @@ void msgdma_start_rxdma(struct altera_tse_private *priv) ...@@ -37,18 +37,16 @@ void msgdma_start_rxdma(struct altera_tse_private *priv)
void msgdma_reset(struct altera_tse_private *priv) void msgdma_reset(struct altera_tse_private *priv)
{ {
int counter; int counter;
struct msgdma_csr *txcsr =
(struct msgdma_csr *)priv->tx_dma_csr;
struct msgdma_csr *rxcsr =
(struct msgdma_csr *)priv->rx_dma_csr;
/* Reset Rx mSGDMA */ /* Reset Rx mSGDMA */
iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
iowrite32(MSGDMA_CSR_CTL_RESET, &rxcsr->control); msgdma_csroffs(status));
csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
msgdma_csroffs(control));
counter = 0; counter = 0;
while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
if (tse_bit_is_clear(&rxcsr->status, if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
MSGDMA_CSR_STAT_RESETTING)) MSGDMA_CSR_STAT_RESETTING))
break; break;
udelay(1); udelay(1);
...@@ -59,15 +57,18 @@ void msgdma_reset(struct altera_tse_private *priv) ...@@ -59,15 +57,18 @@ void msgdma_reset(struct altera_tse_private *priv)
"TSE Rx mSGDMA resetting bit never cleared!\n"); "TSE Rx mSGDMA resetting bit never cleared!\n");
/* clear all status bits */ /* clear all status bits */
iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
/* Reset Tx mSGDMA */ /* Reset Tx mSGDMA */
iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
iowrite32(MSGDMA_CSR_CTL_RESET, &txcsr->control); msgdma_csroffs(status));
csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
msgdma_csroffs(control));
counter = 0; counter = 0;
while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
if (tse_bit_is_clear(&txcsr->status, if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
MSGDMA_CSR_STAT_RESETTING)) MSGDMA_CSR_STAT_RESETTING))
break; break;
udelay(1); udelay(1);
...@@ -78,58 +79,58 @@ void msgdma_reset(struct altera_tse_private *priv) ...@@ -78,58 +79,58 @@ void msgdma_reset(struct altera_tse_private *priv)
"TSE Tx mSGDMA resetting bit never cleared!\n"); "TSE Tx mSGDMA resetting bit never cleared!\n");
/* clear all status bits */ /* clear all status bits */
iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
} }
void msgdma_disable_rxirq(struct altera_tse_private *priv) void msgdma_disable_rxirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->rx_dma_csr; tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_enable_rxirq(struct altera_tse_private *priv) void msgdma_enable_rxirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->rx_dma_csr; tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_disable_txirq(struct altera_tse_private *priv) void msgdma_disable_txirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->tx_dma_csr; tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_enable_txirq(struct altera_tse_private *priv) void msgdma_enable_txirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->tx_dma_csr; tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_clear_rxirq(struct altera_tse_private *priv) void msgdma_clear_rxirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->rx_dma_csr; csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
} }
void msgdma_clear_txirq(struct altera_tse_private *priv) void msgdma_clear_txirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->tx_dma_csr; csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
} }
/* return 0 to indicate transmit is pending */ /* return 0 to indicate transmit is pending */
int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer) int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
{ {
struct msgdma_extended_desc *desc = priv->tx_dma_desc; csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
msgdma_descroffs(read_addr_lo));
iowrite32(lower_32_bits(buffer->dma_addr), &desc->read_addr_lo); csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
iowrite32(upper_32_bits(buffer->dma_addr), &desc->read_addr_hi); msgdma_descroffs(read_addr_hi));
iowrite32(0, &desc->write_addr_lo); csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
iowrite32(0, &desc->write_addr_hi); csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
iowrite32(buffer->len, &desc->len); csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
iowrite32(0, &desc->burst_seq_num); csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
iowrite32(MSGDMA_DESC_TX_STRIDE, &desc->stride); csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
iowrite32(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control); msgdma_descroffs(stride));
csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
msgdma_descroffs(control));
return 0; return 0;
} }
...@@ -138,17 +139,16 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv) ...@@ -138,17 +139,16 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
u32 ready = 0; u32 ready = 0;
u32 inuse; u32 inuse;
u32 status; u32 status;
struct msgdma_csr *txcsr =
(struct msgdma_csr *)priv->tx_dma_csr;
/* Get number of sent descriptors */ /* Get number of sent descriptors */
inuse = ioread32(&txcsr->rw_fill_level) & 0xffff; inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
& 0xffff;
if (inuse) { /* Tx FIFO is not empty */ if (inuse) { /* Tx FIFO is not empty */
ready = priv->tx_prod - priv->tx_cons - inuse - 1; ready = priv->tx_prod - priv->tx_cons - inuse - 1;
} else { } else {
/* Check for buffered last packet */ /* Check for buffered last packet */
status = ioread32(&txcsr->status); status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
if (status & MSGDMA_CSR_STAT_BUSY) if (status & MSGDMA_CSR_STAT_BUSY)
ready = priv->tx_prod - priv->tx_cons - 1; ready = priv->tx_prod - priv->tx_cons - 1;
else else
...@@ -162,7 +162,6 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv) ...@@ -162,7 +162,6 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
void msgdma_add_rx_desc(struct altera_tse_private *priv, void msgdma_add_rx_desc(struct altera_tse_private *priv,
struct tse_buffer *rxbuffer) struct tse_buffer *rxbuffer)
{ {
struct msgdma_extended_desc *desc = priv->rx_dma_desc;
u32 len = priv->rx_dma_buf_sz; u32 len = priv->rx_dma_buf_sz;
dma_addr_t dma_addr = rxbuffer->dma_addr; dma_addr_t dma_addr = rxbuffer->dma_addr;
u32 control = (MSGDMA_DESC_CTL_END_ON_EOP u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
...@@ -172,14 +171,16 @@ void msgdma_add_rx_desc(struct altera_tse_private *priv, ...@@ -172,14 +171,16 @@ void msgdma_add_rx_desc(struct altera_tse_private *priv,
| MSGDMA_DESC_CTL_TR_ERR_IRQ | MSGDMA_DESC_CTL_TR_ERR_IRQ
| MSGDMA_DESC_CTL_GO); | MSGDMA_DESC_CTL_GO);
iowrite32(0, &desc->read_addr_lo); csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
iowrite32(0, &desc->read_addr_hi); csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
iowrite32(lower_32_bits(dma_addr), &desc->write_addr_lo); csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
iowrite32(upper_32_bits(dma_addr), &desc->write_addr_hi); msgdma_descroffs(write_addr_lo));
iowrite32(len, &desc->len); csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
iowrite32(0, &desc->burst_seq_num); msgdma_descroffs(write_addr_hi));
iowrite32(0x00010001, &desc->stride); csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
iowrite32(control, &desc->control); csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
} }
/* status is returned on upper 16 bits, /* status is returned on upper 16 bits,
...@@ -190,14 +191,13 @@ u32 msgdma_rx_status(struct altera_tse_private *priv) ...@@ -190,14 +191,13 @@ u32 msgdma_rx_status(struct altera_tse_private *priv)
u32 rxstatus = 0; u32 rxstatus = 0;
u32 pktlength; u32 pktlength;
u32 pktstatus; u32 pktstatus;
struct msgdma_csr *rxcsr =
(struct msgdma_csr *)priv->rx_dma_csr; if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
struct msgdma_response *rxresp = & 0xffff) {
(struct msgdma_response *)priv->rx_dma_resp; pktlength = csrrd32(priv->rx_dma_resp,
msgdma_respoffs(bytes_transferred));
if (ioread32(&rxcsr->resp_fill_level) & 0xffff) { pktstatus = csrrd32(priv->rx_dma_resp,
pktlength = ioread32(&rxresp->bytes_transferred); msgdma_respoffs(status));
pktstatus = ioread32(&rxresp->status);
rxstatus = pktstatus; rxstatus = pktstatus;
rxstatus = rxstatus << 16; rxstatus = rxstatus << 16;
rxstatus |= (pktlength & 0xffff); rxstatus |= (pktlength & 0xffff);
......
...@@ -17,15 +17,6 @@ ...@@ -17,15 +17,6 @@
#ifndef __ALTERA_MSGDMAHW_H__ #ifndef __ALTERA_MSGDMAHW_H__
#define __ALTERA_MSGDMAHW_H__ #define __ALTERA_MSGDMAHW_H__
/* mSGDMA standard descriptor format
*/
struct msgdma_desc {
u32 read_addr; /* data buffer source address */
u32 write_addr; /* data buffer destination address */
u32 len; /* the number of bytes to transfer per descriptor */
u32 control; /* characteristics of the transfer */
};
/* mSGDMA extended descriptor format /* mSGDMA extended descriptor format
*/ */
struct msgdma_extended_desc { struct msgdma_extended_desc {
...@@ -159,6 +150,10 @@ struct msgdma_response { ...@@ -159,6 +150,10 @@ struct msgdma_response {
u32 status; u32 status;
}; };
#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
/* mSGDMA response register bit definitions /* mSGDMA response register bit definitions
*/ */
#define MSGDMA_RESP_EARLY_TERM BIT(8) #define MSGDMA_RESP_EARLY_TERM BIT(8)
......
This diff is collapsed.
...@@ -19,16 +19,16 @@ ...@@ -19,16 +19,16 @@
/* SGDMA descriptor structure */ /* SGDMA descriptor structure */
struct sgdma_descrip { struct sgdma_descrip {
unsigned int raddr; /* address of data to be read */ u32 raddr; /* address of data to be read */
unsigned int pad1; u32 pad1;
unsigned int waddr; u32 waddr;
unsigned int pad2; u32 pad2;
unsigned int next; u32 next;
unsigned int pad3; u32 pad3;
unsigned short bytes; u16 bytes;
unsigned char rburst; u8 rburst;
unsigned char wburst; u8 wburst;
unsigned short bytes_xferred; /* 16 bits, bytes xferred */ u16 bytes_xferred; /* 16 bits, bytes xferred */
/* bit 0: error /* bit 0: error
* bit 1: length error * bit 1: length error
...@@ -39,7 +39,7 @@ struct sgdma_descrip { ...@@ -39,7 +39,7 @@ struct sgdma_descrip {
* bit 6: reserved * bit 6: reserved
* bit 7: status eop for recv case * bit 7: status eop for recv case
*/ */
unsigned char status; u8 status;
/* bit 0: eop /* bit 0: eop
* bit 1: read_fixed * bit 1: read_fixed
...@@ -47,7 +47,7 @@ struct sgdma_descrip { ...@@ -47,7 +47,7 @@ struct sgdma_descrip {
* bits 3,4,5,6: Channel (always 0) * bits 3,4,5,6: Channel (always 0)
* bit 7: hardware owned * bit 7: hardware owned
*/ */
unsigned char control; u8 control;
} __packed; } __packed;
...@@ -101,6 +101,8 @@ struct sgdma_csr { ...@@ -101,6 +101,8 @@ struct sgdma_csr {
u32 pad3[3]; u32 pad3[3];
}; };
#define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a))
#define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a))
#define SGDMA_STSREG_ERR BIT(0) /* Error */ #define SGDMA_STSREG_ERR BIT(0) /* Error */
#define SGDMA_STSREG_EOP BIT(1) /* EOP */ #define SGDMA_STSREG_EOP BIT(1) /* EOP */
......
...@@ -357,6 +357,8 @@ struct altera_tse_mac { ...@@ -357,6 +357,8 @@ struct altera_tse_mac {
u32 reserved5[42]; u32 reserved5[42];
}; };
#define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
/* Transmit and Receive Command Registers Bit Definitions /* Transmit and Receive Command Registers Bit Definitions
*/ */
#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
...@@ -487,4 +489,49 @@ struct altera_tse_private { ...@@ -487,4 +489,49 @@ struct altera_tse_private {
*/ */
void altera_tse_set_ethtool_ops(struct net_device *); void altera_tse_set_ethtool_ops(struct net_device *);
static inline
u32 csrrd32(void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
return readl(paddr);
}
static inline
u16 csrrd16(void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
return readw(paddr);
}
static inline
u8 csrrd8(void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
return readb(paddr);
}
static inline
void csrwr32(u32 val, void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
writel(val, paddr);
}
static inline
void csrwr16(u16 val, void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
writew(val, paddr);
}
static inline
void csrwr8(u8 val, void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
writeb(val, paddr);
}
#endif /* __ALTERA_TSE_H__ */ #endif /* __ALTERA_TSE_H__ */
...@@ -96,54 +96,89 @@ static void tse_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, ...@@ -96,54 +96,89 @@ static void tse_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
u64 *buf) u64 *buf)
{ {
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct altera_tse_mac *mac = priv->mac_dev;
u64 ext; u64 ext;
buf[0] = ioread32(&mac->frames_transmitted_ok); buf[0] = csrrd32(priv->mac_dev,
buf[1] = ioread32(&mac->frames_received_ok); tse_csroffs(frames_transmitted_ok));
buf[2] = ioread32(&mac->frames_check_sequence_errors); buf[1] = csrrd32(priv->mac_dev,
buf[3] = ioread32(&mac->alignment_errors); tse_csroffs(frames_received_ok));
buf[2] = csrrd32(priv->mac_dev,
tse_csroffs(frames_check_sequence_errors));
buf[3] = csrrd32(priv->mac_dev,
tse_csroffs(alignment_errors));
/* Extended aOctetsTransmittedOK counter */ /* Extended aOctetsTransmittedOK counter */
ext = (u64) ioread32(&mac->msb_octets_transmitted_ok) << 32; ext = (u64) csrrd32(priv->mac_dev,
ext |= ioread32(&mac->octets_transmitted_ok); tse_csroffs(msb_octets_transmitted_ok)) << 32;
ext |= csrrd32(priv->mac_dev,
tse_csroffs(octets_transmitted_ok));
buf[4] = ext; buf[4] = ext;
/* Extended aOctetsReceivedOK counter */ /* Extended aOctetsReceivedOK counter */
ext = (u64) ioread32(&mac->msb_octets_received_ok) << 32; ext = (u64) csrrd32(priv->mac_dev,
ext |= ioread32(&mac->octets_received_ok); tse_csroffs(msb_octets_received_ok)) << 32;
ext |= csrrd32(priv->mac_dev,
tse_csroffs(octets_received_ok));
buf[5] = ext; buf[5] = ext;
buf[6] = ioread32(&mac->tx_pause_mac_ctrl_frames); buf[6] = csrrd32(priv->mac_dev,
buf[7] = ioread32(&mac->rx_pause_mac_ctrl_frames); tse_csroffs(tx_pause_mac_ctrl_frames));
buf[8] = ioread32(&mac->if_in_errors); buf[7] = csrrd32(priv->mac_dev,
buf[9] = ioread32(&mac->if_out_errors); tse_csroffs(rx_pause_mac_ctrl_frames));
buf[10] = ioread32(&mac->if_in_ucast_pkts); buf[8] = csrrd32(priv->mac_dev,
buf[11] = ioread32(&mac->if_in_multicast_pkts); tse_csroffs(if_in_errors));
buf[12] = ioread32(&mac->if_in_broadcast_pkts); buf[9] = csrrd32(priv->mac_dev,
buf[13] = ioread32(&mac->if_out_discards); tse_csroffs(if_out_errors));
buf[14] = ioread32(&mac->if_out_ucast_pkts); buf[10] = csrrd32(priv->mac_dev,
buf[15] = ioread32(&mac->if_out_multicast_pkts); tse_csroffs(if_in_ucast_pkts));
buf[16] = ioread32(&mac->if_out_broadcast_pkts); buf[11] = csrrd32(priv->mac_dev,
buf[17] = ioread32(&mac->ether_stats_drop_events); tse_csroffs(if_in_multicast_pkts));
buf[12] = csrrd32(priv->mac_dev,
tse_csroffs(if_in_broadcast_pkts));
buf[13] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_discards));
buf[14] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_ucast_pkts));
buf[15] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_multicast_pkts));
buf[16] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_broadcast_pkts));
buf[17] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_drop_events));
/* Extended etherStatsOctets counter */ /* Extended etherStatsOctets counter */
ext = (u64) ioread32(&mac->msb_ether_stats_octets) << 32; ext = (u64) csrrd32(priv->mac_dev,
ext |= ioread32(&mac->ether_stats_octets); tse_csroffs(msb_ether_stats_octets)) << 32;
ext |= csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_octets));
buf[18] = ext; buf[18] = ext;
buf[19] = ioread32(&mac->ether_stats_pkts); buf[19] = csrrd32(priv->mac_dev,
buf[20] = ioread32(&mac->ether_stats_undersize_pkts); tse_csroffs(ether_stats_pkts));
buf[21] = ioread32(&mac->ether_stats_oversize_pkts); buf[20] = csrrd32(priv->mac_dev,
buf[22] = ioread32(&mac->ether_stats_pkts_64_octets); tse_csroffs(ether_stats_undersize_pkts));
buf[23] = ioread32(&mac->ether_stats_pkts_65to127_octets); buf[21] = csrrd32(priv->mac_dev,
buf[24] = ioread32(&mac->ether_stats_pkts_128to255_octets); tse_csroffs(ether_stats_oversize_pkts));
buf[25] = ioread32(&mac->ether_stats_pkts_256to511_octets); buf[22] = csrrd32(priv->mac_dev,
buf[26] = ioread32(&mac->ether_stats_pkts_512to1023_octets); tse_csroffs(ether_stats_pkts_64_octets));
buf[27] = ioread32(&mac->ether_stats_pkts_1024to1518_octets); buf[23] = csrrd32(priv->mac_dev,
buf[28] = ioread32(&mac->ether_stats_pkts_1519tox_octets); tse_csroffs(ether_stats_pkts_65to127_octets));
buf[29] = ioread32(&mac->ether_stats_jabbers); buf[24] = csrrd32(priv->mac_dev,
buf[30] = ioread32(&mac->ether_stats_fragments); tse_csroffs(ether_stats_pkts_128to255_octets));
buf[25] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_256to511_octets));
buf[26] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_512to1023_octets));
buf[27] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_1024to1518_octets));
buf[28] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_1519tox_octets));
buf[29] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_jabbers));
buf[30] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_fragments));
} }
static int tse_sset_count(struct net_device *dev, int sset) static int tse_sset_count(struct net_device *dev, int sset)
...@@ -178,7 +213,6 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs, ...@@ -178,7 +213,6 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs,
{ {
int i; int i;
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
u32 *tse_mac_regs = (u32 *)priv->mac_dev;
u32 *buf = regbuf; u32 *buf = regbuf;
/* Set version to a known value, so ethtool knows /* Set version to a known value, so ethtool knows
...@@ -196,7 +230,7 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs, ...@@ -196,7 +230,7 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs,
regs->version = 1; regs->version = 1;
for (i = 0; i < TSE_NUM_REGS; i++) for (i = 0; i < TSE_NUM_REGS; i++)
buf[i] = ioread32(&tse_mac_regs[i]); buf[i] = csrrd32(priv->mac_dev, i * 4);
} }
static int tse_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) static int tse_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
......
...@@ -17,28 +17,28 @@ ...@@ -17,28 +17,28 @@
#include "altera_tse.h" #include "altera_tse.h"
#include "altera_utils.h" #include "altera_utils.h"
void tse_set_bit(void __iomem *ioaddr, u32 bit_mask) void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
value |= bit_mask; value |= bit_mask;
iowrite32(value, ioaddr); csrwr32(value, ioaddr, offs);
} }
void tse_clear_bit(void __iomem *ioaddr, u32 bit_mask) void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
value &= ~bit_mask; value &= ~bit_mask;
iowrite32(value, ioaddr); csrwr32(value, ioaddr, offs);
} }
int tse_bit_is_set(void __iomem *ioaddr, u32 bit_mask) int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
return (value & bit_mask) ? 1 : 0; return (value & bit_mask) ? 1 : 0;
} }
int tse_bit_is_clear(void __iomem *ioaddr, u32 bit_mask) int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
return (value & bit_mask) ? 0 : 1; return (value & bit_mask) ? 0 : 1;
} }
...@@ -19,9 +19,9 @@ ...@@ -19,9 +19,9 @@
#ifndef __ALTERA_UTILS_H__ #ifndef __ALTERA_UTILS_H__
#define __ALTERA_UTILS_H__ #define __ALTERA_UTILS_H__
void tse_set_bit(void __iomem *ioaddr, u32 bit_mask); void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
void tse_clear_bit(void __iomem *ioaddr, u32 bit_mask); void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
int tse_bit_is_set(void __iomem *ioaddr, u32 bit_mask); int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask);
int tse_bit_is_clear(void __iomem *ioaddr, u32 bit_mask); int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask);
#endif /* __ALTERA_UTILS_H__*/ #endif /* __ALTERA_UTILS_H__*/
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