Commit 89d1e514 authored by Maxime Ripard's avatar Maxime Ripard

ARM: dts: sunxi: Add missing watchdog interrupts

The watchdog has an interrupt on all our SoCs, but it wasn't always listed.
Add it to the devicetree where it's missing.
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 4cdc12a3
...@@ -815,6 +815,7 @@ timer@1c20c00 { ...@@ -815,6 +815,7 @@ timer@1c20c00 {
wdt: watchdog@1c20c90 { wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <24>;
}; };
rtc: rtc@1c20d00 { rtc: rtc@1c20d00 {
......
...@@ -600,6 +600,7 @@ timer@1c20c00 { ...@@ -600,6 +600,7 @@ timer@1c20c00 {
wdt: watchdog@1c20c90 { wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <24>;
}; };
ir0: ir@1c21800 { ir0: ir@1c21800 {
......
...@@ -744,6 +744,7 @@ timer@1c20c00 { ...@@ -744,6 +744,7 @@ timer@1c20c00 {
wdt1: watchdog@1c20ca0 { wdt1: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
}; };
spdif: spdif@1c21000 { spdif: spdif@1c21000 {
......
...@@ -1140,6 +1140,7 @@ timer@1c20c00 { ...@@ -1140,6 +1140,7 @@ timer@1c20c00 {
wdt: watchdog@1c20c90 { wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
}; };
rtc: rtc@1c20d00 { rtc: rtc@1c20d00 {
......
...@@ -404,6 +404,7 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { ...@@ -404,6 +404,7 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
wdt: watchdog@1c20c90 { wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt"; compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>; reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
}; };
uart0: serial@1c28000 { uart0: serial@1c28000 {
......
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