Commit 8a39bee1 authored by Jakub Kicinski's avatar Jakub Kicinski

Merge branch 'arrow-speedchips-xrs700x-dsa-driver'

George McCollister says:

====================
Arrow SpeedChips XRS700x DSA Driver

This series adds a DSA driver for the Arrow SpeedChips XRS 7000 series
of HSR/PRP gigabit switch chips.

The chips use Flexibilis IP.
More information can be found here:
 https://www.flexibilis.com/products/speedchips-xrs7000/

The switches have up to three RGMII ports and one MII port and are
managed via mdio or i2c. They use a one byte trailing tag to identify
the switch port when in managed mode so I've added a tag driver which
implements this.

This series contains minimal DSA functionality which may be built upon
in future patches. The ultimate goal is to add HSR and PRP
(IEC 62439-3 Clause 5 & 4) offloading with integration into net/hsr.
====================

Link: https://lore.kernel.org/r/20210114195734.55313-1-george.mccollister@gmail.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents e7fa5c80 8204c2b0
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/arrow,xrs700x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arrow SpeedChips XRS7000 Series Switch Device Tree Bindings
allOf:
- $ref: dsa.yaml#
maintainers:
- George McCollister <george.mccollister@gmail.com>
description:
The Arrow SpeedChips XRS7000 Series of single chip gigabit Ethernet switches
are designed for critical networking applications. They have up to three
RGMII ports and one RMII port and are managed via i2c or mdio.
properties:
compatible:
oneOf:
- enum:
- arrow,xrs7003e
- arrow,xrs7003f
- arrow,xrs7004e
- arrow,xrs7004f
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
switch@8 {
compatible = "arrow,xrs7004e";
reg = <0x8>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy0>;
phy-mode = "rgmii-id";
};
ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy1>;
phy-mode = "rgmii-id";
};
ethernet-port@3 {
reg = <3>;
label = "cpu";
ethernet = <&fec1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
...@@ -60,6 +60,8 @@ source "drivers/net/dsa/qca/Kconfig" ...@@ -60,6 +60,8 @@ source "drivers/net/dsa/qca/Kconfig"
source "drivers/net/dsa/sja1105/Kconfig" source "drivers/net/dsa/sja1105/Kconfig"
source "drivers/net/dsa/xrs700x/Kconfig"
config NET_DSA_QCA8K config NET_DSA_QCA8K
tristate "Qualcomm Atheros QCA8K Ethernet switch family support" tristate "Qualcomm Atheros QCA8K Ethernet switch family support"
depends on NET_DSA depends on NET_DSA
......
...@@ -24,3 +24,4 @@ obj-y += mv88e6xxx/ ...@@ -24,3 +24,4 @@ obj-y += mv88e6xxx/
obj-y += ocelot/ obj-y += ocelot/
obj-y += qca/ obj-y += qca/
obj-y += sja1105/ obj-y += sja1105/
obj-y += xrs700x/
# SPDX-License-Identifier: GPL-2.0-only
config NET_DSA_XRS700X
tristate
depends on NET_DSA
select NET_DSA_TAG_XRS700X
select REGMAP
help
This enables support for Arrow SpeedChips XRS7003/7004 gigabit
Ethernet switches.
config NET_DSA_XRS700X_I2C
tristate "Arrow XRS7000X series switch in I2C mode"
depends on NET_DSA && I2C
select NET_DSA_XRS700X
select REGMAP_I2C
help
Enable I2C support for Arrow SpeedChips XRS7003/7004 gigabit Ethernet
switches.
config NET_DSA_XRS700X_MDIO
tristate "Arrow XRS7000X series switch in MDIO mode"
depends on NET_DSA
select NET_DSA_XRS700X
help
Enable MDIO support for Arrow SpeedChips XRS7003/7004 gigabit Ethernet
switches.
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_NET_DSA_XRS700X) += xrs700x.o
obj-$(CONFIG_NET_DSA_XRS700X_I2C) += xrs700x_i2c.o
obj-$(CONFIG_NET_DSA_XRS700X_MDIO) += xrs700x_mdio.o
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/workqueue.h>
#include <linux/u64_stats_sync.h>
#include <uapi/linux/if_link.h>
struct xrs700x_info {
unsigned int id;
const char *name;
size_t num_ports;
};
extern const struct xrs700x_info xrs7003e_info;
extern const struct xrs700x_info xrs7003f_info;
extern const struct xrs700x_info xrs7004e_info;
extern const struct xrs700x_info xrs7004f_info;
struct xrs700x_port {
struct mutex mib_mutex; /* protects mib_data */
u64 *mib_data;
struct rtnl_link_stats64 stats64;
struct u64_stats_sync syncp;
};
struct xrs700x {
struct dsa_switch *ds;
struct device *dev;
void *priv;
struct regmap *regmap;
struct regmap_field *ps_forward;
struct regmap_field *ps_management;
struct regmap_field *ps_sel_speed;
struct regmap_field *ps_cur_speed;
struct delayed_work mib_work;
struct xrs700x_port *ports;
};
struct xrs700x *xrs700x_switch_alloc(struct device *base, void *devpriv);
int xrs700x_switch_register(struct xrs700x *priv);
void xrs700x_switch_remove(struct xrs700x *priv);
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 NovaTech LLC
* George McCollister <george.mccollister@gmail.com>
*/
#include <linux/bits.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include "xrs700x.h"
#include "xrs700x_reg.h"
static int xrs700x_i2c_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
unsigned char buf[4];
int ret;
buf[0] = reg >> 23 & 0xff;
buf[1] = reg >> 15 & 0xff;
buf[2] = reg >> 7 & 0xff;
buf[3] = (reg & 0x7f) << 1;
ret = i2c_master_send(i2c, buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "xrs i2c_master_send returned %d\n", ret);
return ret;
}
ret = i2c_master_recv(i2c, buf, 2);
if (ret < 0) {
dev_err(dev, "xrs i2c_master_recv returned %d\n", ret);
return ret;
}
*val = buf[0] << 8 | buf[1];
return 0;
}
static int xrs700x_i2c_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
unsigned char buf[6];
int ret;
buf[0] = reg >> 23 & 0xff;
buf[1] = reg >> 15 & 0xff;
buf[2] = reg >> 7 & 0xff;
buf[3] = (reg & 0x7f) << 1 | 1;
buf[4] = val >> 8 & 0xff;
buf[5] = val & 0xff;
ret = i2c_master_send(i2c, buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "xrs i2c_master_send returned %d\n", ret);
return ret;
}
return 0;
}
static const struct regmap_config xrs700x_i2c_regmap_config = {
.val_bits = 16,
.reg_stride = 2,
.reg_bits = 32,
.pad_bits = 0,
.write_flag_mask = 0,
.read_flag_mask = 0,
.reg_read = xrs700x_i2c_reg_read,
.reg_write = xrs700x_i2c_reg_write,
.max_register = 0,
.cache_type = REGCACHE_NONE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG
};
static int xrs700x_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *i2c_id)
{
struct xrs700x *priv;
int ret;
priv = xrs700x_switch_alloc(&i2c->dev, i2c);
if (!priv)
return -ENOMEM;
priv->regmap = devm_regmap_init(&i2c->dev, NULL, &i2c->dev,
&xrs700x_i2c_regmap_config);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&i2c->dev, "Failed to initialize regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, priv);
ret = xrs700x_switch_register(priv);
/* Main DSA driver may not be started yet. */
if (ret)
return ret;
return 0;
}
static int xrs700x_i2c_remove(struct i2c_client *i2c)
{
struct xrs700x *priv = i2c_get_clientdata(i2c);
xrs700x_switch_remove(priv);
return 0;
}
static const struct i2c_device_id xrs700x_i2c_id[] = {
{ "xrs700x-switch", 0 },
{},
};
MODULE_DEVICE_TABLE(i2c, xrs700x_i2c_id);
static const struct of_device_id xrs700x_i2c_dt_ids[] = {
{ .compatible = "arrow,xrs7003e", .data = &xrs7003e_info },
{ .compatible = "arrow,xrs7003f", .data = &xrs7003f_info },
{ .compatible = "arrow,xrs7004e", .data = &xrs7004e_info },
{ .compatible = "arrow,xrs7004f", .data = &xrs7004f_info },
{},
};
MODULE_DEVICE_TABLE(of, xrs700x_i2c_dt_ids);
static struct i2c_driver xrs700x_i2c_driver = {
.driver = {
.name = "xrs700x-i2c",
.of_match_table = of_match_ptr(xrs700x_i2c_dt_ids),
},
.probe = xrs700x_i2c_probe,
.remove = xrs700x_i2c_remove,
.id_table = xrs700x_i2c_id,
};
module_i2c_driver(xrs700x_i2c_driver);
MODULE_AUTHOR("George McCollister <george.mccollister@gmail.com>");
MODULE_DESCRIPTION("Arrow SpeedChips XRS700x DSA I2C driver");
MODULE_LICENSE("GPL v2");
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 NovaTech LLC
* George McCollister <george.mccollister@gmail.com>
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/mdio.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/if_vlan.h>
#include "xrs700x.h"
#include "xrs700x_reg.h"
#define XRS_MDIO_IBA0 0x10
#define XRS_MDIO_IBA1 0x11
#define XRS_MDIO_IBD 0x14
#define XRS_IB_READ 0x0
#define XRS_IB_WRITE 0x1
static int xrs700x_mdio_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct mdio_device *mdiodev = context;
struct device *dev = &mdiodev->dev;
u16 uval;
int ret;
uval = (u16)FIELD_GET(GENMASK(31, 16), reg);
ret = mdiobus_write(mdiodev->bus, mdiodev->addr, XRS_MDIO_IBA1, uval);
if (ret < 0) {
dev_err(dev, "xrs mdiobus_write returned %d\n", ret);
return ret;
}
uval = (u16)((reg & GENMASK(15, 1)) | XRS_IB_READ);
ret = mdiobus_write(mdiodev->bus, mdiodev->addr, XRS_MDIO_IBA0, uval);
if (ret < 0) {
dev_err(dev, "xrs mdiobus_write returned %d\n", ret);
return ret;
}
ret = mdiobus_read(mdiodev->bus, mdiodev->addr, XRS_MDIO_IBD);
if (ret < 0) {
dev_err(dev, "xrs mdiobus_read returned %d\n", ret);
return ret;
}
*val = (unsigned int)ret;
return 0;
}
static int xrs700x_mdio_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct mdio_device *mdiodev = context;
struct device *dev = &mdiodev->dev;
u16 uval;
int ret;
ret = mdiobus_write(mdiodev->bus, mdiodev->addr, XRS_MDIO_IBD, (u16)val);
if (ret < 0) {
dev_err(dev, "xrs mdiobus_write returned %d\n", ret);
return ret;
}
uval = (u16)FIELD_GET(GENMASK(31, 16), reg);
ret = mdiobus_write(mdiodev->bus, mdiodev->addr, XRS_MDIO_IBA1, uval);
if (ret < 0) {
dev_err(dev, "xrs mdiobus_write returned %d\n", ret);
return ret;
}
uval = (u16)((reg & GENMASK(15, 1)) | XRS_IB_WRITE);
ret = mdiobus_write(mdiodev->bus, mdiodev->addr, XRS_MDIO_IBA0, uval);
if (ret < 0) {
dev_err(dev, "xrs mdiobus_write returned %d\n", ret);
return ret;
}
return 0;
}
static const struct regmap_config xrs700x_mdio_regmap_config = {
.val_bits = 16,
.reg_stride = 2,
.reg_bits = 32,
.pad_bits = 0,
.write_flag_mask = 0,
.read_flag_mask = 0,
.reg_read = xrs700x_mdio_reg_read,
.reg_write = xrs700x_mdio_reg_write,
.max_register = XRS_VLAN(VLAN_N_VID - 1),
.cache_type = REGCACHE_NONE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG
};
static int xrs700x_mdio_probe(struct mdio_device *mdiodev)
{
struct xrs700x *priv;
int ret;
priv = xrs700x_switch_alloc(&mdiodev->dev, mdiodev);
if (!priv)
return -ENOMEM;
priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, mdiodev,
&xrs700x_mdio_regmap_config);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&mdiodev->dev, "Failed to initialize regmap: %d\n", ret);
return ret;
}
dev_set_drvdata(&mdiodev->dev, priv);
ret = xrs700x_switch_register(priv);
/* Main DSA driver may not be started yet. */
if (ret)
return ret;
return 0;
}
static void xrs700x_mdio_remove(struct mdio_device *mdiodev)
{
struct xrs700x *priv = dev_get_drvdata(&mdiodev->dev);
xrs700x_switch_remove(priv);
}
static const struct of_device_id xrs700x_mdio_dt_ids[] = {
{ .compatible = "arrow,xrs7003e", .data = &xrs7003e_info },
{ .compatible = "arrow,xrs7003f", .data = &xrs7003f_info },
{ .compatible = "arrow,xrs7004e", .data = &xrs7004e_info },
{ .compatible = "arrow,xrs7004f", .data = &xrs7004f_info },
{},
};
MODULE_DEVICE_TABLE(of, xrs700x_mdio_dt_ids);
static struct mdio_driver xrs700x_mdio_driver = {
.mdiodrv.driver = {
.name = "xrs700x-mdio",
.of_match_table = xrs700x_mdio_dt_ids,
},
.probe = xrs700x_mdio_probe,
.remove = xrs700x_mdio_remove,
};
mdio_module_driver(xrs700x_mdio_driver);
MODULE_AUTHOR("George McCollister <george.mccollister@gmail.com>");
MODULE_DESCRIPTION("Arrow SpeedChips XRS700x DSA MDIO driver");
MODULE_LICENSE("GPL v2");
/* SPDX-License-Identifier: GPL-2.0 */
/* Register Base Addresses */
#define XRS_DEVICE_ID_BASE 0x0
#define XRS_GPIO_BASE 0x10000
#define XRS_PORT_OFFSET 0x10000
#define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x))
#define XRS_RTC_BASE 0x280000
#define XRS_TS_OFFSET 0x8000
#define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x))
#define XRS_SWITCH_CONF_BASE 0x300000
/* Device Identification Registers */
#define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0)
#define XRS_DEV_ID1 (XRS_DEVICE_ID_BASE + 2)
#define XRS_INT_ID0 (XRS_DEVICE_ID_BASE + 4)
#define XRS_INT_ID1 (XRS_DEVICE_ID_BASE + 6)
#define XRS_REV_ID (XRS_DEVICE_ID_BASE + 8)
/* GPIO Registers */
#define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000)
#define XRS_INPUT_STATUS0 (XRS_GPIO_BASE + 0x1002)
#define XRS_CONFIG1 (XRS_GPIO_BASE + 0x1004)
#define XRS_INPUT_STATUS1 (XRS_GPIO_BASE + 0x1006)
#define XRS_CONFIG2 (XRS_GPIO_BASE + 0x1008)
#define XRS_INPUT_STATUS2 (XRS_GPIO_BASE + 0x100a)
/* Port Configuration Registers */
#define XRS_PORT_GEN_BASE(x) (XRS_PORT_BASE(x) + 0x0)
#define XRS_PORT_HSR_BASE(x) (XRS_PORT_BASE(x) + 0x2000)
#define XRS_PORT_PTP_BASE(x) (XRS_PORT_BASE(x) + 0x4000)
#define XRS_PORT_CNT_BASE(x) (XRS_PORT_BASE(x) + 0x6000)
#define XRS_PORT_IPO_BASE(x) (XRS_PORT_BASE(x) + 0x8000)
/* Port Configuration Registers - General and State */
#define XRS_PORT_STATE(x) (XRS_PORT_GEN_BASE(x) + 0x0)
#define XRS_PORT_FORWARDING 0
#define XRS_PORT_LEARNING 1
#define XRS_PORT_DISABLED 2
#define XRS_PORT_MODE_NORMAL 0
#define XRS_PORT_MODE_MANAGEMENT 1
#define XRS_PORT_SPEED_1000 0x12
#define XRS_PORT_SPEED_100 0x20
#define XRS_PORT_SPEED_10 0x30
#define XRS_PORT_VLAN(x) (XRS_PORT_GEN_BASE(x) + 0x10)
#define XRS_PORT_VLAN0_MAPPING(x) (XRS_PORT_GEN_BASE(x) + 0x12)
#define XRS_PORT_FWD_MASK(x) (XRS_PORT_GEN_BASE(x) + 0x14)
#define XRS_PORT_VLAN_PRIO(x) (XRS_PORT_GEN_BASE(x) + 0x16)
/* Port Configuration Registers - HSR/PRP */
#define XRS_HSR_CFG(x) (XRS_PORT_HSR_BASE(x) + 0x0)
/* Port Configuration Registers - PTP */
#define XRS_PTP_RX_SYNC_DELAY_NS_LO(x) (XRS_PORT_PTP_BASE(x) + 0x2)
#define XRS_PTP_RX_SYNC_DELAY_NS_HI(x) (XRS_PORT_PTP_BASE(x) + 0x4)
#define XRS_PTP_RX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0xa)
#define XRS_PTP_TX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0x12)
/* Port Configuration Registers - Counter */
#define XRS_CNT_CTRL(x) (XRS_PORT_CNT_BASE(x) + 0x0)
#define XRS_RX_GOOD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x200)
#define XRS_RX_GOOD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x202)
#define XRS_RX_BAD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x204)
#define XRS_RX_BAD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x206)
#define XRS_RX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x208)
#define XRS_RX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x20a)
#define XRS_RX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x20c)
#define XRS_RX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x20e)
#define XRS_RX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x210)
#define XRS_RX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x212)
#define XRS_RX_UNDERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x214)
#define XRS_RX_UNDERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x216)
#define XRS_RX_FRAGMENTS_L (XRS_PORT_CNT_BASE(0) + 0x218)
#define XRS_RX_FRAGMENTS_H (XRS_PORT_CNT_BASE(0) + 0x21a)
#define XRS_RX_OVERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x21c)
#define XRS_RX_OVERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x21e)
#define XRS_RX_JABBER_L (XRS_PORT_CNT_BASE(0) + 0x220)
#define XRS_RX_JABBER_H (XRS_PORT_CNT_BASE(0) + 0x222)
#define XRS_RX_ERR_L (XRS_PORT_CNT_BASE(0) + 0x224)
#define XRS_RX_ERR_H (XRS_PORT_CNT_BASE(0) + 0x226)
#define XRS_RX_CRC_L (XRS_PORT_CNT_BASE(0) + 0x228)
#define XRS_RX_CRC_H (XRS_PORT_CNT_BASE(0) + 0x22a)
#define XRS_RX_64_L (XRS_PORT_CNT_BASE(0) + 0x22c)
#define XRS_RX_64_H (XRS_PORT_CNT_BASE(0) + 0x22e)
#define XRS_RX_65_127_L (XRS_PORT_CNT_BASE(0) + 0x230)
#define XRS_RX_65_127_H (XRS_PORT_CNT_BASE(0) + 0x232)
#define XRS_RX_128_255_L (XRS_PORT_CNT_BASE(0) + 0x234)
#define XRS_RX_128_255_H (XRS_PORT_CNT_BASE(0) + 0x236)
#define XRS_RX_256_511_L (XRS_PORT_CNT_BASE(0) + 0x238)
#define XRS_RX_256_511_H (XRS_PORT_CNT_BASE(0) + 0x23a)
#define XRS_RX_512_1023_L (XRS_PORT_CNT_BASE(0) + 0x23c)
#define XRS_RX_512_1023_H (XRS_PORT_CNT_BASE(0) + 0x23e)
#define XRS_RX_1024_1536_L (XRS_PORT_CNT_BASE(0) + 0x240)
#define XRS_RX_1024_1536_H (XRS_PORT_CNT_BASE(0) + 0x242)
#define XRS_RX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x244)
#define XRS_RX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x246)
#define XRS_RX_WRONGLAN_L (XRS_PORT_CNT_BASE(0) + 0x248)
#define XRS_RX_WRONGLAN_H (XRS_PORT_CNT_BASE(0) + 0x24a)
#define XRS_RX_DUPLICATE_L (XRS_PORT_CNT_BASE(0) + 0x24c)
#define XRS_RX_DUPLICATE_H (XRS_PORT_CNT_BASE(0) + 0x24e)
#define XRS_TX_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x280)
#define XRS_TX_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x282)
#define XRS_TX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x284)
#define XRS_TX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x286)
#define XRS_TX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x288)
#define XRS_TX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x28a)
#define XRS_TX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x28c)
#define XRS_TX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x28e)
#define XRS_TX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x290)
#define XRS_TX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x292)
#define XRS_PRIQ_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c0)
#define XRS_PRIQ_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c2)
#define XRS_EARLY_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c4)
#define XRS_EARLY_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c6)
/* Port Configuration Registers - Inbound Policy 0 - 15 */
#define XRS_ETH_ADDR_CFG(x, p) (XRS_PORT_IPO_BASE(x) + \
(p) * 0x20 + 0x0)
#define XRS_ETH_ADDR_FWD_ALLOW(x, p) (XRS_PORT_IPO_BASE(x) + \
(p) * 0x20 + 0x2)
#define XRS_ETH_ADDR_FWD_MIRROR(x, p) (XRS_PORT_IPO_BASE(x) + \
(p) * 0x20 + 0x4)
#define XRS_ETH_ADDR_0(x, p) (XRS_PORT_IPO_BASE(x) + \
(p) * 0x20 + 0x8)
#define XRS_ETH_ADDR_1(x, p) (XRS_PORT_IPO_BASE(x) + \
(p) * 0x20 + 0xa)
#define XRS_ETH_ADDR_2(x, p) (XRS_PORT_IPO_BASE(x) + \
(p) * 0x20 + 0xc)
/* RTC Registers */
#define XRS_CUR_NSEC0 (XRS_RTC_BASE + 0x1004)
#define XRS_CUR_NSEC1 (XRS_RTC_BASE + 0x1006)
#define XRS_CUR_SEC0 (XRS_RTC_BASE + 0x1008)
#define XRS_CUR_SEC1 (XRS_RTC_BASE + 0x100a)
#define XRS_CUR_SEC2 (XRS_RTC_BASE + 0x100c)
#define XRS_TIME_CC0 (XRS_RTC_BASE + 0x1010)
#define XRS_TIME_CC1 (XRS_RTC_BASE + 0x1012)
#define XRS_TIME_CC2 (XRS_RTC_BASE + 0x1014)
#define XRS_STEP_SIZE0 (XRS_RTC_BASE + 0x1020)
#define XRS_STEP_SIZE1 (XRS_RTC_BASE + 0x1022)
#define XRS_STEP_SIZE2 (XRS_RTC_BASE + 0x1024)
#define XRS_ADJUST_NSEC0 (XRS_RTC_BASE + 0x1034)
#define XRS_ADJUST_NSEC1 (XRS_RTC_BASE + 0x1036)
#define XRS_ADJUST_SEC0 (XRS_RTC_BASE + 0x1038)
#define XRS_ADJUST_SEC1 (XRS_RTC_BASE + 0x103a)
#define XRS_ADJUST_SEC2 (XRS_RTC_BASE + 0x103c)
#define XRS_TIME_CMD (XRS_RTC_BASE + 0x1040)
/* Time Stamper Registers */
#define XRS_TS_CTRL(x) (XRS_TS_BASE(x) + 0x1000)
#define XRS_TS_INT_MASK(x) (XRS_TS_BASE(x) + 0x1008)
#define XRS_TS_INT_STATUS(x) (XRS_TS_BASE(x) + 0x1010)
#define XRS_TS_NSEC0(x) (XRS_TS_BASE(x) + 0x1104)
#define XRS_TS_NSEC1(x) (XRS_TS_BASE(x) + 0x1106)
#define XRS_TS_SEC0(x) (XRS_TS_BASE(x) + 0x1108)
#define XRS_TS_SEC1(x) (XRS_TS_BASE(x) + 0x110a)
#define XRS_TS_SEC2(x) (XRS_TS_BASE(x) + 0x110c)
#define XRS_PNCT0(x) (XRS_TS_BASE(x) + 0x1110)
#define XRS_PNCT1(x) (XRS_TS_BASE(x) + 0x1112)
/* Switch Configuration Registers */
#define XRS_SWITCH_GEN_BASE (XRS_SWITCH_CONF_BASE + 0x0)
#define XRS_SWITCH_TS_BASE (XRS_SWITCH_CONF_BASE + 0x2000)
#define XRS_SWITCH_VLAN_BASE (XRS_SWITCH_CONF_BASE + 0x4000)
/* Switch Configuration Registers - General */
#define XRS_GENERAL (XRS_SWITCH_GEN_BASE + 0x10)
#define XRS_GENERAL_TIME_TRAILER BIT(9)
#define XRS_GENERAL_MOD_SYNC BIT(10)
#define XRS_GENERAL_CUT_THRU BIT(13)
#define XRS_GENERAL_CLR_MAC_TBL BIT(14)
#define XRS_GENERAL_RESET BIT(15)
#define XRS_MT_CLEAR_MASK (XRS_SWITCH_GEN_BASE + 0x12)
#define XRS_ADDRESS_AGING (XRS_SWITCH_GEN_BASE + 0x20)
#define XRS_TS_CTRL_TX (XRS_SWITCH_GEN_BASE + 0x28)
#define XRS_TS_CTRL_RX (XRS_SWITCH_GEN_BASE + 0x2a)
#define XRS_INT_MASK (XRS_SWITCH_GEN_BASE + 0x2c)
#define XRS_INT_STATUS (XRS_SWITCH_GEN_BASE + 0x2e)
#define XRS_MAC_TABLE0 (XRS_SWITCH_GEN_BASE + 0x200)
#define XRS_MAC_TABLE1 (XRS_SWITCH_GEN_BASE + 0x202)
#define XRS_MAC_TABLE2 (XRS_SWITCH_GEN_BASE + 0x204)
#define XRS_MAC_TABLE3 (XRS_SWITCH_GEN_BASE + 0x206)
/* Switch Configuration Registers - Frame Timestamp */
#define XRS_TX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x0)
#define XRS_TX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x2)
#define XRS_TX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x4)
#define XRS_TX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x6)
#define XRS_TX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0x2 * (h) + 0xe)
#define XRS_RX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0x200)
#define XRS_RX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0x202)
#define XRS_RX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0x204)
#define XRS_RX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0x206)
#define XRS_RX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
0x2 * (h) + 0xe)
/* Switch Configuration Registers - VLAN */
#define XRS_VLAN(v) (XRS_SWITCH_VLAN_BASE + 0x2 * (v))
...@@ -46,6 +46,7 @@ struct phylink_link_state; ...@@ -46,6 +46,7 @@ struct phylink_link_state;
#define DSA_TAG_PROTO_AR9331_VALUE 16 #define DSA_TAG_PROTO_AR9331_VALUE 16
#define DSA_TAG_PROTO_RTL4_A_VALUE 17 #define DSA_TAG_PROTO_RTL4_A_VALUE 17
#define DSA_TAG_PROTO_HELLCREEK_VALUE 18 #define DSA_TAG_PROTO_HELLCREEK_VALUE 18
#define DSA_TAG_PROTO_XRS700X_VALUE 19
enum dsa_tag_protocol { enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
...@@ -67,6 +68,7 @@ enum dsa_tag_protocol { ...@@ -67,6 +68,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_AR9331 = DSA_TAG_PROTO_AR9331_VALUE, DSA_TAG_PROTO_AR9331 = DSA_TAG_PROTO_AR9331_VALUE,
DSA_TAG_PROTO_RTL4_A = DSA_TAG_PROTO_RTL4_A_VALUE, DSA_TAG_PROTO_RTL4_A = DSA_TAG_PROTO_RTL4_A_VALUE,
DSA_TAG_PROTO_HELLCREEK = DSA_TAG_PROTO_HELLCREEK_VALUE, DSA_TAG_PROTO_HELLCREEK = DSA_TAG_PROTO_HELLCREEK_VALUE,
DSA_TAG_PROTO_XRS700X = DSA_TAG_PROTO_XRS700X_VALUE,
}; };
struct packet_type; struct packet_type;
......
...@@ -139,4 +139,10 @@ config NET_DSA_TAG_TRAILER ...@@ -139,4 +139,10 @@ config NET_DSA_TAG_TRAILER
Say Y or M if you want to enable support for tagging frames at Say Y or M if you want to enable support for tagging frames at
with a trailed. e.g. Marvell 88E6060. with a trailed. e.g. Marvell 88E6060.
config NET_DSA_TAG_XRS700X
tristate "Tag driver for XRS700x switches"
help
Say Y or M if you want to enable support for tagging frames for
Arrow SpeedChips XRS700x switches that use a single byte tag trailer.
endif endif
...@@ -18,3 +18,4 @@ obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o ...@@ -18,3 +18,4 @@ obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
obj-$(CONFIG_NET_DSA_TAG_SJA1105) += tag_sja1105.o obj-$(CONFIG_NET_DSA_TAG_SJA1105) += tag_sja1105.o
obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
obj-$(CONFIG_NET_DSA_TAG_XRS700X) += tag_xrs700x.o
// SPDX-License-Identifier: GPL-2.0+
/*
* XRS700x tag format handling
* Copyright (c) 2008-2009 Marvell Semiconductor
* Copyright (c) 2020 NovaTech LLC
*/
#include <linux/bitops.h>
#include "dsa_priv.h"
static struct sk_buff *xrs700x_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct dsa_port *dp = dsa_slave_to_port(dev);
u8 *trailer;
trailer = skb_put(skb, 1);
trailer[0] = BIT(dp->index);
return skb;
}
static struct sk_buff *xrs700x_rcv(struct sk_buff *skb, struct net_device *dev,
struct packet_type *pt)
{
int source_port;
u8 *trailer;
trailer = skb_tail_pointer(skb) - 1;
source_port = ffs((int)trailer[0]) - 1;
if (source_port < 0)
return NULL;
skb->dev = dsa_master_find_slave(dev, 0, source_port);
if (!skb->dev)
return NULL;
if (pskb_trim_rcsum(skb, skb->len - 1))
return NULL;
/* Frame is forwarded by hardware, don't forward in software. */
skb->offload_fwd_mark = 1;
return skb;
}
static const struct dsa_device_ops xrs700x_netdev_ops = {
.name = "xrs700x",
.proto = DSA_TAG_PROTO_XRS700X,
.xmit = xrs700x_xmit,
.rcv = xrs700x_rcv,
.overhead = 1,
.tail_tag = true,
};
MODULE_LICENSE("GPL");
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_XRS700X);
module_dsa_tag_driver(xrs700x_netdev_ops);
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