Merge tetrachloride.(none):/mnt/stuff/kernel/2.5/bk-linus

into tetrachloride.(none):/mnt/stuff/kernel/2.5/agpgart

drivers/char/agp/agp.h

@@ -33,6 +33,7 @@ extern struct agp_bridge_data agp_bridge;
 
 /* Generic routines. */
 void agp_generic_agp_enable(u32 mode);
+int agp_generic_agp_3_0_enable(u32 mode);
 int agp_generic_create_gatt_table(void);
 int agp_generic_free_gatt_table(void);
 agp_memory *agp_create_memory(int scratch_pages);
@@ -290,6 +291,9 @@ struct agp_bridge_data {
 #define VIA_APSIZE	0x84
 #define VIA_ATTBASE	0x88
 
+/* VIA KT400 */
+#define VIA_AGPSEL	0xfd
+
 /* SiS registers */
 #define SIS_APBASE	0x10
 #define SIS_ATTBASE	0x90

drivers/char/agp/ali-agp.c

@@ -195,7 +195,7 @@ static struct aper_size_info_32 ali_generic_sizes[7] =
 	{4, 1024, 0, 3}
 };
 
-int __init ali_generic_setup (struct pci_dev *pdev)
+static int __init ali_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = ali_generic_masks;
 	agp_bridge.num_of_masks = 1;
@@ -338,17 +338,20 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 }
 
 
-
-
-static int agp_ali_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_ali_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
-		return -ENODEV;
+	u8 cap_ptr = 0;
 
-	agp_bridge.dev = dev;
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
+		return -ENODEV;
 
 	/* probe for known chipsets */
-	if (agp_lookup_host_bridge (dev) != -ENODEV ) {
+	if (agp_lookup_host_bridge(dev) != -ENODEV) {
+		agp_bridge.dev = dev;
+		agp_bridge.capndx = cap_ptr;
+		/* Fill in the mode register */
+		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode);
 		agp_register_driver(dev);
 		return 0;
 	}
@@ -369,7 +372,7 @@ static struct pci_device_id agp_ali_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_ali_pci_table);
 
-static struct pci_driver agp_ali_pci_driver = {
+static struct __initdata pci_driver agp_ali_pci_driver = {
 	.name		= "agpgart-ali",
 	.id_table	= agp_ali_pci_table,
 	.probe		= agp_ali_probe,

drivers/char/agp/amd-k7-agp.c

@@ -351,7 +351,7 @@ static struct gatt_mask amd_irongate_masks[] =
 	{.mask = 0x00000001, .type = 0}
 };
 
-int __init amd_irongate_setup (struct pci_dev *pdev)
+static int __init amd_irongate_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = amd_irongate_masks;
 	agp_bridge.num_of_masks = 1;
@@ -439,25 +439,23 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 
 /* Supported Device Scanning routine */
 
-static int __init agp_find_supported_device(struct pci_dev *dev)
+static int __init agp_amdk7_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	agp_bridge.dev = dev;
+	u8 cap_ptr = 0;
 
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
 		return -ENODEV;
 
-	/* probe for known chipsets */
-	return agp_lookup_host_bridge (dev);
-}
-
-
-static int agp_amdk7_probe (struct pci_dev *dev, const struct pci_device_id *ent)
-{
-	if (agp_find_supported_device(dev) == 0) {
+	if (agp_lookup_host_bridge(dev) != -ENODEV) {
+		agp_bridge.dev = dev;
+		agp_bridge.capndx = cap_ptr;
+		/* Fill in the mode register */
+		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode);
 		agp_register_driver(dev);
 		return 0;
 	}
-	return -ENODEV;	
+	return -ENODEV;
 }
 
 static struct pci_device_id agp_amdk7_pci_table[] __initdata = {
@@ -474,7 +472,7 @@ static struct pci_device_id agp_amdk7_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
 
-static struct pci_driver agp_amdk7_pci_driver = {
+static struct __initdata pci_driver agp_amdk7_pci_driver = {
 	.name		= "agpgart-amdk7",
 	.id_table	= agp_amdk7_pci_table,
 	.probe		= agp_amdk7_probe,

drivers/char/agp/amd-k8-agp.c

@@ -370,7 +370,7 @@ static void agp_x86_64_agp_enable(u32 mode)
 	}
 
 
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 4, &command);
+	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &command);
 
 	/*
 	 * PASS2: go through all devices that claim to be
@@ -429,7 +429,7 @@ static void agp_x86_64_agp_enable(u32 mode)
 
 	command |= 0x100;
 
-	pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx + 8, command);
+	pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+8, command);
 
 	/*
 	 * PASS4: Go through all AGP devices and update the
@@ -475,11 +475,19 @@ static int __init amd_8151_setup (struct pci_dev *pdev)
 }
 
 
-static int agp_amdk8_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_amdk8_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
+	u8 cap_ptr = 0;
+
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
 		return -ENODEV;
 
+	agp_bridge.dev = dev;
+	agp_bridge.capndx = cap_ptr;
+
+	/* Fill in the mode register */
+	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode);
 	amd_8151_setup(dev);
 	agp_register_driver(dev);
 	return 0;
@@ -499,7 +507,7 @@ static struct pci_device_id agp_amdk8_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_amdk8_pci_table);
 
-static struct pci_driver agp_amdk8_pci_driver = {
+static struct __initdata pci_driver agp_amdk8_pci_driver = {
 	.name		= "agpgart-amd-k8",
 	.id_table	= agp_amdk8_pci_table,
 	.probe		= agp_amdk8_probe,

drivers/char/agp/backend.c

@@ -112,23 +112,13 @@ static struct agp_version agp_current_version =
 	.minor = AGPGART_VERSION_MINOR,
 };
 
-static int __init agp_backend_initialize(struct pci_dev *dev)
+static int agp_backend_initialize(struct pci_dev *dev)
 {
 	int size_value, rc, got_gatt=0, got_keylist=0;
-	u8 cap_ptr = 0;
 
 	agp_bridge.max_memory_agp = agp_find_max();
 	agp_bridge.version = &agp_current_version;
 
-	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
-	if (cap_ptr == 0)
-		return -ENODEV;
-	agp_bridge.capndx = cap_ptr;
-
-	/* Fill in the mode register */
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 4, &agp_bridge.mode);
-
-
 	if (agp_bridge.needs_scratch_page == TRUE) {
 		void *addr;
 		addr = agp_bridge.agp_alloc_page();
@@ -272,13 +262,6 @@ int agp_unregister_driver(void)
 	return 0;
 }
 
-int __exit agp_exit(void)
-{
-	if (agp_count==0)
-		return -EBUSY;
-
-	return 0;
-}
 
 int __init agp_init(void)
 {
@@ -299,7 +282,6 @@ int __init agp_init(void)
 
 #ifndef CONFIG_GART_IOMMU
 module_init(agp_init);
-module_exit(agp_exit);
 #endif
 
 EXPORT_SYMBOL(agp_backend_acquire);

drivers/char/agp/generic-3.0.c

 #include <linux/list.h>
 #include <linux/pci.h>
-
-
-//#include <linux/pagemap.h>
-//#include <linux/miscdevice.h>
-//#include <linux/pm.h>
 #include <linux/agp_backend.h>
 
 #include "agp.h"
@@ -529,7 +524,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
  * (AGP 3.0 devices are required to operate as AGP 2.0 devices 
  * when not using 3.0 electricals.
  */
-void agp_generic_agp_3_0_enable(u32 mode)
+int agp_generic_agp_3_0_enable(u32 mode)
 {
 	u32 ncapid, major, minor, agp_3_0;
 
@@ -548,9 +543,9 @@ void agp_generic_agp_3_0_enable(u32 mode)
 		 */
 		if((agp_3_0 >> 3) & 0x1) {
 			agp_3_0_node_enable(mode, minor);
-			return;
+			return TRUE;
 		}
 	}
-	agp_generic_agp_enable(mode);
+	return FALSE;
 }
 

drivers/char/agp/hp-agp.c

@@ -216,8 +216,7 @@ static void hp_zx1_tlbflush(agp_memory * mem)
 {
 	struct _hp_private *hp = &hp_private;
 
-	OUTREG64(hp->registers, HP_ZX1_PCOM, 
-		hp->gart_base | log2(hp->gart_size));
+	OUTREG64(hp->registers, HP_ZX1_PCOM, hp->gart_base | log2(hp->gart_size));
 	INREG64(hp->registers, HP_ZX1_PCOM);
 }
 
@@ -251,7 +250,7 @@ static int hp_zx1_create_gatt_table(void)
 static int hp_zx1_free_gatt_table(void)
 {
 	struct _hp_private *hp = &hp_private;
-	
+
 	if (hp->io_pdir_owner)
 		free_pages((unsigned long) hp->io_pdir,
 			    get_order(hp->io_pdir_size));
@@ -329,7 +328,7 @@ static unsigned long hp_zx1_mask_memory(unsigned long addr, int type)
 	return HP_ZX1_PDIR_VALID_BIT | addr;
 }
 
-int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
+static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
 {
 	agp_bridge.masks = hp_zx1_masks;
 	agp_bridge.num_of_masks = 1;
@@ -368,21 +367,22 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		return hp_zx1_setup(dev);
 	}
 	return -ENODEV;
+}
 
-static int agp_hp_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_hp_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
 	if (agp_find_supported_device(dev) == 0) {
 		agp_register_driver(dev);
 		return 0;
 	}
-	return -ENODEV;	
+	return -ENODEV;
 }
 
 static struct pci_device_id agp_hp_pci_table[] __initdata = {
 	{
 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
 	.class_mask	= ~0,
-	.vendor_id	= PCI_VENDOR_ID_HP,
+	.vendor		= PCI_VENDOR_ID_HP,
 	.device		= PCI_DEVICE_ID_HP_ZX1_LBA,
 	.subvendor	= PCI_ANY_ID,
 	.subdevice	= PCI_ANY_ID,
@@ -392,7 +392,7 @@ static struct pci_device_id agp_hp_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_pci_table);
 
-static struct pci_driver agp_hp_pci_driver = {
+static struct __initdata pci_driver agp_hp_pci_driver = {
 	.name		= "agpgart-hp",
 	.id_table	= agp_hp_pci_table,
 	.probe		= agp_hp_probe,
@@ -412,7 +412,7 @@ static int __init agp_hp_init(void)
 static void __exit agp_hp_cleanup(void)
 {
 	agp_unregister_driver();
-	pci_unregister_driver(&agp_pci_driver);
+	pci_unregister_driver(&agp_hp_pci_driver);
 }
 
 module_init(agp_hp_init);

drivers/char/agp/i460-agp.c

@@ -523,7 +523,7 @@ static unsigned long i460_mask_memory (unsigned long addr, int type)
 		| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12));
 }
 
-int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
+static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
 {
 	agp_bridge.num_of_masks = 1;
 	agp_bridge.masks = i460_masks;
@@ -560,55 +560,60 @@ int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
 	return 0;
 }
 
-static int agp_intel_i460_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_intel_i460_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
+	u8 cap_ptr = 0;
+
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
 		return -ENODEV;
 
+	agp_bridge.dev = dev;
+	agp_bridge.capndx = cap_ptr;
 	intel_i460_setup(dev);
 	agp_register_driver(dev);
 	return 0;
 }
 
-static struct pci_device_id agp_i460_pci_table[] __initdata = {
+static struct pci_device_id agp_intel_i460_pci_table[] __initdata = {
 	{
 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
 	.class_mask	= ~0,
 	.vendor		= PCI_VENDOR_ID_INTEL,
-	.device		= PCI_DEVICE_ID_INTEL_460GX,
+	.device		= PCI_DEVICE_ID_INTEL_84460GX,
 	.subvendor	= PCI_ANY_ID,
 	.subdevice	= PCI_ANY_ID,
 	},
 	{ }
 };
 
-MODULE_DEVICE_TABLE(pci, agp_i460_pci_table);
+MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);
 
-static struct pci_driver agp_i460_pci_driver = {
+static struct __initdata pci_driver agp_intel_i460_pci_driver = {
 	.name		= "agpgart-intel-i460",
-	.id_table	= agp_i460_pci_table,
-	.probe		= agp_i460_probe,
+	.id_table	= agp_intel_i460_pci_table,
+	.probe		= agp_intel_i460_probe,
 };
 
-static int __init agp_i460_init(void)
+static int __init agp_intel_i460_init(void)
 {
 	int ret_val;
 
-	ret_val = pci_module_init(&agp_i460_pci_driver);
+	ret_val = pci_module_init(&agp_intel_i460_pci_driver);
 	if (ret_val)
 		agp_bridge.type = NOT_SUPPORTED;
 
 	return ret_val;
 }
 
-static void __exit agp_i460_cleanup(void)
+static void __exit agp_intel_i460_cleanup(void)
 {
 	agp_unregister_driver();
-	pci_unregister_driver(&agp_i460_pci_driver);
+	pci_unregister_driver(&agp_intel_i460_pci_driver);
 }
 
-module_init(agp_i460_init);
-module_exit(agp_i460_cleanup);
+module_init(agp_intel_i460_init);
+module_exit(agp_intel_i460_cleanup);
 
 MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
 MODULE_LICENSE("GPL and additional rights");

drivers/char/agp/i7x05-agp.c

@@ -87,6 +87,11 @@ static aper_size_info_16 intel_7505_sizes[7] =
 	{4, 1024, 0, 0xf3f}
 };
 
+static void i7505_setup (u32 mode)
+{
+	if ((agp_generic_agp_3_0_enable)==FALSE)
+		agp_generic_agp_enable(mode);
+}
 
 static int __init intel_7505_setup (struct pci_dev *pdev)
 {
@@ -102,7 +107,7 @@ static int __init intel_7505_setup (struct pci_dev *pdev)
 	agp_bridge.cleanup = intel_7505_cleanup;
 	agp_bridge.tlb_flush = intel_7505_tlbflush;
 	agp_bridge.mask_memory = intel_mask_memory;
-	agp_bridge.agp_enable = agp_generic_agp_3_0_enable;
+	agp_bridge.agp_enable = i7505_enable;
 	agp_bridge.cache_flush = global_cache_flush;
 	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
 	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
@@ -161,27 +166,26 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 }
 
 
-static int __init agp_find_supported_device(struct pci_dev *dev)
+static int __init agp_i7x05_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	agp_bridge.dev = dev;
+	u8 cap_ptr = 0;
 
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
 		return -ENODEV;
 
-	/* probe for known chipsets */
-	return agp_lookup_host_bridge(dev);
-}
-
-
-static int agp_i7x05_probe (struct pci_dev *dev, const struct pci_device_id *ent)
-{
-	if (agp_find_supported_device(dev) == 0) {
+	if (agp_lookup_host_bridge(dev) != -ENODEV) {
+		agp_bridge.dev = dev;
+		agp_bridge.capndx = cap_ptr;
+		/* Fill in the mode register */
+		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode)
 		agp_register_driver(dev);
 		return 0;
 	}
-	return -ENODEV;	
+	return -ENODEV;
 }
 
+
 static struct pci_device_id agp_i7x05_pci_table[] __initdata = {
 	{
 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
@@ -196,7 +200,7 @@ static struct pci_device_id agp_i7x05_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_i7x05_pci_table);
 
-static struct pci_driver agp_i7x05_pci_driver = {
+static struct __initdata pci_driver agp_i7x05_pci_driver = {
 	.name		= "agpgart-i7x05",
 	.id_table	= agp_i7x05_pci_table,
 	.probe		= agp_i7x05_probe,

drivers/char/agp/intel-agp.c

@@ -14,12 +14,12 @@ static int agp_try_unsupported __initdata = 0;
 static struct aper_size_info_fixed intel_i810_sizes[] =
 {
 	{64, 16384, 4},
-     /* The 32M mode still requires a 64k gatt */
+	/* The 32M mode still requires a 64k gatt */
 	{32, 8192, 4}
 };
 
-#define AGP_DCACHE_MEMORY 1
-#define AGP_PHYS_MEMORY   2
+#define AGP_DCACHE_MEMORY	1
+#define AGP_PHYS_MEMORY		2
 
 static struct gatt_mask intel_i810_masks[] =
 {
@@ -48,12 +48,12 @@ static int intel_i810_fetch_size(void)
 	}
 	if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 		agp_bridge.previous_size =
-		    agp_bridge.current_size = (void *) (values + 1);
+			agp_bridge.current_size = (void *) (values + 1);
 		agp_bridge.aperture_size_idx = 1;
 		return values[1].size;
 	} else {
 		agp_bridge.previous_size =
-		    agp_bridge.current_size = (void *) (values);
+			agp_bridge.current_size = (void *) (values);
 		agp_bridge.aperture_size_idx = 0;
 		return values[0].size;
 	}
@@ -72,11 +72,10 @@ static int intel_i810_configure(void)
 	pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
 	temp &= 0xfff80000;
 
-	intel_i810_private.registers =
-	    (volatile u8 *) ioremap(temp, 128 * 4096);
+	intel_i810_private.registers = (volatile u8 *) ioremap(temp, 128 * 4096);
 
 	if ((INREG32(intel_i810_private.registers, I810_DRAM_CTL)
-	     & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
+		& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 		/* This will need to be dynamically assigned */
 		printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 		intel_i810_private.num_dcache_entries = 1024;
@@ -114,7 +113,7 @@ static void intel_i810_agp_enable(u32 mode)
 }
 
 static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
-				     int type)
+				int type)
 {
 	int i, j, num_entries;
 	void *temp;
@@ -132,12 +131,10 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
 	}
 
 	if (type != 0 || mem->type != 0) {
-		if ((type == AGP_DCACHE_MEMORY) &&
-		    (mem->type == AGP_DCACHE_MEMORY)) {
+		if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) {
 			/* special insert */
 			CACHE_FLUSH();
-			for (i = pg_start;
-			     i < (pg_start + mem->page_count); i++) {
+			for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 				OUTREG32(intel_i810_private.registers,
 					 I810_PTE_BASE + (i * 4),
 					 (i * 4096) | I810_PTE_LOCAL |
@@ -147,15 +144,13 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
 			agp_bridge.tlb_flush(mem);
 			return 0;
 		}
-	        if((type == AGP_PHYS_MEMORY) &&
-		   (mem->type == AGP_PHYS_MEMORY)) {
-		   goto insert;
-		}
+		if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
+			goto insert;
 		return -EINVAL;
 	}
 
 insert:
-   	CACHE_FLUSH();
+	CACHE_FLUSH();
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 		OUTREG32(intel_i810_private.registers,
 			 I810_PTE_BASE + (j * 4), mem->memory[i]);
@@ -167,7 +162,7 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
 }
 
 static int intel_i810_remove_entries(agp_memory * mem, off_t pg_start,
-				     int type)
+				int type)
 {
 	int i;
 
@@ -199,7 +194,7 @@ static agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 		new->page_count = pg_count;
 		new->num_scratch_pages = 0;
 		vfree(new->memory);
-	   	MOD_INC_USE_COUNT;
+		MOD_INC_USE_COUNT;
 		return new;
 	}
 	if(type == AGP_PHYS_MEMORY) {
@@ -209,15 +204,14 @@ static agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 		 * Xserver still writes to it through the agp
 		 * aperture
 		 */
-	   	if (pg_count != 1) {
-		   	return NULL;
-		}
-	   	new = agp_create_memory(1);
+		if (pg_count != 1)
+			return NULL;
 
-		if (new == NULL) {
+		new = agp_create_memory(1);
+		if (new == NULL)
 			return NULL;
-		}
-	   	MOD_INC_USE_COUNT;
+
+		MOD_INC_USE_COUNT;
 		addr = agp_bridge.agp_alloc_page();
 
 		if (addr == NULL) {
@@ -227,25 +221,23 @@ static agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 		}
 		new->memory[0] = agp_bridge.mask_memory(virt_to_phys(addr), type);
 		new->page_count = 1;
-	   	new->num_scratch_pages = 1;
-	   	new->type = AGP_PHYS_MEMORY;
-	        new->physical = virt_to_phys((void *) new->memory[0]);
-	   	return new;
+		new->num_scratch_pages = 1;
+		new->type = AGP_PHYS_MEMORY;
+		new->physical = virt_to_phys((void *) new->memory[0]);
+		return new;
 	}
-   
 	return NULL;
 }
 
 static void intel_i810_free_by_type(agp_memory * curr)
 {
 	agp_free_key(curr->key);
-   	if(curr->type == AGP_PHYS_MEMORY) {
-	   	agp_bridge.agp_destroy_page(
-				 phys_to_virt(curr->memory[0]));
+	if(curr->type == AGP_PHYS_MEMORY) {
+		agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[0]));
 		vfree(curr->memory);
 	}
 	kfree(curr);
-   	MOD_DEC_USE_COUNT;
+	MOD_DEC_USE_COUNT;
 }
 
 static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
@@ -254,7 +246,7 @@ static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
 	return addr | agp_bridge.masks[type].mask;
 }
 
-int __init intel_i810_setup(struct pci_dev *i810_dev)
+static int __init intel_i810_setup(struct pci_dev *i810_dev)
 {
 	intel_i810_private.i810_dev = i810_dev;
 
@@ -295,7 +287,7 @@ static struct aper_size_info_fixed intel_i830_sizes[] =
 };
 
 static struct _intel_i830_private {
-	struct pci_dev *i830_dev;   /* device one */
+	struct pci_dev *i830_dev;		/* device one */
 	volatile u8 *registers;
 	int gtt_entries;
 } intel_i830_private;
@@ -533,7 +525,7 @@ static agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 	return(NULL);
 }
 
-int __init intel_i830_setup(struct pci_dev *i830_dev)
+static int __init intel_i830_setup(struct pci_dev *i830_dev)
 {
 	intel_i830_private.i830_dev = i830_dev;
 
@@ -581,8 +573,7 @@ static int intel_fetch_size(void)
 
 	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
 		if (temp == values[i].size_value) {
-			agp_bridge.previous_size =
-			    agp_bridge.current_size = (void *) (values + i);
+			agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
 			agp_bridge.aperture_size_idx = i;
 			return values[i].size;
 		}
@@ -627,11 +618,11 @@ static void intel_tlbflush(agp_memory * mem)
 
 static void intel_8xx_tlbflush(agp_memory * mem)
 {
-  u32 temp;
-  pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
-  pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp & ~(1 << 7));
-  pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
-  pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp | (1 << 7));
+	u32 temp;
+	pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
+	pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp & ~(1 << 7));
+	pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
+	pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp | (1 << 7));
 }
 
 
@@ -683,7 +674,7 @@ static int intel_configure(void)
 	/* paccfg/nbxcfg */
 	pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
 	pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG,
-			      (temp2 & ~(1 << 10)) | (1 << 9));
+			(temp2 & ~(1 << 10)) | (1 << 9));
 	/* clear any possible error conditions */
 	pci_write_config_byte(agp_bridge.dev, INTEL_ERRSTS + 1, 7);
 	return 0;
@@ -708,7 +699,7 @@ static int intel_815_configure(void)
 	/* attbase - aperture base */
 	/* the Intel 815 chipset spec. says that bits 29-31 in the
 	* ATTBASE register are reserved -> try not to write them */
-	if (agp_bridge.gatt_bus_addr &  INTEL_815_ATTBASE_MASK)
+	if (agp_bridge.gatt_bus_addr & INTEL_815_ATTBASE_MASK)
 		panic("gatt bus addr too high");
 	pci_read_config_dword(agp_bridge.dev, INTEL_ATTBASE, &addr);
 	addr &= INTEL_815_ATTBASE_MASK;
@@ -729,7 +720,7 @@ static int intel_815_configure(void)
 
 static void intel_820_tlbflush(agp_memory * mem)
 {
-  return;
+	return;
 }
 
 static void intel_820_cleanup(void)
@@ -740,9 +731,9 @@ static void intel_820_cleanup(void)
 	previous_size = A_SIZE_8(agp_bridge.previous_size);
 	pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp);
 	pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR, 
-			      temp & ~(1 << 1));
+			temp & ~(1 << 1));
 	pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
-			      previous_size->size_value);
+			previous_size->size_value);
 }
 
 
@@ -974,10 +965,10 @@ static struct aper_size_info_16 intel_generic_sizes[7] =
 
 static struct aper_size_info_8 intel_830mp_sizes[4] = 
 {
-  {256, 65536, 6, 0},
-  {128, 32768, 5, 32},
-  {64, 16384, 4, 48},
-  {32, 8192, 3, 56}
+	{256, 65536, 6, 0},
+	{128, 32768, 5, 32},
+	{64, 16384, 4, 48},
+	{32, 8192, 3, 56}
 };
 
 static int __init intel_generic_setup (struct pci_dev *pdev)
@@ -1322,7 +1313,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 	/* try init anyway, if user requests it */
 	if (agp_try_unsupported) {
 		printk(KERN_WARNING PFX "Trying generic Intel routines"
-		       " for device id: %04x\n", pdev->device);
+			" for device id: %04x\n", pdev->device);
 		agp_bridge.type = INTEL_GENERIC;
 		return intel_generic_setup(pdev);
 	}
@@ -1338,6 +1329,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 static int __init agp_find_supported_device(struct pci_dev *dev)
 {
 	struct pci_dev *i810_dev;
+	u8 cap_ptr = 0;
 
 	agp_bridge.dev = dev;
 
@@ -1347,7 +1339,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1, NULL);
 		if (i810_dev == NULL) {
 			printk(KERN_ERR PFX "Detected an Intel i810,"
-			       " but could not find the secondary device.\n");
+				" but could not find the secondary device.\n");
 			return -ENODEV;
 		}
 		printk(KERN_INFO PFX "Detected an Intel i810 Chipset.\n");
@@ -1358,7 +1350,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, NULL);
 		if (i810_dev == NULL) {
 			printk(KERN_ERR PFX "Detected an Intel i810 DC100, but could not find the "
-			       "secondary device.\n");
+				"secondary device.\n");
 			return -ENODEV;
 		}
 		printk(KERN_INFO PFX "Detected an Intel i810 DC100 Chipset.\n");
@@ -1369,7 +1361,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG, NULL);
 		if (i810_dev == NULL) {
 			printk(KERN_ERR PFX "Detected an Intel i810 E"
-			    ", but could not find the secondary device.\n");
+				", but could not find the secondary device.\n");
 			return -ENODEV;
 		}
 		printk(KERN_INFO PFX "Detected an Intel i810 E Chipset.\n");
@@ -1377,11 +1369,11 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		return intel_i810_setup(i810_dev);
 
 	 case PCI_DEVICE_ID_INTEL_82815_MC:
-	   /* The i815 can operate either as an i810 style
-	    * integrated device, or as an AGP4X motherboard.
-	    *
-	    * This only addresses the first mode:
-	    */
+		/* The i815 can operate either as an i810 style
+		 * integrated device, or as an AGP4X motherboard.
+		 *
+		 * This only addresses the first mode:
+		 */
 		i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, NULL);
 		if (i810_dev == NULL) {
 			printk(KERN_ERR PFX "agpgart: Detected an "
@@ -1413,7 +1405,7 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		printk(KERN_INFO PFX "Detected an Intel 845G Chipset.\n");
 		agp_bridge.type = INTEL_I810;
 		return intel_i830_setup(i810_dev);
-		   
+
 	case PCI_DEVICE_ID_INTEL_82830_HB:
 		i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830_CGC, NULL);
 		if(i810_dev && PCI_FUNC(i810_dev->devfn) != 0)
@@ -1433,15 +1425,20 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 		break;
 	}
 
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
 		return -ENODEV;
+	agp_bridge.capndx = cap_ptr;
+
+	/* Fill in the mode register */
+	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode);
 
 	/* probe for known chipsets */
 	return agp_lookup_host_bridge(dev);
 }
 
 
-static int agp_intel_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_intel_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
 	if (agp_find_supported_device(dev) == 0) {
 		agp_register_driver(dev);
@@ -1464,7 +1461,7 @@ static struct pci_device_id agp_intel_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
 
-static struct pci_driver agp_intel_pci_driver = {
+static struct __initdata pci_driver agp_intel_pci_driver = {
 	.name		= "agpgart-intel",
 	.id_table	= agp_intel_pci_table,
 	.probe		= agp_intel_probe,
@@ -1498,4 +1495,3 @@ module_exit(agp_intel_cleanup);
 MODULE_PARM(agp_try_unsupported, "1i");
 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
 MODULE_LICENSE("GPL and additional rights");
-

drivers/char/agp/sis-agp.c

@@ -86,7 +86,7 @@ static struct gatt_mask sis_generic_masks[] =
 	{.mask = 0x00000000, .type = 0}
 };
 
-int __init sis_generic_setup (struct pci_dev *pdev)
+static int __init sis_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = sis_generic_masks;
 	agp_bridge.num_of_masks = 1;
@@ -223,25 +223,24 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 }
 
 
-static int __init agp_find_supported_device(struct pci_dev *dev)
+static int __init agp_sis_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	agp_bridge.dev = dev;
+	u8 cap_ptr = 0;
 
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
 		return -ENODEV;
 
 	/* probe for known chipsets */
-	return agp_lookup_host_bridge (dev);
-}
-
-
-static int agp_sis_probe (struct pci_dev *dev, const struct pci_device_id *ent)
-{
-	if (agp_find_supported_device(dev) == 0) {
+	if (agp_lookup_host_bridge(dev) != -ENODEV) {
+		agp_bridge.dev = dev;
+		agp_bridge.capndx = cap_ptr;
+		/* Fill in the mode register */
+		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode);
 		agp_register_driver(dev);
 		return 0;
 	}
-	return -ENODEV;	
+	return -ENODEV;
 }
 
 static struct pci_device_id agp_sis_pci_table[] __initdata = {
@@ -258,13 +257,13 @@ static struct pci_device_id agp_sis_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
 
-static struct pci_driver agp_sis_pci_driver = {
+static struct __initdata pci_driver agp_sis_pci_driver = {
 	.name		= "agpgart-sis",
 	.id_table	= agp_sis_pci_table,
 	.probe		= agp_sis_probe,
 };
 
-int __init agp_sis_init(void)
+static int __init agp_sis_init(void)
 {
 	int ret_val;
 

drivers/char/agp/sworks-agp.c

@@ -169,9 +169,7 @@ static int serverworks_create_gatt_table(void)
 	 * used to program the agp master not the cpu
 	 */
 
-	pci_read_config_dword(agp_bridge.dev,
-			      serverworks_private.gart_addr_ofs,
-			      &temp);
+	pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
 	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 
 	/* Calculate the agp offset */	
@@ -206,18 +204,11 @@ static int serverworks_fetch_size(void)
 	struct aper_size_info_lvl2 *values;
 
 	values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
-	pci_read_config_dword(agp_bridge.dev,
-			      serverworks_private.gart_addr_ofs,
-			      &temp);
-	pci_write_config_dword(agp_bridge.dev,
-			       serverworks_private.gart_addr_ofs,
-			       SVWRKS_SIZE_MASK);
-	pci_read_config_dword(agp_bridge.dev,
-			      serverworks_private.gart_addr_ofs,
-			      &temp2);
-	pci_write_config_dword(agp_bridge.dev,
-			       serverworks_private.gart_addr_ofs,
-			       temp);
+	pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
+	pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,
+					SVWRKS_SIZE_MASK);
+	pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp2);
+	pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,temp);
 	temp2 &= SVWRKS_SIZE_MASK;
 
 	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
@@ -245,9 +236,7 @@ static int serverworks_configure(void)
 	current_size = A_SIZE_LVL2(agp_bridge.current_size);
 
 	/* Get the memory mapped registers */
-	pci_read_config_dword(agp_bridge.dev,
-			      serverworks_private.mm_addr_ofs,
-			      &temp);
+	pci_read_config_dword(agp_bridge.dev, serverworks_private.mm_addr_ofs, &temp);
 	temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 	serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
 
@@ -269,7 +258,7 @@ static int serverworks_configure(void)
 	agp_bridge.tlb_flush(NULL);
 
 	pci_read_config_byte(serverworks_private.svrwrks_dev, 0x34, &cap_ptr);
-	if (cap_ptr != 0x00) {
+	if (cap_ptr != 0) {
 		do {
 			pci_read_config_dword(serverworks_private.svrwrks_dev,
 					      cap_ptr, &cap_id);
@@ -277,30 +266,21 @@ static int serverworks_configure(void)
 			if ((cap_id & 0xff) != 0x02)
 				cap_ptr = (cap_id >> 8) & 0xff;
 		}
-		while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0x00));
+		while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0));
 	}
 	agp_bridge.capndx = cap_ptr;
 
 	/* Fill in the mode register */
 	pci_read_config_dword(serverworks_private.svrwrks_dev,
-			      agp_bridge.capndx + 4,
-			      &agp_bridge.mode);
+			      agp_bridge.capndx+4, &agp_bridge.mode);
 
-	pci_read_config_byte(agp_bridge.dev,
-			     SVWRKS_CACHING,
-			     &enable_reg);
+	pci_read_config_byte(agp_bridge.dev, SVWRKS_CACHING, &enable_reg);
 	enable_reg &= ~0x3;
-	pci_write_config_byte(agp_bridge.dev,
-			      SVWRKS_CACHING,
-			      enable_reg);
+	pci_write_config_byte(agp_bridge.dev, SVWRKS_CACHING, enable_reg);
 
-	pci_read_config_byte(agp_bridge.dev,
-			     SVWRKS_FEATURE,
-			     &enable_reg);
+	pci_read_config_byte(agp_bridge.dev, SVWRKS_FEATURE, &enable_reg);
 	enable_reg |= (1<<6);
-	pci_write_config_byte(agp_bridge.dev,
-			      SVWRKS_FEATURE,
-			      enable_reg);
+	pci_write_config_byte(agp_bridge.dev,SVWRKS_FEATURE, enable_reg);
 
 	return 0;
 }
@@ -532,7 +512,7 @@ static void serverworks_agp_enable(u32 mode)
 	}
 }
 
-int __init serverworks_setup (struct pci_dev *pdev)
+static int __init serverworks_setup (struct pci_dev *pdev)
 {
 	u32 temp;
 	u32 temp2;
@@ -606,7 +586,6 @@ int __init serverworks_setup (struct pci_dev *pdev)
 static int __init agp_find_supported_device(struct pci_dev *dev)
 {
 	struct pci_dev *bridge_dev;
-	agp_bridge.dev = dev;
 
 	/* Everything is on func 1 here so we are hardcoding function one */
 	bridge_dev = pci_find_slot ((unsigned int)dev->bus->number, PCI_DEVFN(0, 1));
@@ -638,9 +617,10 @@ static int __init agp_find_supported_device(struct pci_dev *dev)
 }
 
 
-static int agp_serverworks_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_serverworks_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
 	if (agp_find_supported_device(dev) == 0) {
+		agp_bridge.dev = dev;
 		agp_register_driver(dev);
 		return 0;
 	}
@@ -661,7 +641,7 @@ static struct pci_device_id agp_serverworks_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
 
-static struct pci_driver agp_serverworks_pci_driver = {
+static struct __initdata pci_driver agp_serverworks_pci_driver = {
 	.name		= "agpgart-serverworks",
 	.id_table	= agp_serverworks_pci_table,
 	.probe		= agp_serverworks_probe,

drivers/char/agp/via-agp.c

@@ -94,7 +94,7 @@ static struct gatt_mask via_generic_masks[] =
 	{.mask = 0x00000000, .type = 0}
 };
 
-int __init via_generic_setup (struct pci_dev *pdev)
+static int __init via_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = via_generic_masks;
 	agp_bridge.num_of_masks = 1;
@@ -124,13 +124,64 @@ int __init via_generic_setup (struct pci_dev *pdev)
 	return 0;
 }
 
-struct agp_device_ids via_agp_device_ids[] __initdata =
+
+/*
+ * The KT400 does magick to put the AGP bridge compliant with the same
+ * standards version as the graphics card. If we haven't fallen into
+ * 2.0 compatability mode, we run the normal 3.0 code, and fall back
+ * if something nasty happens.
+ */
+static void __init via_kt400_enable(u32 mode)
+{
+	if ((agp_generic_agp_3_0_enable(mode))==FALSE)
+		/* Something weird happened, fall back to 2.0 */
+		agp_generic_agp_enable(mode);
+}
+
+static int __init via_kt400_setup(struct pci_dev *pdev)
+{
+	u8 reg;
+
+	agp_bridge.masks = via_generic_masks;
+	agp_bridge.num_of_masks = 1;
+	agp_bridge.aperture_sizes = (void *) via_generic_sizes;
+	agp_bridge.size_type = U8_APER_SIZE;
+	agp_bridge.num_aperture_sizes = 7;
+	agp_bridge.dev_private_data = NULL;
+	agp_bridge.needs_scratch_page = FALSE;
+	agp_bridge.configure = via_configure;
+	agp_bridge.fetch_size = via_fetch_size;
+	agp_bridge.cleanup = via_cleanup;
+	agp_bridge.tlb_flush = via_tlbflush;
+	agp_bridge.mask_memory = via_mask_memory;
+	agp_bridge.cache_flush = global_cache_flush;
+	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
+	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
+	agp_bridge.insert_memory = agp_generic_insert_memory;
+	agp_bridge.remove_memory = agp_generic_remove_memory;
+	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge.free_by_type = agp_generic_free_by_type;
+	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
+	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+	agp_bridge.suspend = agp_generic_suspend;
+	agp_bridge.resume = agp_generic_resume;
+	agp_bridge.cant_use_aperture = 0;
+
+	pci_read_config_byte(agp_bridge.dev, VIA_AGPSEL, &reg);
+	if ((reg & (1<<1))==1) {
+		/* AGP 2.0 compatability mode. */
+		agp_bridge.agp_enable = agp_generic_agp_enable;
+
+	} else {
+
+		/* AGP 3.0 mode */
+		agp_bridge.agp_enable = via_kt400_enable;
+	}
+	return 0;
+}
+
+static struct agp_device_ids via_agp_device_ids[] __initdata =
 {
-	{
-		.device_id	= PCI_DEVICE_ID_VIA_8501_0,
-		.chipset	= VIA_MVP4,
-		.chipset_name	= "MVP4",
-	},
 	{
 		.device_id	= PCI_DEVICE_ID_VIA_82C597_0,
 		.chipset	= VIA_VP3,
@@ -141,6 +192,11 @@ struct agp_device_ids via_agp_device_ids[] __initdata =
 		.chipset	= VIA_MVP3,
 		.chipset_name	= "MVP3",
 	},
+	{
+		.device_id	= PCI_DEVICE_ID_VIA_8501_0,
+		.chipset	= VIA_MVP4,
+		.chipset_name	= "MVP4",
+	},
 	{
 		.device_id	= PCI_DEVICE_ID_VIA_82C691,
 		.chipset	= VIA_APOLLO_PRO,
@@ -166,20 +222,22 @@ struct agp_device_ids via_agp_device_ids[] __initdata =
 		.chipset	= VIA_APOLLO_KT133,
 		.chipset_name	= "Apollo Pro KT266",
 	},
+	{
+		.device_id	= PCI_DEVICE_ID_VIA_8653_0,
+		.chipset	= VIA_APOLLO_PRO,
+		.chipset_name	= "Apollo Pro 266T",
+	},
 	{
 		.device_id	= PCI_DEVICE_ID_VIA_8377_0,
 		.chipset	= VIA_APOLLO_KT400,
 		.chipset_name	= "Apollo Pro KT400",
+		.chipset_setup	= via_kt400_setup,
 	},
 	{
-		.device_id	= PCI_DEVICE_ID_VIA_8653_0,
-		.chipset	= VIA_APOLLO_PRO,
-		.chipset_name	= "Apollo Pro266T",
-	},
-	{
+		/* VIA ProSavage PM133 (Apollo Pro133A chipset with S3 Savage4) */
 		.device_id	= PCI_DEVICE_ID_VIA_82C694X_0,
 		.chipset	= VIA_VT8605,
-		.chipset_name	= "PM133"
+		.chipset_name	= "Apollo ProSavage PM133"
 	},
 	{ }, /* dummy final entry, always present */
 };
@@ -220,15 +278,20 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 }
 
 
-static int agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
+static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
 {
-	if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0)
-		return -ENODEV;
+	u8 cap_ptr = 0;
 
-	agp_bridge.dev = dev;
+	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
+	if (cap_ptr == 0)
+		return -ENODEV;
 
 	/* probe for known chipsets */
 	if (agp_lookup_host_bridge (dev) != -ENODEV) {
+		agp_bridge.dev = dev;
+		agp_bridge.capndx = cap_ptr;
+		/* Fill in the mode register */
+		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &agp_bridge.mode);
 		agp_register_driver(dev);
 		return 0;
 	}
@@ -249,7 +312,7 @@ static struct pci_device_id agp_via_pci_table[] __initdata = {
 
 MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
 
-static struct pci_driver agp_via_pci_driver = {
+static struct __initdata pci_driver agp_via_pci_driver = {
 	.name		= "agpgart-via",
 	.id_table	= agp_via_pci_table,
 	.probe		= agp_via_probe,