Merge bk://bk.arm.linux.org.uk

into home.transmeta.com:/home/torvalds/v2.5/linux

Documentation/arm/XScale/IOP310/IQ80310 → Documentation/arm/XScale/IOP3XX/IQ80310

@@ -49,61 +49,14 @@ Preparing the Hardware
 -----------------------------
 
 This document assumes you're using a Rev D or newer board running
-Redboot as the bootloader.
-
-The as-supplied RedBoot image appears to leave the first page of RAM
-in a corrupt state such that certain words in that page are unwritable
-and contain random data.  The value of the data, and the location within
-the first page changes with each boot, but is generally in the range
-0xa0000150 to 0xa0000fff.
-
-You can grab the source from the ECOS CVS or you can get a prebuilt image
-from:
-
-   ftp://source.mvista.com/pub/xscale/iop310/IQ80310/redboot.bin
-
-which is:
-
-    # strings redboot.bin | grep bootstrap
-    RedBoot(tm) bootstrap and debug environment, version UNKNOWN - built 14:58:21, Aug 15 2001
-
-md5sum of this version:
-
-    bcb96edbc6f8e55b16c165930b6e4439  redboot.bin
-
-You have two options to program it:
-
-1. Using the FRU program (see the instructions in the user manual).
-
-2. Using a Linux host, with MTD support built into the host kernel:
-   - ensure that the RedBoot image is not locked (issue the following
-     command under the existing RedBoot image):
-    RedBoot> fis unlock -f 0 -l 0x40000
-   - switch S3-1 and S3-2 on.
-   - reboot the host
-   - login as root
-   - identify the 80310 card:
-    # lspci
-    ...
-    00:0c.1 Memory controller: Intel Corporation 80310 IOP [IO Processor] (rev 01)
-   - in this example, bus 0, slot 0c, function 1.
-   - insert the MTD modules, and the PCI map module:
-    # insmod drivers/mtd/maps/pci.o
-   - locate the MTD device (using the bus, slot, function)
-    # cat /proc/mtd
-    dev:    size   erasesize  name
-    mtd0: 00800000 00020000 "00:0c.1"
-   - in this example, it is mtd device 0.  Yours will be different.
-     Check carefully.
-   - program the flash
-    # cat redboot.bin > /dev/mtdblock0
-   - check the kernel message log for errors (some cat commands don't
-     error on failure)   
-    # dmesg
-   - switch S3-1 and S3-2 off
-   - reboot host
-
-In any case, make sure you do an 'fis init' command once you boot with the new
+Redboot as the bootloader.  Note that the version of RedBoot provided
+with the boards has a major issue and you need to replace it with the
+latest RedBoot. You can grab the source from the ECOS CVS or you can
+get a prebuilt image and burn it in using FRU at:
+
+   ftp://source.mvista.com/pub/xscale/iq80310/redboot.bin
+
+Make sure you do an 'fis init' command once you boot with the new
 RedBoot image.
 
 
@@ -235,7 +188,7 @@ JFFS RedBoot partition mapped into the MTD partition scheme.
 
 You can grab a pre-built JFFS image to use as a root file system at:
 
-   ftp://source.mvista.com/pub/xscale/iop310/IQ80310/jffs.img
+   ftp://source.mvista.com/pub/xscale/iq80310/jffs.img
 
 For detailed info on using MTD and creating a JFFS image go to:
 

Documentation/arm/XScale/IOP3XX/IQ80321

+
+Board Overview
+-----------------------------
+
+The Worcester IQ80321 board is an evaluation platform for Intel's 80321 Xscale
+CPU (sometimes called IOP321 chipset).
+
+The 80321 contains a single PCI hose (called the ATUs), a PCI-to-PCI bridge,
+two DMA channels, I2C, I2O messaging unit, XOR unit for RAID operations,
+a bus performance monitoring unit, and a memory controller with ECC features.
+
+For more information on the board, see http://developer.intel.com/iio
+
+Port Status
+-----------------------------
+
+Supported:
+
+- MTD/JFFS/JFFS2 root
+- NFS root
+- RAMDISK root
+- Serial port (ttyS0)
+- Cache/TLB locking on 80321 CPU
+- Performance monitoring unit on 80321 CPU
+
+TODO:
+
+- DMA engines
+- I2C
+- 80321 Bus Performance Monitor
+- Application Accelerator Unit (XOR engine for RAID)
+- I2O Messaging Unit
+- I2C unit
+- SSP
+
+Building the Kernel
+-----------------------------
+make iq80321_config
+make oldconfig
+make dep
+make zImage
+
+This will build an image setup for BOOTP/NFS root support.  To change this,
+just run make menuconfig and disable nfs root or add a "root=" option.
+
+Preparing the Hardware
+-----------------------------
+
+Make sure you do an 'fis init' command once you boot with the new
+RedBoot image.
+
+Downloading Linux
+-----------------------------
+
+Assuming you have your development system setup to act as a bootp/dhcp
+server and running tftp:
+
+NOTE: The 80321 board uses a different default memory map than the 80310.
+
+   RedBoot> load -r -b 0x01008000 -m y
+
+Once the download is completed:
+
+   RedBoot> go 0x01008000
+
+There is a version of RedBoot floating around that has DHCP support, but
+I've never been able to cleanly transfer a kernel image and have it run.
+
+Root Devices
+-----------------------------
+
+A kernel is not useful without a root filesystem, and you have several
+choices with this board:  NFS root, RAMDISK, or JFFS/JFFS2.  For development
+purposes, it is suggested that you use NFS root for easy access to various
+tools.  Once you're ready to deploy, probably want to utilize JFFS/JFFS2 on
+the flash device.
+
+MTD on the IQ80321
+-----------------------------
+
+Linux on the IQ80321 supports RedBoot FIS paritioning if it is enabled.
+Out of the box, once you've done 'fis init' on RedBoot, you will get
+the following partitioning scheme:
+
+   root@192.168.0.14:~# cat /proc/mtd
+   dev:    size   erasesize  name
+   mtd0: 00040000 00020000 "RedBoot"
+   mtd1: 00040000 00020000 "RedBoot[backup]"
+   mtd2: 0075f000 00020000 "unallocated space"
+   mtd3: 00001000 00020000 "RedBoot config"
+   mtd4: 00020000 00020000 "FIS directory"
+
+To create an FIS directory, you need to use the fis command in RedBoot.
+As an example, you can burn the kernel into the flash once it's downloaded:
+
+   RedBoot> fis create -b 0x01008000 -l 0x8CBAC -r 0x01008000 -f 0x80000 kernel
+   ... Erase from 0x00080000-0x00120000: .....
+   ... Program from 0x01008000-0x01094bac at 0x00080000: .....
+   ... Unlock from 0x007e0000-0x00800000: .
+   ... Erase from 0x007e0000-0x00800000: .
+   ... Program from 0x01fdf000-0x01fff000 at 0x007e0000: .
+   ... Lock from 0x007e0000-0x00800000: .
+
+   RedBoot> fis list
+   Name              FLASH addr  Mem addr    Length      Entry point
+   RedBoot           0x00000000  0x00000000  0x00040000  0x00000000
+   RedBoot[backup]   0x00040000  0x00040000  0x00040000  0x00000000
+   RedBoot config    0x007DF000  0x007DF000  0x00001000  0x00000000
+   FIS directory     0x007E0000  0x007E0000  0x00020000  0x00000000
+   kernel            0x00080000  0x01008000  0x000A0000  0x00000000
+
+This leads to the following Linux MTD setup:
+
+   mtroot@192.168.0.14:~# cat /proc/mtd
+   dev:    size   erasesize  name
+   mtd0: 00040000 00020000 "RedBoot"
+   mtd1: 00040000 00020000 "RedBoot[backup]"
+   mtd2: 000a0000 00020000 "kernel"
+   mtd3: 006bf000 00020000 "unallocated space"
+   mtd4: 00001000 00020000 "RedBoot config"
+   mtd5: 00020000 00020000 "FIS directory"
+
+Note that there is not a 1:1 mapping to the number of RedBoot paritions to
+MTD partitions as unused space also gets allocated into MTD partitions.
+
+As an aside, the -r option when creating the Kernel entry allows you to
+simply do an 'fis load kernel' to copy the image from flash into memory.
+You can then do an 'fis go 0x01008000' to start Linux.
+
+If you choose to use static partitioning instead of the RedBoot partioning:
+
+   /dev/mtd0  0x00000000 - 0x0007ffff: Boot Monitor     (512k)
+   /dev/mtd1  0x00080000 - 0x0011ffff: Kernel Image     (640K)
+   /dev/mtd2  0x00120000 - 0x0071ffff: File System      (6M)
+   /dev/mtd3  0x00720000 - 0x00800000: RedBoot Reserved (896K)
+
+To use a JFFS1/2 root FS, you need to donwload the JFFS image using either
+tftp or ymodem, and then copy it to flash:
+
+   RedBoot> load -r -b 0x01000000 /tftpboot/jffs.img
+   Raw file loaded 0x01000000-0x01600000
+   RedBoot> fis create -b 0x01000000 -l 0x600000 -f 0x120000 jffs
+   ... Erase from 0x00120000-0x00720000: ..................................
+   ... Program from 0x01000000-0x01600000 at 0x00120000: ..................
+   ......................
+   ... Unlock from 0x007e0000-0x00800000: .
+   ... Erase from 0x007e0000-0x00800000: .
+   ... Program from 0x01fdf000-0x01fff000 at 0x007e0000: .
+   ... Lock from 0x007e0000-0x00800000: .
+   RedBoot> fis list
+   Name              FLASH addr  Mem addr    Length      Entry point
+   RedBoot           0x00000000  0x00000000  0x00040000  0x00000000
+   RedBoot[backup]   0x00040000  0x00040000  0x00040000  0x00000000
+   RedBoot config    0x007DF000  0x007DF000  0x00001000  0x00000000
+   FIS directory     0x007E0000  0x007E0000  0x00020000  0x00000000
+   kernel            0x00080000  0x01008000  0x000A0000  0x01008000
+   jffs              0x00120000  0x00120000  0x00600000  0x00000000
+
+This looks like this in Linux:
+
+   root@192.168.0.14:~# cat /proc/mtd
+   dev:    size   erasesize  name
+   mtd0: 00040000 00020000 "RedBoot"
+   mtd1: 00040000 00020000 "RedBoot[backup]"
+   mtd2: 000a0000 00020000 "kernel"
+   mtd3: 00600000 00020000 "jffs"
+   mtd4: 000bf000 00020000 "unallocated space"
+   mtd5: 00001000 00020000 "RedBoot config"
+   mtd6: 00020000 00020000 "FIS directory"
+
+You need to boot the kernel once and watch the boot messages to see how the
+JFFS RedBoot partition mapped into the MTD partition scheme.
+
+You can grab a pre-built JFFS image to use as a root file system at:
+
+   ftp://source.mvista.com/pub/xscale/iq80310/jffs.img
+
+For detailed info on using MTD and creating a JFFS image go to:
+
+   http://www.linux-mtd.infradead.org.
+
+For details on using RedBoot's FIS commands, type 'fis help' or consult
+your RedBoot manual.
+
+BUGS and ISSUES
+-----------------------------
+
+* As shipped from Intel, pre-production boards have two issues:
+
+- The on board ethernet is disabled S8E1-2 is off. You will need to turn it on.
+
+- The PCIXCAPs are configured for a 100Mhz clock, but the clock selected is
+  actually only 66Mhz. This causes the wrong PPL multiplier to be used and the
+  board only runs at 400Mhz instead of 600Mhz. The way to observe this is to
+  use a independent clock to time a "sleep 10" command from the prompt. If it
+  takes 15 seconds instead of 10, you are running at 400Mhz.
+
+- The experimental IOP310 drivers for the AAU, DMA, etc. are not supported yet.
+
+Contributors
+-----------------------------
+The port to the IQ80321 was performed by:
+
+Rory Bolt <rorybolt@pacbell.net> - Initial port, debugging.
+
+This port was based on the IQ80310 port with the following contributors:
+
+Nicolas Pitre <nico@cam.org> - Initial port, cleanup, debugging
+Matt Porter <mporter@mvista.com> - PCI subsystem development, debugging
+Tim Sanders <tsanders@sanders.org> - Initial PCI code
+Deepak Saxena <dsaxena@mvista.com> - Cleanup, debug, cache lock, PMU
+
+The port is currently maintained by Deepak Saxena <dsaxena@mvista.com>
+
+-----------------------------
+Enjoy.

Documentation/arm/XScale/IOP3XX/aau.txt

+Support functions for the Intel 80310 AAU
+===========================================
+
+Dave Jiang <dave.jiang@intel.com>
+Last updated: 09/18/2001
+
+The Intel 80312 companion chip in the 80310 chipset contains an AAU. The
+AAU is capable of processing up to 8 data block sources and perform XOR
+operations on them. This unit is typically used to accelerated XOR
+operations utilized by RAID storage device drivers such as RAID 5. This
+API is designed to provide a set of functions to take adventage of the
+AAU. The AAU can also be used to transfer data blocks and used as a memory
+copier. The AAU transfer the memory faster than the operation performed by
+using CPU copy therefore it is recommended to use the AAU for memory copy.
+
+------------------
+int aau_request(u32 *aau_context, const char *device_id);
+This function allows the user the acquire the control of the the AAU. The
+function will return a context of AAU to the user and allocate
+an interrupt for the AAU. The user must pass the context as a parameter to
+various AAU API calls.
+
+int aau_queue_buffer(u32 aau_context, aau_head_t *listhead);
+This function starts the AAU operation. The user must create a SGL
+header with a SGL attached. The format is presented below. The SGL is
+built from kernel memory.
+
+/* hardware descriptor */
+typedef struct _aau_desc
+{
+    u32 NDA;                    /* next descriptor address [READONLY] */
+    u32 SAR[AAU_SAR_GROUP];     /* src addrs */
+    u32 DAR;                    /* destination addr */
+    u32 BC;                     /* byte count */
+    u32 DC;                     /* descriptor control */
+    u32 SARE[AAU_SAR_GROUP];    /* extended src addrs */
+} aau_desc_t;
+
+/* user SGL format */
+typedef struct _aau_sgl
+{
+    aau_desc_t          aau_desc;  /* AAU HW Desc */
+    u32		        status;    /* status of SGL [READONLY] */
+    struct _aau_sgl	*next;     /* pointer to next SG [READONLY] */
+    void                *dest;     /* destination addr */
+    void                *src[AAU_SAR_GROUP]; 	    /* source addr[4] */
+    void                *ext_src[AAU_SAR_GROUP];    /* ext src addr[4] */
+    u32                 total_src; /* total number of source */
+} aau_sgl_t;
+
+/* header for user SGL */
+typedef struct _aau_head
+{
+    u32		total;      /* total descriptors allocated */
+    u32         status;     /* SGL status */
+    aau_sgl_t   *list;      /* ptr to head of list */
+    aau_callback_t  callback;  /* callback func ptr */
+} aau_head_t;
+
+
+The function will call aau_start() and start the AAU after it queues
+the SGL to the processing queue. When the function will either
+a. Sleep on the wait queue aau->wait_q if no callback has been provided, or
+b. Continue and then call the provided callback function when DMA interrupt
+   has been triggered.
+
+int aau_suspend(u32 aau_context);
+Stops/Suspends the AAU operation
+
+int aau_free(u32 aau_context);
+Frees the ownership of AAU. Called when no longer need AAU service.
+
+aau_sgl_t * aau_get_buffer(u32 aau_context, int num_buf);
+This function obtains an AAU SGL for the user. User must specify the number
+of descriptors to be allocated in the chain that is returned.
+
+void aau_return_buffer(u32 aau_context, aau_sgl_t *list);
+This function returns all SGL back to the API after user is done.
+
+int aau_memcpy(void *dest, void *src, u32 size);
+This function is a short cut for user to do memory copy utilizing the AAU for
+better large block memory copy vs using the CPU. This is similar to using
+typical memcpy() call.
+
+* User is responsible for the source address(es) and the destination address.
+  The source and destination should all be cached memory.
+
+
+
+void aau_test()
+{
+	u32 aau;
+	char dev_id[] = "AAU";
+	int size = 2;
+	int err = 0;
+	aau_head_t *head;
+	aau_sgl_t *list;
+	u32 i;
+	u32 result = 0;
+	void *src, *dest;
+
+	printk("Starting AAU test\n");
+	if((err = aau_request(&aau, dev_id))<0)
+	{
+		printk("test - AAU request failed: %d\n", err);
+		return;
+	}
+	else
+	{
+		printk("test - AAU request successful\n");
+	}
+
+	head = kmalloc(sizeof(aau_head_t), GFP_KERNEL);
+	head->total = size;
+	head->status = 0;
+	head->callback = NULL;
+
+	list = aau_get_buffer(aau, size);
+	if(!list)
+	{
+		printk("Can't get buffers\n");
+		return;
+	}
+	head->list = list;
+
+	src = kmalloc(1024, GFP_KERNEL);
+	dest = kmalloc(1024, GFP_KERNEL);
+
+	while(list)
+	{
+		list->status = 0;
+		list->aau_desc->SAR[0] = (u32)src;
+		list->aau_desc->DAR = (u32)dest;
+		list->aau_desc->BC = 1024;
+
+		/* see iop310-aau.h for more DCR commands */
+		list->aau_desc->DC = AAU_DCR_WRITE | AAU_DCR_BLKCTRL_1_DF;
+		if(!list->next)
+		{
+			list->aau_desc->DC = AAU_DCR_IE;
+			break;
+		}
+		list = list->next;
+	}
+
+	printk("test- Queueing buffer for AAU operation\n");
+	err = aau_queue_buffer(aau, head);
+	if(err >= 0)
+	{
+		printk("AAU Queue Buffer is done...\n");
+	}
+	else
+	{
+		printk("AAU Queue Buffer failed...: %d\n", err);
+	}
+
+
+
+#if 1
+	printk("freeing the AAU\n");
+	aau_return_buffer(aau, head->list);
+	aau_free(aau);
+	kfree(src);
+	kfree(dest);
+	kfree((void *)head);
+#endif
+}
+
+All Disclaimers apply. Use this at your own discretion. Neither Intel nor I
+will be responsible if anything goes wrong. =)
+
+
+TODO
+____
+* Testing
+* Do zero-size AAU transfer/channel at init
+  so all we have to do is chainining
+

Documentation/arm/XScale/IOP3XX/dma.txt

+Support functions forthe Intel 80310 DMA channels
+==================================================
+
+Dave Jiang <dave.jiang@intel.com>
+Last updated: 09/18/2001
+
+The Intel 80310 XScale chipset provides 3 DMA channels via the 80312 I/O
+companion chip. Two of them resides on the primary PCI bus and one on the
+secondary PCI bus.
+
+The DMA API provided is not compatible with the generic interface in the
+ARM tree unfortunately due to how the 80312 DMACs work. Hopefully some time
+in the near future a software interface can be done to bridge the differences.
+The DMA API has been modeled after Nicholas Pitre's SA11x0 DMA API therefore
+they will look somewhat similar.
+
+
+80310 DMA API
+-------------
+
+int dma_request(dmach_t channel, const char *device_id);
+
+This function will attempt to allocate the channel depending on what the
+user requests:
+
+IOP310_DMA_P0: PCI Primary 1
+IOP310_DMA_P1: PCI Primary 2
+IOP310_DMA_S0: PCI Secondary 1
+/*EOF*/
+
+Once the user allocates the DMA channel it is owned until released. Although
+other users can also use the same DMA channel, but no new resources will be
+allocated. The function will return the allocated channel number if successful.
+
+int dma_queue_buffer(dmach_t channel, dma_sghead_t *listhead);
+
+The user will construct a SGL in the form of below:
+/*
+ * Scattered Gather DMA List for user
+ */
+typedef struct _dma_desc
+{
+    u32  NDAR;       /* next descriptor adress [READONLY] */
+    u32  PDAR;       /* PCI address */
+    u32  PUADR;      /* upper PCI address */
+    u32  LADR;       /* local address */
+    u32  BC;         /* byte count */
+    u32  DC;         /* descriptor control */
+} dma_desc_t;
+
+typedef struct _dma_sgl
+{
+    dma_desc_t      dma_desc;     /* DMA descriptor */
+    u32             status;       /* descriptor status [READONLY] */
+    u32	    	    data;	  /* user defined data */
+    struct _dma_sgl *next;	  /* next descriptor [READONLY] */
+} dma_sgl_t;
+
+/* dma sgl head */
+typedef struct _dma_head
+{
+    u32		    total;	/* total elements in SGL */
+    u32		    status;	/* status of sgl */
+    u32		    mode;	/* read or write mode */
+    dma_sgl_t	    *list;	/* pointer to list */
+    dma_callback_t  callback;   /* callback function */
+} dma_head_t;
+
+
+The user shall allocate user SGL elements by calling the function:
+dma_get_buffer(). This function will give the user an SGL element. The user
+is responsible for creating the SGL head however. The user is also
+responsible for allocating the memory for DMA data. The following code segment
+shows how a DMA operation can be performed:
+
+#include <asm/arch/iop310-dma.h>
+
+void dma_test(void)
+{
+	char dev_id[] = "Primary 0";
+	dma_head_t *sgl_head = NULL;
+	dma_sgl_t *sgl = NULL;
+	int err = 0;
+	int channel = -1;
+	u32 *test_ptr = 0;
+	DECLARE_WAIT_QUEUE_HEAD(wait_q);
+
+
+	*(IOP310_ATUCR) = (IOP310_ATUCR_PRIM_OUT_ENAB |
+			IOP310_ATUCR_DIR_ADDR_ENAB);
+
+	channel = dma_request(IOP310_DMA_P0, dev_id);
+
+	sgl_head = (dma_head_t *)kmalloc(sizeof(dma_head_t), GFP_KERNEL);
+	sgl_head->callback = NULL;      /* no callback created */
+	sgl_head->total = 2; /* allocating 2 DMA descriptors */
+	sgl_head->mode = (DMA_MOD_WRITE);
+	sgl_head->status = 0;
+
+	/* now we get the two descriptors */
+	sgl = dma_get_buffer(channel, 2);
+
+    	/* we set the header to point to the list we allocated */
+    	sgl_head->list = sgl;
+
+	/* allocate 1k of DMA data */
+    	sgl->data = (u32)kmalloc(1024, GFP_KERNEL);
+
+    	/* Local address is physical */
+	sgl->dma_desc.LADR = (u32)virt_to_phys(sgl->data);
+
+	/* write to arbitrary location over the PCI bus */
+    	sgl->dma_desc.PDAR = 0x00600000;
+	sgl->dma_desc.PUADR = 0;
+	sgl->dma_desc.BC = 1024;
+
+    	/* set write & invalidate PCI command */
+	sgl->dma_desc.DC = DMA_DCR_PCI_MWI;
+	sgl->status = 0;
+
+    	/* set a pattern */
+    	memset(sgl->data, 0xFF, 1024);
+
+	/* User's responsibility to keep buffers cached coherent */
+	cpu_dcache_clean(sgl->data, sgl->data + 1024);
+
+	sgl = sgl->next;
+
+	sgl->data = (u32)kmalloc(1024, GFP_KERNEL);
+	sgl->dma_desc.LADR = (u32)virt_to_phys(sgl->data);
+	sgl->dma_desc.PDAR = 0x00610000;
+	sgl->dma_desc.PUADR = 0;
+	sgl->dma_desc.BC = 1024;
+
+	/* second descriptor has interrupt flag enabled */
+	sgl->dma_desc.DC = (DMA_DCR_PCI_MWI | DMA_DCR_IE);
+
+	/* must set end of chain flag */
+	sgl->status = DMA_END_CHAIN; /* DO NOT FORGET THIS!!!! */
+
+    	memset(sgl->data, 0x0f, 1024);
+	/* User's responsibility to keep buffers cached coherent */
+	cpu_dcache_clean(sgl->data, sgl->data + 1024);
+
+    	/* queing the buffer, this function will sleep since no callback */
+    	err = dma_queue_buffer(channel, sgl_head);
+
+    	/* now we are woken from DMA complete */
+
+    	/* do data operations here */
+
+    	/* free DMA data if necessary */
+
+	/* return the descriptors */
+	dma_return_buffer(channel, sgl_head->list);
+
+	/* free the DMA */
+	dma_free(channel);
+
+	kfree((void *)sgl_head);
+}
+
+
+dma_sgl_t * dma_get_buffer(dmach_t channel, int buf_num);
+
+This call allocates DMA descriptors for the user.
+
+
+void dma_return_buffer(dmach_t channel, dma_sgl_t *list);
+
+This call returns the allocated descriptors back to the API.
+
+
+int dma_suspend(dmach_t channel);
+
+This call suspends any DMA transfer on the given channel.
+
+
+
+int dma_resume(dmach_t channel);
+
+This call resumes a DMA transfer which would have been stopped through
+dma_suspend().
+
+
+int dma_flush_all(dmach_t channel);
+
+This completely flushes all queued buffers and on-going DMA transfers on a
+given channel. This is called when DMA channel errors have occured.
+
+
+void dma_free(dmach_t channel);
+
+This clears all activities on a given DMA channel and releases it for future
+requests.
+
+
+
+Buffer Allocation
+-----------------
+It is the user's responsibility to allocate, free, and keep track of the
+allocated DMA data memory. Upon calling dma_queue_buffer() the user must
+relinquish the control of the buffers to the kernel and not change the
+state of the buffers that it has passed to the kernel. The user will regain
+the control of the buffers when it has been woken up by the bottom half of
+the DMA interrupt handler. The user can allocate cached buffers or non-cached
+via pci_alloc_consistent(). It is the user's responsibility to ensure that
+the data is cache coherent.
+
+*Reminder*
+The user is responsble to ensure the ATU is setup properly for DMA transfers.
+
+All Disclaimers apply. Use this at your own discretion. Neither Intel nor I
+will be responsible ifanything goes wrong.

Documentation/arm/XScale/IOP3XX/message.txt

+Support functions for the Intel 80310 MU
+===========================================
+
+Dave Jiang <dave.jiang@intel.com>
+Last updated: 10/11/2001
+
+The messaging unit of the IOP310 contains 4 components and is utilized for
+passing messages between the PCI agents on the primary bus and the Intel(R)
+80200 CPU. The four components are:
+Messaging Component
+Doorbell Component
+Circular Queues Component
+Index Registers Component
+
+Messaging Component:
+Contains 4 32bit registers, 2 in and 2 out. Writing to the registers assert
+interrupt on the PCI bus or to the 80200 depend on incoming or outgoing.
+
+int mu_msg_request(u32 *mu_context);
+Request the usage of Messaging Component. mu_context is written back by the
+API. The MU context is passed to other Messaging calls as a parameter.
+
+int mu_msg_set_callback(u32 mu_context, u8 reg, mu_msg_cb_t func);
+Setup the callback function for incoming messages. Callback can be setup for
+outbound 0, 1, or both outbound registers.
+
+int mu_msg_post(u32 mu_context, u32 val, u8 reg);
+Posting a message in the val parameter. The reg parameter denotes whether
+to use register 0, 1.
+
+int mu_msg_free(u32 mu_context, u8 mode);
+Free the usage of messaging component. mode can be specified soft or hard. In
+hardmode all resources are unallocated.
+
+Doorbell Component:
+The doorbell registers contains 1 inbound and 1 outbound. Depending on the bits
+being set different interrupts are asserted.
+
+int mu_db_request(u32 *mu_context);
+Request the usage of the doorbell register.
+
+int mu_db_set_callback(u32 mu_context, mu_db_cb_t func);
+Setting up the inbound callback.
+
+void mu_db_ring(u32 mu_context, u32 mask);
+Write to the outbound db register with mask.
+
+int mu_db_free(u32 mu_context);
+Free the usage of doorbell component.
+
+Circular Queues Component:
+The circular queue component has 4 circular queues. Inbound post, inbound free,
+outbound post, outbound free. These queues are used to pass messages.
+
+int mu_cq_request(u32 *mu_context, u32 q_size);
+Request the usage of the queue. See code comment header for q_size. It tells
+the API how big of queues to setup.
+
+int mu_cq_inbound_init(u32 mu_context, mfa_list_t *list, u32 size,
+                       mu_cq_cb_t func);
+Init inbound queues. The user must provide a list of free message frames to
+be put in inbound free queue and the callback function to handle the inbound
+messages.
+
+int mu_cq_enable(u32 mu_context);
+Enables the circular queues mechanism. Called once all the setup functions
+are called.
+
+u32 mu_cq_get_frame(u32 mu_context);
+Obtain the address of an outbound free frame for the user.
+
+int mu_cq_post_frame(u32 mu_context, u32 mfa);
+The user can post the frame once getting the frame and put information in the
+frame.
+
+int mu_cq_free(u32 mu_context);
+Free the usage of circular queues mechanism.
+
+Index Registers Component:
+The index register provides the mechanism to receive inbound messages.
+
+int mu_ir_request(u32 *mu_context);
+Request of Index Register component usage.
+
+int mu_ir_set_callback(u32 mu_context, mu_ir_cb_t callback);
+Setting up callback for inbound messages. The callback will receive the
+value of the register that IAR offsets to.
+
+int mu_ir_free(u32 mu_context);
+Free the usage of Index Registers component.
+
+void mu_set_irq_threshold(u32 mu_context, int thresh);
+Setup the IRQ threshold before relinquish processing in IRQ space. Default
+is set at 10 loops.
+
+
+*NOTE: Example of host driver that utilize the MU can be found in the Linux I2O
+driver. Specifically i2o_pci and some functions of i2o_core. The I2O driver
+only utilize the circular queues mechanism. The other 3 components are simple
+enough that they can be easily setup. The MU API provides no flow control for
+the messaging mechanism. Flow control of the messaging needs to be established
+by a higher layer of software on the IOP or the host driver.
+
+All Disclaimers apply. Use this at your own discretion. Neither Intel nor I
+will be responsible if anything goes wrong. =)
+
+
+TODO
+____
+

Documentation/arm/XScale/IOP3XX/pmon.txt

+
+Intel's XScale Microarchitecture 80312 companion processor provides a
+Performance Monitoring Unit (PMON) that can be utilized to provide
+information that can be useful for fine tuning of code.  This text
+file describes the API that's been developed for use by Linux kernel
+programmers.  Note that to get the most usage out of the PMON,
+I highly reccomend getting the XScale reference manual from Intel[1]
+and looking at chapter 12.
+
+To use the PMON, you must #include <asm-arm/arch-iop310/pmon.h> in your
+source file.
+
+Since there's only one PMON, only one user can currently use the PMON
+at a given time.  To claim the PMON for usage, call iop310_pmon_claim() which
+returns an identifier.  When you are done using the PMON, call
+iop310_pmon_release() with the id you were given earlier.
+
+The PMON consists of 14 registers that can be used for performance measurements.
+By combining different statistics, you can derive complex performance metrics.
+
+To start the PMON, just call iop310_pmon_start(mode).  Mode tells the PMON what
+statistics to capture and can each be one of:
+
+    IOP310_PMU_MODE0
+    Performance Monitoring Disabled
+
+    IOP310_PMU_MODE1
+    Primary PCI bus and internal agents (bridge, dma Ch0, dam Ch1, patu)
+
+    IOP310_PMU_MODE2
+    Secondary PCI bus and internal agents (bridge, dma Ch0, dam Ch1, patu)
+
+    IOP310_PMU_MODE3
+    Secondary PCI bus and internal agents (external masters 0..2 and Intel
+    80312 I/O companion chip)
+
+    IOP310_PMU_MODE4
+    Secondary PCI bus and internal agents (external masters 3..5 and Intel
+    80312 I/O companion chip)
+
+    IOP310_PMU_MODE5
+    Intel 80312 I/O companion chip internal bus, DMA Channels and Application
+    Accelerator
+
+    IOP310_PMU_MODE6
+    Intel 80312 I/O companion chip internal bus, PATU, SATU and Intel 80200
+    processor
+
+    IOP310_PMU_MODE7
+    Intel 80312 I/O companion chip internal bus, Primary PCI bus, Secondary
+    PCI bus and Secondary PCI agents (external masters 0..5 & Intel 80312 I/O
+    companion chip)
+
+To get the results back, call iop310_pmon_stop(&results) where results is
+defined as follows:
+
+typedef struct _iop310_pmon_result
+{
+	u32 timestamp;			/* Global Time Stamp Register */
+	u32 timestamp_overflow;		/* Time Stamp overflow count */
+	u32 event_count[14];		/* Programmable Event Counter
+					   Registers 1-14 */
+	u32 event_overflow[14];		/* Overflow counter for PECR1-14 */
+} iop310_pmon_res_t;
+
+
+--
+This code is still under development, so please feel free to send patches,
+questions, comments, etc to me.
+
+Deepak Saxena <dsaxena@mvista.com>

Documentation/arm/XScale/cache-lock.txt

+
+Intel's XScale Microarchitecture provides support for locking of data
+and instructions into the appropriate caches. This  file provides
+an overview of the API that has been developed to take advantage of this
+feature from kernel space. Note that there is NO support for user space
+cache locking.
+
+For example usage of this code, grab:
+
+	ftp://source.mvista.com/pub/xscale/cache-test.c
+
+If you have any questions, comments, patches, etc, please contact me.
+
+Deepak Saxena <dsaxena@mvista.com>
+
+API DESCRIPTION
+
+
+I. Header File
+
+   #include <asm/xscale-lock.h>
+
+II. Cache Capability Discovery
+
+   SYNOPSIS
+
+   int cache_query(u8 cache_type,
+                           struct cache_capabilities *pcache);
+
+   struct cache_capabilities
+   {
+      u32   flags;      /* Flags defining capabilities  */
+      u32   cache_size; /* Cache size in K (1024 bytes) */
+      u32   max_lock;   /* Maximum lockable region in K */
+   }
+
+   /*
+    * Flags
+    */
+
+   /*
+    * Bit 0: Cache lockability
+    * Bits 1-31: Reserved for future use
+    */
+   #define CACHE_LOCKABLE    0x00000001   /* Cache can be locked */
+
+   /*
+    * Cache Types
+    */
+   #define ICACHE            0x00
+   #define DCACHE            0x01
+
+   DESCRIPTION
+
+   This function fills out the pcache capability identifier for the
+   requested cache. cache_type is either DCACHE or ICACHE. This
+   function is not very useful at the moment as all XScale CPU's
+   have the same size Cache, but is is provided for future XScale
+   based processors that may have larger cache sizes.
+
+   RETURN VALUE
+
+   This function returns 0 if no error occurs, otherwise it returns
+   a negative, errno compatible value.
+
+      -EIO   Unknown hardware error
+
+III. Cache Locking
+
+   SYNOPSIS
+
+   int cache_lock(void *addr, u32 len, u8 cache_type, const char *desc);
+
+   DESCRIPTION
+
+   This function locks a physically contigous portion of memory starting
+   at the virtual address pointed to by addr into the cache referenced
+   by cache_type.
+
+   The address of the data/instruction that is to be locked must be
+   aligned on a cache line boundary (L1_CACHE_ALIGNEMENT).
+
+   The desc parameter is an optional (pass NULL if not used) human readable
+   descriptor of the locked memory region that is used by the cache
+   management code to build the /proc/cache_locks table.
+
+   Note that this function does not check whether the address is valid
+   or not before locking it into the cache.  That duty is up to the
+   caller.  Also, it does not check for duplicate or overlaping
+   entries.
+
+   RETURN VALUE
+
+   If the function is successful in locking the entry into cache, a
+   zero is returned.
+
+   If an error occurs, an appropriate error value is returned.
+
+      -EINVAL   The memory address provided was not cache line aligned
+      -ENOMEM   Could not allocate memory to complete operation
+      -ENOSPC   Not enough space left on cache to lock in requested region
+      -EIO      Unknown error
+
+III. Cache Unlocking
+
+   SYNOPSIS
+
+   int cache_unlock(void *addr)
+
+   DESCRIPTION
+
+   This function unlocks a portion of memory that was previously locked
+   into either the I or D cache.
+
+   RETURN VALUE
+
+   If the entry is cleanly unlocked from the cache, a 0 is returned.
+   In the case of an error, an appropriate error is returned.
+
+      -ENOENT    No entry with given address associated with this cache
+      -EIO       Unknown error
+
+

Documentation/arm/XScale/pmu.txt

+
+Intel's XScale Microarchitecture processors provide a Performance
+Monitoring Unit (PMU) that can be utilized to provide information
+that can be useful for fine tuning of code.  This text file describes
+the API that's been developed for use by Linux kernel programmers.
+When I have some extra time on my hand, I will extend the code to
+provide support for user mode performance monitoring (which is
+probably much more useful).  Note that to get the most usage out
+of the PMU, I highly reccomend getting the XScale reference manual
+from Intel and looking at chapter 12.
+
+To use the PMU, you must #include <asm/xscale-pmu.h> in your source file.
+
+Since there's only one PMU, only one user can currently use the PMU
+at a given time.  To claim the PMU for usage, call pmu_claim() which
+returns an identifier.  When you are done using the PMU, call
+pmu_release() with the identifier that you were given by pmu_claim.
+
+In addition, the PMU can only be used on XScale based systems that
+provide an external timer.  Systems that the PMU is currently supported
+on are:
+
+	- Cyclone IQ80310
+
+Before delving into how to use the PMU code, let's do a quick overview
+of the PMU itself.  The PMU consists of three registers that can be
+used for performance measurements.  The first is the CCNT register with
+provides the number of clock cycles elapsed since the PMU was started.
+The next two register, PMN0 and PMN1, are eace user programmable to
+provide 1 of 20 different performance statistics.  By combining different
+statistics, you can derive complex performance metrics.
+
+To start the PMU, just call pmu_start(pm0, pmn1).  pmn0 and pmn1 tell
+the PMU what statistics to capture and can each be one of:
+
+EVT_ICACHE_MISS
+	Instruction fetches requiring access to external memory
+
+EVT_ICACHE_NO_DELIVER
+	Instruction cache could not deliver an instruction.  Either an
+	ICACHE miss or an instruction TLB miss.
+
+EVT_ICACHE_DATA_STALL
+	Stall in execution due to a data dependency. This counter is
+	incremented each cycle in which the condition is present.
+
+EVT_ITLB_MISS
+	Instruction TLB miss
+
+EVT_DTLB_MISS
+	Data TLB miss
+
+EVT_BRANCH
+	A branch instruction was executed and it may or may not have
+	changed program flow
+
+EVT_BRANCH_MISS
+	A branch (B or BL instructions only) was mispredicted
+
+EVT_INSTRUCTION
+	An instruction was executed
+
+EVT_DCACHE_FULL_STALL
+	Stall because data cache buffers are full.  Incremented on every
+	cycle in which condition is present.
+
+EVT_DCACHE_FULL_STALL_CONTIG
+	Stall because data cache buffers are full.  Incremented on every
+	cycle in which condition is contigous.
+
+EVT_DCACHE_ACCESS
+	Data cache access (data fetch)
+
+EVT_DCACHE_MISS
+	Data cache miss
+
+EVT_DCACHE_WRITE_BACK
+	Data cache write back.  This counter is incremented for every
+	1/2 line (four words) that are written back.
+
+EVT_PC_CHANGED
+	Software changed the PC.  This is incremented only when the
+	software changes the PC and there is no mode change.  For example,
+	a MOV instruction that targets the PC would increment the counter.
+	An SWI would not as it triggers a mode change.
+
+EVT_BCU_REQUEST
+	The Bus Control Unit(BCU) received a request from the core
+
+EVT_BCU_FULL
+	The BCU request queue if full.  A high value for this event means
+	that the BCU is often waiting for to complete on the external bus.
+
+EVT_BCU_DRAIN
+	The BCU queues were drained due to either a Drain Write Buffer
+	command or an I/O transaction for a page that was marked as
+	uncacheable and unbufferable.
+
+EVT_BCU_ECC_NO_ELOG
+	The BCU detected an ECC error on the memory bus but noe ELOG
+	register was available to to log the errors.
+
+EVT_BCU_1_BIT_ERR
+	The BCU detected a 1-bit error while reading from the bus.
+
+EVT_RMW
+	An RMW cycle occurred due to narrow write on ECC protected memory.
+
+To get the results back, call pmu_stop(&results) where results is defined
+as a struct pmu_results:
+
+	struct pmu_results
+	{
+		u32     ccnt;	/* Clock Counter Register */
+		u32	ccnt_of; /
+		u32     pmn0;	/* Performance Counter Register 0 */
+		u32	pmn0_of;
+		u32     pmn1;	/* Performance Counter Register 1 */
+		u32	pmn1_of;
+	};
+
+Pretty simple huh?  Following are some examples of how to get some commonly
+wanted numbers out of the PMU data.  Note that since you will be dividing
+things, this isn't super useful from the kernel and you need to printk the
+data out to syslog.  See [1] for more examples.
+
+Instruction Cache Efficiency
+
+	pmu_start(EVT_INSTRUCTION, EVT_ICACHE_MISS);
+	...
+	pmu_stop(&results);
+
+	icache_miss_rage = results.pmn1 / results.pmn0;
+	cycles_per_instruction = results.ccnt / results.pmn0;
+
+Data Cache Efficiency
+
+	pmu_start(EVT_DCACHE_ACCESS, EVT_DCACHE_MISS);
+	...
+	pmu_stop(&results);
+
+	dcache_miss_rage = results.pmn1 / results.pmn0;
+
+Instruction Fetch Latency
+
+	pmu_start(EVT_ICACHE_NO_DELIVER, EVT_ICACHE_MISS);
+	...
+	pmu_stop(&results);
+
+	average_stall_waiting_for_instruction_fetch =
+		results.pmn0 / results.pmn1;
+
+	percent_stall_cycles_due_to_instruction_fetch =
+		results.pmn0 / results.ccnt;
+
+
+ToDo:
+
+- Add support for usermode PMU usage.  This might require hooking into
+  the scheduler so that we pause the PMU when the task that requested
+  statistics is scheduled out.
+
+--
+This code is still under development, so please feel free to send patches,
+questions, comments, etc to me.
+
+Deepak Saxena <dsaxena@mvista.com>
+

Documentation/arm/XScale/tlb-lock.txt

+
+Intel's XScale Microarchitecture provides support for locking of TLB
+entries in both the instruction and data TLBs.  This  file provides
+an overview of the API that has been developed to take advantage of this
+feature from kernel space. Note that there is NO support for user space.
+
+In general, this feature should be used in conjunction with locking
+data or instructions into the appropriate caches.  See the file
+cache-lock.txt in this directory.
+
+If you have any questions, comments, patches, etc, please contact me.
+
+Deepak Saxena <dsaxena@mvista.com>
+
+
+API DESCRIPTION
+
+I. Header file
+
+   #include <asm/xscale-lock.h>
+
+II. Locking an entry into the TLB
+
+    SYNOPSIS
+
+    xscale_tlb_lock(u8 tlb_type, u32 addr);
+
+    /*
+     * TLB types
+     */
+    #define ITLB	0x0
+    #define DTLB	0x1
+
+    DESCRIPTION
+
+    This function locks the virtual to physical mapping for virtual
+    address addr into the requested TLB.
+
+    RETURN VALUE
+
+    If the entry is properly locked into the TLB, a 0 is returned.
+    In case of an error, an appropriate error is returned.
+
+       -ENOSPC No more entries left in the TLB
+       -EIO    Unknown error
+
+III. Unlocking an entry from a TLB
+
+     SYNOPSIS
+
+     xscale_tlb_unlock(u8 tlb_type, u32 addr);
+
+     DESCRIPTION
+
+     This function unlocks the entry for virtual address addr from the
+     specified cache.
+
+     RETURN VALUE
+
+     If the TLB entry is properly unlocked, a 0 is returned.
+     In case of an error, an appropriate error is returned.
+
+        -ENOENT  No entry for given address in specified TLB
+

arch/arm/common/sa1111.c

@@ -418,6 +418,7 @@ static void sa1111_wake(struct sa1111 *sachip)
 
 	spin_lock_irqsave(&sachip->lock, flags);
 
+#if CONFIG_ARCH_SA1100
 	/*
 	 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
 	 * (SA-1110 Developer's Manual, section 9.1.2.1)
@@ -425,6 +426,11 @@ static void sa1111_wake(struct sa1111 *sachip)
 	GAFR |= GPIO_32_768kHz;
 	GPDR |= GPIO_32_768kHz;
 	TUCR = TUCR_3_6864MHz;
+#elif CONFIG_ARCH_PXA
+	pxa_gpio_mode(GPIO11_3_6MHz_MD);
+#else
+#error missing clock setup
+#endif
 
 	/*
 	 * Turn VCO on, and disable PLL Bypass.
@@ -461,6 +467,8 @@ static void sa1111_wake(struct sa1111 *sachip)
 	spin_unlock_irqrestore(&sachip->lock, flags);
 }
 
+#ifdef CONFIG_ARCH_SA1100
+
 /*
  * Configure the SA1111 shared memory controller.
  */
@@ -476,6 +484,8 @@ sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
 	sa1111_writel(smcr, sachip->base + SA1111_SMCR);
 }
 
+#endif
+
 static void
 sa1111_init_one_child(struct sa1111 *sachip, struct sa1111_dev *sadev, unsigned int offset)
 {
@@ -569,6 +579,7 @@ __sa1111_probe(struct device *me, unsigned long phys_addr, int irq)
 	 */
 	sa1111_wake(sachip);
 
+#ifdef CONFIG_ARCH_SA1100
 	/*
 	 * The SDRAM configuration of the SA1110 and the SA1111 must
 	 * match.  This is very important to ensure that SA1111 accesses
@@ -592,6 +603,7 @@ __sa1111_probe(struct device *me, unsigned long phys_addr, int irq)
 	 * Enable the SA1110 memory bus request and grant signals.
 	 */
 	sa1110_mb_enable();
+#endif
 
 	/*
 	 * The interrupt controller must be initialised before any

arch/arm/kernel/head.S

@@ -37,7 +37,7 @@
 	.globl	swapper_pg_dir
 	.equ	swapper_pg_dir, TEXTADDR - 0x4000
 
-	.macro	pgtbl, reg, rambase
+	.macro	pgtbl, reg
 	adr	\reg, stext
 	sub	\reg, \reg, #0x4000
 	.endm
@@ -47,7 +47,7 @@
  * can convert the page table base address to the base address of the section
  * containing both.
  */
-	.macro	krnladr, rd, pgtable, rambase
+	.macro	krnladr, rd, pgtable
 	bic	\rd, \pgtable, #0x000ff000
 	.endm
 
@@ -164,7 +164,7 @@ __mmap_switched:
  * r8 = page table flags
  */
 __create_page_tables:
-	pgtbl	r4, r5				@ page table address
+	pgtbl	r4				@ page table address
 
 	/*
 	 * Clear the 16K level 1 swapper page table
@@ -184,7 +184,7 @@ __create_page_tables:
 	 * cater for the MMU enable.  This identity mapping
 	 * will be removed by paging_init()
 	 */
-	krnladr	r2, r4, r5			@ start of kernel
+	krnladr	r2, r4				@ start of kernel
 	add	r3, r8, r2			@ flags + kernel base
 	str	r3, [r4, r2, lsr #18]		@ identity mapping
 

arch/arm/mach-pxa/Makefile

@@ -4,18 +4,17 @@
 
 # Common support (must be linked before board specific support)
 obj-y += generic.o irq.o dma.o
-obj-$(CONFIG_SA1111) += sa1111.o
 
 # Specific board support
 obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
 obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
 
 # Support for blinky lights
-leds-y := leds.o
-leds-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
-leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
+led-y := leds.o
+led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
+led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
 
-obj-$(CONFIG_LEDS) += $(leds-y)
+obj-$(CONFIG_LEDS) += $(led-y)
 
 # Misc features
 obj-$(CONFIG_PM) += pm.o sleep.o

arch/arm/mach-pxa/generic.c

@@ -38,7 +38,7 @@
 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
 
 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
-static unsigned char M_clk_mult[4] = { 0, 1, 2, 0 };
+static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
 
 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
 /* Note: we store the value N * 2 here. */
@@ -47,11 +47,12 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
 /* Crystal clock */
 #define BASE_CLK	3686400
 
-
 /*
- * Display what we were booted with.
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
  */
-static int __init pxa_display_clocks(void)
+unsigned int get_clk_frequency_khz(int info)
 {
 	unsigned long cccr, turbo;
 	unsigned int l, L, m, M, n2, N;
@@ -67,20 +68,24 @@ static int __init pxa_display_clocks(void)
 	M = m * L;
 	N = n2 * M / 2;
 
-	L += 5000;
-	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
-		L / 1000000, (L % 1000000) / 10000, l );
-	M += 5000;
-	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
-		M / 1000000, (M % 1000000) / 10000, m );
-	N += 5000;
-	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
-		N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
-		(turbo & 1) ? "" : "in" );
-
-	return 0;
+	if(info)
+	{
+		L += 5000;
+		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l );
+		M += 5000;
+		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m );
+		N += 5000;
+		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
+			(turbo & 1) ? "" : "in" );
+	}
+
+	return (turbo & 1) ? (N/1000) : (M/1000);
 }
 
+EXPORT_SYMBOL(get_clk_frequency_khz);
 
 /*
  * Return the current lclk requency in units of 10kHz
@@ -132,5 +137,5 @@ static struct map_desc standard_io_desc[] __initdata = {
 void __init pxa_map_io(void)
 {
 	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-	pxa_display_clocks();
+	get_clk_frequency_khz(1);
 }

arch/arm/mach-pxa/irq.c

@@ -241,10 +241,4 @@ void __init pxa_init_irq(void)
 	/* Install handler for GPIO 2-80 edge detect interrupts */
 	set_irq_chip(IRQ_GPIO_2_80, &pxa_internal_chip);
 	set_irq_chained_handler(IRQ_GPIO_2_80, pxa_gpio_demux_handler);
-
-	/*
-	 * We generally don't want the LCD IRQ being
-	 * enabled as soon as we request it.
-	 */
-	set_irq_flags(IRQ_LCD, IRQF_VALID | IRQF_NOAUTOEN);
 }

arch/arm/mach-pxa/leds.c

@@ -27,4 +27,4 @@ pxa_leds_init(void)
 	return 0;
 }
 
-__initcall(pxa_leds_init);
+core_initcall(pxa_leds_init);

arch/arm/mach-pxa/lubbock.c

@@ -13,6 +13,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/device.h>
 #include <linux/major.h>
 #include <linux/fs.h>
 #include <linux/interrupt.h>
@@ -31,7 +32,6 @@
 #include <asm/hardware/sa1111.h>
 
 #include "generic.h"
-#include "sa1111.h"
 
 static void lubbock_ack_irq(unsigned int irq)
 {
@@ -106,24 +106,16 @@ static void __init lubbock_init_irq(void)
 
 static int __init lubbock_init(void)
 {
-	int ret;
-
-	ret = sa1111_probe(LUBBOCK_SA1111_BASE);
-	if (ret)
-		return ret;
-	sa1111_wake();
-	sa1111_init_irq(LUBBOCK_SA1111_IRQ);
-	return 0;
+	return sa1111_init(0x10000000, LUBBOCK_SA1111_IRQ);
 }
 
-__initcall(lubbock_init);
+subsys_initcall(lubbock_init);
 
 static struct map_desc lubbock_io_desc[] __initdata = {
  /* virtual     physical    length      type */
   { 0xf0000000, 0x08000000, 0x00100000, MT_DEVICE }, /* CPLD */
   { 0xf1000000, 0x0c000000, 0x00100000, MT_DEVICE }, /* LAN91C96 IO */
   { 0xf1100000, 0x0e000000, 0x00100000, MT_DEVICE }, /* LAN91C96 Attr */
-  { 0xf4000000, 0x10000000, 0x00400000, MT_DEVICE }  /* SA1111 */
 };
 
 static void __init lubbock_map_io(void)

drivers/mtd/maps/dc21285.c

@@ -104,11 +104,13 @@ struct map_info dc21285_map = {
 	.copy_to	= dc21285_copy_to
 };
 
-
 /* Partition stuff */
 static struct mtd_partition *dc21285_parts;
 		      
 extern int parse_redboot_partitions(struct mtd_info *, struct mtd_partition **);
+extern int parse_cmdline_partitions(struct mtd_info *master,
+				    struct mtd_partition **pparts,
+				    const char *mtd_id);
 
 int __init init_dc21285(void)
 {
@@ -140,18 +142,34 @@ int __init init_dc21285(void)
 	mymtd = do_map_probe("cfi_probe", &dc21285_map);
 	if (mymtd) {
 		int nrparts = 0;
+		const char *part_type = NULL;
 
 		mymtd->module = THIS_MODULE;
 			
 		/* partition fixup */
-
+		do {
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+			nrparts = parse_cmdline_partitions(mymtd, &dc21285_parts, "dc21285");
+			if (nrparts > 0) {
+				part_type = "command line";
+				break;
+			}
+#endif
 #ifdef CONFIG_MTD_REDBOOT_PARTS
-		nrparts = parse_redboot_partitions(mymtd, &dc21285_parts);
+			nrparts = parse_redboot_partitions(mymtd, &dc21285_parts);
+			if (nrparts > 0) {
+				part_type = "RedBoot";
+				break;
+			}
 #endif
+		} while (0);
+
 		if (nrparts > 0) {
 			add_mtd_partitions(mymtd, dc21285_parts, nrparts);
+			printk(KERN_NOTICE "DC21285 using %s partition "
+			       "definition\n", part_type);
 		} else if (nrparts == 0) {
-			printk(KERN_NOTICE "RedBoot partition table failed\n");
+			printk(KERN_NOTICE "DC21285 partition table failed\n");
 			add_mtd_device(mymtd);
 		}
 

include/asm-arm/arch-pxa/bitfield.h

+/*
+ *	FILE    	bitfield.h
+ *
+ *	Version 	1.1
+ *	Author  	Copyright (c) Marc A. Viredaz, 1998
+ *	        	DEC Western Research Laboratory, Palo Alto, CA
+ *	Date    	April 1998 (April 1997)
+ *	System  	Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose 	Definition of macros to operate on bit fields.
+ */
+
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size      	Size of the bit field, in number of bits.
+ *    Shft      	Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld       	Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize     	Size of the bit field, in number of bits.
+ *    FShft     	Shift value of the bit field with respect to bit 0.
+ *    FMsk      	Mask for the bit field.
+ *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
+ *    F1stBit   	First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value     	Bit-field value.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt    	Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+                	(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data      	Data containing the bit-field to be extracted.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr     	Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+                	((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */

include/asm-arm/arch-pxa/hardware.h

@@ -103,6 +103,5 @@ extern unsigned int get_lclk_frequency_10khz(void);
 
 #include "lubbock.h"
 #include "idp.h"
-#include "cerf.h"
 
 #endif  /* _ASM_ARCH_HARDWARE_H */

include/asm-arm/arch-pxa/irqs.h

@@ -44,78 +44,86 @@
 			((i) - PXA_IRQ(32) + 2)
 #define IRQ_TO_GPIO(i)	((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) : IRQ_GPIO(0)))
 
-#define	NR_IRQS		(IRQ_GPIO(80) + 1)
-
-#if defined(CONFIG_SA1111)
-
-#define IRQ_SA1111_START	(IRQ_GPIO(80) + 1)
-#define SA1111_IRQ(x)		(IRQ_SA1111_START + (x))
-
-#define IRQ_GPAIN0		SA1111_IRQ(0)
-#define IRQ_GPAIN1		SA1111_IRQ(1)
-#define IRQ_GPAIN2		SA1111_IRQ(2)
-#define IRQ_GPAIN3		SA1111_IRQ(3)
-#define IRQ_GPBIN0		SA1111_IRQ(4)
-#define IRQ_GPBIN1		SA1111_IRQ(5)
-#define IRQ_GPBIN2		SA1111_IRQ(6)
-#define IRQ_GPBIN3		SA1111_IRQ(7)
-#define IRQ_GPBIN4		SA1111_IRQ(8)
-#define IRQ_GPBIN5		SA1111_IRQ(9)
-#define IRQ_GPCIN0		SA1111_IRQ(10)
-#define IRQ_GPCIN1		SA1111_IRQ(11)
-#define IRQ_GPCIN2		SA1111_IRQ(12)
-#define IRQ_GPCIN3		SA1111_IRQ(13)
-#define IRQ_GPCIN4		SA1111_IRQ(14)
-#define IRQ_GPCIN5		SA1111_IRQ(15)
-#define IRQ_GPCIN6		SA1111_IRQ(16)
-#define IRQ_GPCIN7		SA1111_IRQ(17)
-#define IRQ_MSTXINT		SA1111_IRQ(18)
-#define IRQ_MSRXINT		SA1111_IRQ(19)
-#define IRQ_MSSTOPERRINT	SA1111_IRQ(20)
-#define IRQ_TPTXINT		SA1111_IRQ(21)
-#define IRQ_TPRXINT		SA1111_IRQ(22)
-#define IRQ_TPSTOPERRINT	SA1111_IRQ(23)
-#define SSPXMTINT	SA1111_IRQ(24)
-#define SSPRCVINT	SA1111_IRQ(25)
-#define SSPROR		SA1111_IRQ(26)
-#define AUDXMTDMADONEA	SA1111_IRQ(32)
-#define AUDRCVDMADONEA	SA1111_IRQ(33)
-#define AUDXMTDMADONEB	SA1111_IRQ(34)
-#define AUDRCVDMADONEB	SA1111_IRQ(35)
-#define AUDTFSR		SA1111_IRQ(36)
-#define AUDRFSR		SA1111_IRQ(37)
-#define AUDTUR		SA1111_IRQ(38)
-#define AUDROR		SA1111_IRQ(39)
-#define AUDDTS		SA1111_IRQ(40)
-#define AUDRDD		SA1111_IRQ(41)
-#define AUDSTO		SA1111_IRQ(42)
-#define USBPWR		SA1111_IRQ(43)
-#define NIRQHCIM	SA1111_IRQ(44)
-#define HCIBUFFACC	SA1111_IRQ(45)
-#define HCIRMTWKP	SA1111_IRQ(46)
-#define NHCIMFCIR	SA1111_IRQ(47)
-#define PORT_RESUME	SA1111_IRQ(48)
-#define S0_READY_NINT	SA1111_IRQ(49)
-#define S1_READY_NINT	SA1111_IRQ(50)
-#define S0_CD_VALID	SA1111_IRQ(51)
-#define S1_CD_VALID	SA1111_IRQ(52)
-#define S0_BVD1_STSCHG	SA1111_IRQ(53)
-#define S1_BVD1_STSCHG	SA1111_IRQ(54)
-
-#define SA1111_IRQ_MAX	SA1111_IRQ(54)
-
-#undef NR_IRQS
-#define NR_IRQS		(SA1111_IRQ_MAX + 1)
-
-#endif	// defined(CONFIG_SA1111)
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.
+ */
+#define IRQ_BOARD_START		(IRQ_GPIO(80) + 1)
+#define IRQ_BOARD_END		(IRQ_BOARD_START + 16)
+
+#define IRQ_SA1111_START	(IRQ_BOARD_END)
+#define IRQ_GPAIN0		(IRQ_BOARD_END + 0)
+#define IRQ_GPAIN1		(IRQ_BOARD_END + 1)
+#define IRQ_GPAIN2		(IRQ_BOARD_END + 2)
+#define IRQ_GPAIN3		(IRQ_BOARD_END + 3)
+#define IRQ_GPBIN0		(IRQ_BOARD_END + 4)
+#define IRQ_GPBIN1		(IRQ_BOARD_END + 5)
+#define IRQ_GPBIN2		(IRQ_BOARD_END + 6)
+#define IRQ_GPBIN3		(IRQ_BOARD_END + 7)
+#define IRQ_GPBIN4		(IRQ_BOARD_END + 8)
+#define IRQ_GPBIN5		(IRQ_BOARD_END + 9)
+#define IRQ_GPCIN0		(IRQ_BOARD_END + 10)
+#define IRQ_GPCIN1		(IRQ_BOARD_END + 11)
+#define IRQ_GPCIN2		(IRQ_BOARD_END + 12)
+#define IRQ_GPCIN3		(IRQ_BOARD_END + 13)
+#define IRQ_GPCIN4		(IRQ_BOARD_END + 14)
+#define IRQ_GPCIN5		(IRQ_BOARD_END + 15)
+#define IRQ_GPCIN6		(IRQ_BOARD_END + 16)
+#define IRQ_GPCIN7		(IRQ_BOARD_END + 17)
+#define IRQ_MSTXINT		(IRQ_BOARD_END + 18)
+#define IRQ_MSRXINT		(IRQ_BOARD_END + 19)
+#define IRQ_MSSTOPERRINT	(IRQ_BOARD_END + 20)
+#define IRQ_TPTXINT		(IRQ_BOARD_END + 21)
+#define IRQ_TPRXINT		(IRQ_BOARD_END + 22)
+#define IRQ_TPSTOPERRINT	(IRQ_BOARD_END + 23)
+#define SSPXMTINT		(IRQ_BOARD_END + 24)
+#define SSPRCVINT		(IRQ_BOARD_END + 25)
+#define SSPROR			(IRQ_BOARD_END + 26)
+#define AUDXMTDMADONEA		(IRQ_BOARD_END + 32)
+#define AUDRCVDMADONEA		(IRQ_BOARD_END + 33)
+#define AUDXMTDMADONEB		(IRQ_BOARD_END + 34)
+#define AUDRCVDMADONEB		(IRQ_BOARD_END + 35)
+#define AUDTFSR			(IRQ_BOARD_END + 36)
+#define AUDRFSR			(IRQ_BOARD_END + 37)
+#define AUDTUR			(IRQ_BOARD_END + 38)
+#define AUDROR			(IRQ_BOARD_END + 39)
+#define AUDDTS			(IRQ_BOARD_END + 40)
+#define AUDRDD			(IRQ_BOARD_END + 41)
+#define AUDSTO			(IRQ_BOARD_END + 42)
+#define IRQ_USBPWR		(IRQ_BOARD_END + 43)
+#define IRQ_HCIM		(IRQ_BOARD_END + 44)
+#define IRQ_HCIBUFFACC		(IRQ_BOARD_END + 45)
+#define IRQ_HCIRMTWKP		(IRQ_BOARD_END + 46)
+#define IRQ_NHCIMFCIR		(IRQ_BOARD_END + 47)
+#define IRQ_USB_PORT_RESUME	(IRQ_BOARD_END + 48)
+#define IRQ_S0_READY_NINT	(IRQ_BOARD_END + 49)
+#define IRQ_S1_READY_NINT	(IRQ_BOARD_END + 50)
+#define IRQ_S0_CD_VALID		(IRQ_BOARD_END + 51)
+#define IRQ_S1_CD_VALID		(IRQ_BOARD_END + 52)
+#define IRQ_S0_BVD1_STSCHG	(IRQ_BOARD_END + 53)
+#define IRQ_S1_BVD1_STSCHG	(IRQ_BOARD_END + 54)
 
-#if defined(CONFIG_ARCH_LUBBOCK) || defined(CONFIG_ARCH_PXA_IDP)
-#if CONFIG_SA1111
-#define LUBBOCK_IRQ(x)	(SA1111_IRQ_MAX + 1 + (x))
+/*
+ * Figure out the MAX IRQ number.
+ *
+ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
+ * Otherwise, we have the standard IRQs only.
+ */
+#ifdef CONFIG_SA1111
+#define NR_IRQS			(IRQ_S1_BVD1_STSCHG + 1)
+#elif defined(CONFIG_ARCH_LUBBOCK)
+#define NR_IRQS			(IRQ_BOARD_END)
 #else
-#define LUBBOCK_IRQ(x)	(IRQ_GPIO(80) + 1 + (x))
+#define NR_IRQS			(IRQ_BOARD_START)
 #endif
 
+/*
+ * Board specific IRQs.  Define them here.
+ * Do not surround them with ifdefs.
+ */
+#define LUBBOCK_IRQ(x)		(IRQ_BOARD_START + (x))
 #define LUBBOCK_SD_IRQ		LUBBOCK_IRQ(0)
 #define LUBBOCK_SA1111_IRQ	LUBBOCK_IRQ(1)
 #define LUBBOCK_USB_IRQ		LUBBOCK_IRQ(2)
@@ -123,10 +131,3 @@
 #define LUBBOCK_UCB1400_IRQ	LUBBOCK_IRQ(4)
 #define LUBBOCK_BB_IRQ		LUBBOCK_IRQ(5)
 
-#undef NR_IRQS
-#define NR_IRQS		(LUBBOCK_IRQ(5) + 1)
-
-#endif	// CONFIG_ARCH_LUBBOCK
-
-
-

include/asm-arm/arch-pxa/lubbock.h

@@ -13,7 +13,6 @@
 #define LUBBOCK_FPGA_PHYS	PXA_CS2_PHYS
 #define LUBBOCK_FPGA_VIRT	(0xf0000000)	/* phys 0x08000000 */
 #define LUBBOCK_ETH_BASE	(0xf1000000)	/* phys 0x0c000000 */
-#define LUBBOCK_SA1111_BASE	(0xf4000000)	/* phys 0x10000000 */
 
 #define LUB_P2V(x)		((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
 #define LUB_V2P(x)		((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)

include/asm-arm/arch-pxa/pxa-regs.h

@@ -380,32 +380,12 @@ typedef void            (*ExcpHndlr) (void) ;
 /*
  * IrSR (Infrared Selection Register)
  */
-#define IrSR_OFFSET 0x20
-
-#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
-#define IrSR_RXPL_POS_IS_ZERO 0x0
-#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
-#define IrSR_TXPL_POS_IS_ZERO 0x0
-#define IrSR_XMODE_PULSE_1_6  (1<<2)
-#define IrSR_XMODE_PULSE_3_16 0x0
-#define IrSR_RCVEIR_IR_MODE   (1<<1)
-#define IrSR_RCVEIR_UART_MODE 0x0
-#define IrSR_XMITIR_IR_MODE   (1<<0)
-#define IrSR_XMITIR_UART_MODE 0x0
-
-#define IrSR_IR_RECEIVE_ON (\
-                IrSR_RXPL_NEG_IS_ZERO | \
-                IrSR_TXPL_POS_IS_ZERO | \
-                IrSR_XMODE_PULSE_3_16 | \
-                IrSR_RCVEIR_IR_MODE   | \
-                IrSR_XMITIR_UART_MODE)
-
-#define IrSR_IR_TRANSMIT_ON (\
-                IrSR_RXPL_NEG_IS_ZERO | \
-                IrSR_TXPL_POS_IS_ZERO | \
-                IrSR_XMODE_PULSE_3_16 | \
-                IrSR_RCVEIR_UART_MODE | \
-                IrSR_XMITIR_IR_MODE)
+#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
+#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
+#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
+#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
+#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
+
 
 /*
  * I2C registers
@@ -417,53 +397,49 @@ typedef void            (*ExcpHndlr) (void) ;
 #define ISR		__REG(0x40301698)  /* I2C Status Register - ISR */
 #define ISAR		__REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
 
-/* ----- Control register bits ---------------------------------------- */
-
-#define ICR_START	0x1		/* start bit */
-#define ICR_STOP	0x2		/* stop bit */
-#define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
-#define ICR_TB		0x8 		/* transfer byte bit */
-#define ICR_MA		0x10		/* master abort */
-#define ICR_SCLE	0x20		/* master clock enable */
-#define ICR_IUE		0x40		/* unit enable */
-#define ICR_GCD		0x80		/* general call disable */
-#define ICR_ITEIE	0x100		/* enable tx interrupts */
-#define ICR_IRFIE	0x200		/* enable rx interrupts */
-#define ICR_BEIE	0x400		/* enable bus error ints */
-#define ICR_SSDIE	0x800		/* slave STOP detected int enable */
-#define ICR_ALDIE	0x1000  	/* enable arbitration interrupt */
-#define ICR_SADIE	0x2000		/* slave address detected int enable */
-#define ICR_UR		0x4000		/* unit reset */
-
-/* ----- Status register bits ----------------------------------------- */
-
-#define ISR_RWM         0x1		/* read/write mode */
-#define ISR_ACKNAK      0x2		/* ack/nak status */
-#define ISR_UB          0x4		/* unit busy */
-#define ISR_IBB         0x8		/* bus busy */
-#define ISR_SSD         0x10		/* slave stop detected */
-#define ISR_ALD         0x20		/* arbitration loss detected */
-#define ISR_ITE         0x40            /* tx buffer empty */
-#define ISR_IRF         0x80            /* rx buffer full */
-#define ISR_GCAD        0x100		/* general call address detected */
-#define ISR_SAD         0x200		/* slave address detected */
-#define ISR_BED         0x400           /* bus error no ACK/NAK */
+#define ICR_START	(1 << 0)	   /* start bit */
+#define ICR_STOP	(1 << 1)	   /* stop bit */
+#define ICR_ACKNAK	(1 << 2)	   /* send ACK(0) or NAK(1) */
+#define ICR_TB		(1 << 3)	   /* transfer byte bit */
+#define ICR_MA		(1 << 4)	   /* master abort */
+#define ICR_SCLE	(1 << 5)	   /* master clock enable */
+#define ICR_IUE		(1 << 6)	   /* unit enable */
+#define ICR_GCD		(1 << 7)	   /* general call disable */
+#define ICR_ITEIE	(1 << 8)	   /* enable tx interrupts */
+#define ICR_IRFIE	(1 << 9)	   /* enable rx interrupts */
+#define ICR_BEIE	(1 << 10)	   /* enable bus error ints */
+#define ICR_SSDIE	(1 << 11)	   /* slave STOP detected int enable */
+#define ICR_ALDIE	(1 << 12)	   /* enable arbitration interrupt */
+#define ICR_SADIE	(1 << 13)	   /* slave address detected int enable */
+#define ICR_UR		(1 << 14)	   /* unit reset */
+
+#define ISR_RWM		(1 << 0)	   /* read/write mode */
+#define ISR_ACKNAK	(1 << 1)	   /* ack/nak status */
+#define ISR_UB		(1 << 2)	   /* unit busy */
+#define ISR_IBB		(1 << 3)	   /* bus busy */
+#define ISR_SSD		(1 << 4)	   /* slave stop detected */
+#define ISR_ALD		(1 << 5)	   /* arbitration loss detected */
+#define ISR_ITE		(1 << 6)	   /* tx buffer empty */
+#define ISR_IRF		(1 << 7)	   /* rx buffer full */
+#define ISR_GCAD	(1 << 8)	   /* general call address detected */
+#define ISR_SAD		(1 << 9)	   /* slave address detected */
+#define ISR_BED		(1 << 10)	   /* bus error no ACK/NAK */
+
 
 /*
  * Serial Audio Controller
  */
 
-
-/* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
- * short defines because there is too much chance of namespace collision */
-
-//#define SACR0		__REG(0x40400000)  /* Global Control Register */
-//#define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
-//#define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-//#define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
-//#define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
-//#define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
-//#define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
+/* FIXME: This clash with SA1111 defines */
+#ifndef CONFIG_SA1111
+#define SACR0		__REG(0x40400000)  /* Global Control Register */
+#define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
+#define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
+#define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
+#define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
+#endif
 
 
 /*
@@ -714,6 +690,30 @@ typedef void            (*ExcpHndlr) (void) ;
 #define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
 #define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */
 
+#define ICCR0_AME       (1 << 7)           /* Adress match enable */
+#define ICCR0_TIE       (1 << 6)           /* Transmit FIFO interrupt enable */
+#define ICCR0_RIE       (1 << 5)           /* Recieve FIFO interrupt enable */
+#define ICCR0_RXE       (1 << 4)           /* Receive enable */
+#define ICCR0_TXE       (1 << 3)           /* Transmit enable */
+#define ICCR0_TUS       (1 << 2)           /* Transmit FIFO underrun select */
+#define ICCR0_LBM       (1 << 1)           /* Loopback mode */
+#define ICCR0_ITR       (1 << 0)           /* IrDA transmission */
+
+#define ICSR0_FRE       (1 << 5)           /* Framing error */
+#define ICSR0_RFS       (1 << 4)           /* Receive FIFO service request */
+#define ICSR0_TFS       (1 << 3)           /* Transnit FIFO service request */
+#define ICSR0_RAB       (1 << 2)           /* Receiver abort */
+#define ICSR0_TUR       (1 << 1)           /* Trunsmit FIFO underun */
+#define ICSR0_EIF       (1 << 0)           /* End/Error in FIFO */
+
+#define ICSR1_ROR       (1 << 6)           /* Receiver FIFO underrun  */
+#define ICSR1_CRE       (1 << 5)           /* CRC error */
+#define ICSR1_EOF       (1 << 4)           /* End of frame */
+#define ICSR1_TNF       (1 << 3)           /* Transmit FIFO not full */
+#define ICSR1_RNE       (1 << 2)           /* Receive FIFO not empty */
+#define ICSR1_TBY       (1 << 1)           /* Tramsmiter busy flag */
+#define ICSR1_RSY       (1 << 0)           /* Recevier synchronized flag */
+
 
 /*
  * Real Time Clock
@@ -1171,19 +1171,105 @@ typedef void            (*ExcpHndlr) (void) ;
 #define LCCR0_BM	(1 << 20) 	/* Branch mask */
 #define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
 
+#define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
+                        (((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization     */
+#define LCCR1_HorSnchWdth(Tpix)         /* Horizontal Synchronization     */ \
+                                        /* pulse Width [1..64 Tpix]       */ \
+                        (((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait    */
+                                        /* count - 1 [Tpix]                */
+#define LCCR1_EndLnDel(Tpix)            /*  End-of-Line Delay              */ \
+                                        /*  [1..256 Tpix]                  */ \
+                        (((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock   */
+                                        /* Wait count - 1 [Tpix]           */
+#define LCCR1_BegLnDel(Tpix)            /*  Beginning-of-Line Delay        */ \
+                                        /*  [1..256 Tpix]                  */ \
+                        (((Tpix) - 1) << FShft (LCCR1_BLW))
+
+
+#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1              */
+#define LCCR2_DisHght(Line)             /*  Display Height [1..1024 lines] */ \
+                        (((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse  */
+                                        /* Width - 1 [Tln] (L_FCLK)        */
+#define LCCR2_VrtSnchWdth(Tln)          /*  Vertical Synchronization pulse */ \
+                                        /*  Width [1..64 Tln]              */ \
+                        (((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait    */
+                                        /* count [Tln]                     */
+#define LCCR2_EndFrmDel(Tln)            /*  End-of-Frame Delay             */ \
+                                        /*  [0..255 Tln]                   */ \
+                        ((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock   */
+                                        /* Wait count [Tln]                */
+#define LCCR2_BegFrmDel(Tln)            /*  Beginning-of-Frame Delay       */ \
+                                        /*  [0..255 Tln]                   */ \
+                        ((Tln) << FShft (LCCR2_BFW))
+
+#if 0
 #define LCCR3_PCD	(0xff)		/* Pixel clock divisor */
 #define LCCR3_ACB	(0xff << 8)	/* AC Bias pin frequency */
 #define LCCR3_ACB_S	8
+#endif
+
 #define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
 #define LCCR3_API_S	16
 #define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
 #define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
 #define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
 #define LCCR3_OEP	(1 << 23)	/* output enable polarity */
+#if 0
 #define LCCR3_BPP	(7 << 24)	/* bits per pixel */
 #define LCCR3_BPP_S	24
+#endif
 #define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
 
+
+#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)            /* Pixel Clock Divisor */ \
+                        (((Div) << FShft (LCCR3_PCD)))
+
+
+#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)                  /* Bit Per Pixel */ \
+                        (((Bpp) << FShft (LCCR3_BPP)))
+
+#define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
+#define LCCR3_Acb(Acb)                  /* BAC Bias */ \
+                        (((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  Horizontal Synchronization     */
+                                        /*  pulse active High              */
+#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  Horizontal Synchronization     */
+
+#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  Vertical Synchronization pulse */
+                                        /*  active High                    */
+#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  Vertical Synchronization pulse */
+                                        /*  active Low                     */
+
+#define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
+#define LCSR_SOF	(1 << 1)	/* Start of frame */
+#define LCSR_BER	(1 << 2)	/* Bus error */
+#define LCSR_ABC	(1 << 3)	/* AC Bias count */
+#define LCSR_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
+#define LCSR_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
+#define LCSR_OU		(1 << 6)	/* output FIFO underrun */
+#define LCSR_QD		(1 << 7)	/* quick disable */
+#define LCSR_EOF	(1 << 8)	/* end of frame */
+#define LCSR_BS		(1 << 9)	/* branch status */
+#define LCSR_SINT	(1 << 10)	/* subsequent interrupt */
+
+#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
+
 #define LCSR_LDD	(1 << 0)	/* LCD Disable Done */
 #define LCSR_SOF	(1 << 1)	/* Start of frame */
 #define LCSR_BER	(1 << 2)	/* Bus error */

include/asm-arm/arch-pxa/system.h

@@ -27,7 +27,7 @@ static inline void arch_reset(char mode)
 		/* Initialize the watchdog and let it fire */
 		OWER = OWER_WME;
 		OSSR = OSSR_M3;
-		OSMR3 = OSCR + 36864;	/* ... in 10 ms */
+		OSMR3 = OSCR + 368640;	/* ... in 100 ms */
 	}
 }
 

include/asm-arm/arch-pxa/time.h

@@ -42,7 +42,7 @@ static unsigned long pxa_gettimeoffset (void)
 	elapsed = LATCH - ticks_to_match;
 
 	/* Now convert them to usec */
-	usec = (unsigned long)(elapsed*tick)/LATCH;
+	usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
 
 	return usec;
 }
@@ -52,6 +52,8 @@ static void pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	long flags;
 	int next_match;
 
+	do_profile(regs);
+
 	/* Loop until we get ahead of the free running timer.
 	 * This ensures an exact clock tick count and time accuracy.
 	 * IRQs are disabled inside the loop to ensure coherence between