Commit 8e1c3aa3 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman

arm64: dts: r8a7795: Add CA53 L2 cache-controller node

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a528b4bf
......@@ -72,6 +72,12 @@ L2_CA57: cache-controller@0 {
cache-level = <2>;
};
L2_CA53: cache-controller@1 {
compatible = "cache";
cache-unified;
cache-level = <2>;
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment