Commit 8e9c24a2 authored by Russell King's avatar Russell King Committed by Will Deacon

ARM: virt: avoid clobbering lr when forcing svc mode

The safe_svcmode_maskall macro is used to ensure that we are running in
svc mode, causing an exception return from hvc mode if required.

This patch removes the unneeded lr clobber from the macro and operates
entirely on the temporary parameter register instead.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
[will: updated comment]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 9931faca
...@@ -246,18 +246,14 @@ ...@@ -246,18 +246,14 @@
* *
* This macro is intended for forcing the CPU into SVC mode at boot time. * This macro is intended for forcing the CPU into SVC mode at boot time.
* you cannot return to the original mode. * you cannot return to the original mode.
*
* Beware, it also clobers LR.
*/ */
.macro safe_svcmode_maskall reg:req .macro safe_svcmode_maskall reg:req
#if __LINUX_ARM_ARCH__ >= 6 #if __LINUX_ARM_ARCH__ >= 6
mrs \reg , cpsr mrs \reg , cpsr
mov lr , \reg eor \reg, \reg, #HYP_MODE
and lr , lr , #MODE_MASK tst \reg, #MODE_MASK
cmp lr , #HYP_MODE
orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT
bic \reg , \reg , #MODE_MASK bic \reg , \reg , #MODE_MASK
orr \reg , \reg , #SVC_MODE orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
THUMB( orr \reg , \reg , #PSR_T_BIT ) THUMB( orr \reg , \reg , #PSR_T_BIT )
bne 1f bne 1f
orr \reg, \reg, #PSR_A_BIT orr \reg, \reg, #PSR_A_BIT
......
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