Commit 9056b559 authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://gkernel.bkbits.net/libata-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 29f175ce 7457affc
......@@ -53,6 +53,7 @@ restrictions referred to are that the relevant option is valid if:
NFS Appropriate NFS support is enabled.
OSS OSS sound support is enabled.
PARIDE The ParIDE subsystem is enabled.
PARISC The PA-RISC architecture is enabled.
PCI PCI bus support is enabled.
PCMCIA The PCMCIA subsystem is enabled.
PNP Plug & Play support is enabled.
......@@ -394,7 +395,7 @@ running once the system is up.
eicon= [HW,ISDN]
Format: <id>,<membase>,<irq>
eisa_irq_edge= [PARISC]
eisa_irq_edge= [PARISC,HW]
See header of drivers/parisc/eisa.c.
elanfreq= [IA-32]
......@@ -933,6 +934,11 @@ running once the system is up.
pd. [PARIDE]
See Documentation/paride.txt.
pdcchassis= [PARISC,HW] Disable/Enable PDC Chassis Status codes at
boot time.
Format: { 0 | 1 }
See arch/parisc/kernel/pdc_chassis.c
pf. [PARIDE]
See Documentation/paride.txt.
......@@ -1250,7 +1256,7 @@ running once the system is up.
st0x= [HW,SCSI]
See header of drivers/scsi/seagate.c.
sti= [HW]
sti= [PARISC,HW]
Format: <num>
Set the STI (builtin display/keyboard on the HP-PARISC
machines) console (graphic card) which should be used
......
......@@ -1110,8 +1110,8 @@ P: John Ronciak
M: john.ronciak@intel.com
P: Ganesh Venkatesan
M: ganesh.venkatesan@intel.com
P: Scott Feldman
M: scott.feldman@intel.com
P: Jesse Brandeburg
M: jesse.brandeburg@intel.com
W: http://sourceforge.net/projects/e1000/
S: Supported
......
......@@ -194,7 +194,7 @@ amba_attr(resource, "\t%08lx\t%08lx\t%08lx\n",
int amba_device_register(struct amba_device *dev, struct resource *parent)
{
u32 pid, cid;
void *tmp;
void __iomem *tmp;
int i, ret;
dev->dev.release = amba_device_release;
......
......@@ -27,9 +27,9 @@
#include <asm/io.h>
#include <asm/page.h>
static u32 __isamem_convert_addr(void *addr)
static void __iomem *__isamem_convert_addr(void __iomem *addr)
{
u32 ret, a = (u32) addr;
u32 ret, a = (u32 __force) addr;
/*
* The PCMCIA controller is wired up as follows:
......@@ -53,41 +53,43 @@ static u32 __isamem_convert_addr(void *addr)
ret += 0xe8000000;
if ((a & 0x20000) == (a & 0x40000) >> 1)
return ret;
return (void __iomem *)ret;
BUG();
return 0;
return NULL;
}
/*
* read[bwl] and write[bwl]
*/
u8 __readb(void *addr)
u8 __readb(void __iomem *addr)
{
u32 ret, a = __isamem_convert_addr(addr);
void __iomem *a = __isamem_convert_addr(addr);
u32 ret;
if ((int)addr & 1)
if ((unsigned long)addr & 1)
ret = __raw_readl(a);
else
ret = __raw_readb(a);
return ret;
}
u16 __readw(void *addr)
u16 __readw(void __iomem *addr)
{
u32 a = __isamem_convert_addr(addr);
void __iomem *a = __isamem_convert_addr(addr);
if ((int)addr & 1)
if ((unsigned long)addr & 1)
BUG();
return __raw_readw(a);
}
u32 __readl(void *addr)
u32 __readl(void __iomem *addr)
{
u32 ret, a = __isamem_convert_addr(addr);
void __iomem *a = __isamem_convert_addr(addr);
u32 ret;
if ((int)addr & 3)
if ((unsigned long)addr & 3)
BUG();
ret = __raw_readw(a);
......@@ -99,31 +101,31 @@ EXPORT_SYMBOL(__readb);
EXPORT_SYMBOL(__readw);
EXPORT_SYMBOL(__readl);
void __writeb(u8 val, void *addr)
void __writeb(u8 val, void __iomem *addr)
{
u32 a = __isamem_convert_addr(addr);
void __iomem *a = __isamem_convert_addr(addr);
if ((int)addr & 1)
if ((unsigned long)addr & 1)
__raw_writel(val, a);
else
__raw_writeb(val, a);
}
void __writew(u16 val, void *addr)
void __writew(u16 val, void __iomem *addr)
{
u32 a = __isamem_convert_addr(addr);
void __iomem *a = __isamem_convert_addr(addr);
if ((int)addr & 1)
if ((unsigned long)addr & 1)
BUG();
__raw_writew(val, a);
}
void __writel(u32 val, void *addr)
void __writel(u32 val, void __iomem *addr)
{
u32 a = __isamem_convert_addr(addr);
void __iomem *a = __isamem_convert_addr(addr);
if ((int)addr & 3)
if ((unsigned long)addr & 3)
BUG();
__raw_writew(val, a);
......@@ -153,7 +155,7 @@ u8 __inb8(unsigned int port)
if (SUPERIO_PORT(port))
ret = __raw_readb(ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
......@@ -180,7 +182,7 @@ u8 __inb16(unsigned int port)
if (SUPERIO_PORT(port))
ret = __raw_readb(ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
......@@ -200,7 +202,7 @@ u16 __inw(unsigned int port)
if (SUPERIO_PORT(port))
ret = __raw_readw(ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
......@@ -218,7 +220,7 @@ u16 __inw(unsigned int port)
*/
u32 __inl(unsigned int port)
{
u32 a;
void __iomem *a;
if (SUPERIO_PORT(port) || port & 3)
BUG();
......@@ -241,7 +243,7 @@ void __outb8(u8 val, unsigned int port)
if (SUPERIO_PORT(port))
__raw_writeb(val, ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
......@@ -261,7 +263,7 @@ void __outb16(u8 val, unsigned int port)
if (SUPERIO_PORT(port))
__raw_writeb(val, ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
......
......@@ -52,7 +52,7 @@
#include <asm/arch/map.h>
/* io map for dma */
static void *dma_base;
static void __iomem *dma_base;
/* dma channel state information */
s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];
......@@ -1065,7 +1065,7 @@ static int __init s3c2410_init_dma(void)
/* dma channel irqs are in order.. */
cp->number = channel;
cp->irq = channel + IRQ_DMA0;
cp->regs = (unsigned long)dma_base + (channel*0x40);
cp->regs = dma_base + (channel*0x40);
/* point current stats somewhere */
cp->stats = &cp->stats_store;
......@@ -1075,7 +1075,7 @@ static int __init s3c2410_init_dma(void)
cp->load_timeout = 1<<18;
printk("DMA channel %d at %08lx, irq %d\n",
printk("DMA channel %d at %p, irq %d\n",
cp->number, cp->regs, cp->irq);
}
......
......@@ -130,7 +130,7 @@ remap_area_pages(unsigned long start, unsigned long phys_addr,
* 'flags' are the extra L_PTE_ flags that you want to specify for this
* mapping. See include/asm-arm/proc-armv/pgtable.h for more information.
*/
void *
void __iomem *
__ioremap(unsigned long phys_addr, size_t size, unsigned long flags,
unsigned long align)
{
......@@ -161,11 +161,11 @@ __ioremap(unsigned long phys_addr, size_t size, unsigned long flags,
vfree(addr);
return NULL;
}
return (void *) (offset + (char *)addr);
return (void __iomem *) (offset + (char *)addr);
}
EXPORT_SYMBOL(__ioremap);
void __iounmap(void *addr)
void __iounmap(void __iomem *addr)
{
vfree((void *) (PAGE_MASK & (unsigned long) addr));
}
......
......@@ -69,7 +69,7 @@ static void mmci_stop_data(struct mmci_host *host)
static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
{
unsigned int datactrl, timeout, irqmask;
void *base;
void __iomem *base;
DBG(host, "blksz %04x blks %04x flags %08x\n",
1 << data->blksz_bits, data->blocks, data->flags);
......@@ -108,7 +108,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
static void
mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
{
void *base = host->base;
void __iomem *base = host->base;
DBG(host, "op %02x arg %08x flags %08x\n",
cmd->opcode, cmd->arg, cmd->flags);
......@@ -169,7 +169,7 @@ static void
mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
unsigned int status)
{
void *base = host->base;
void __iomem *base = host->base;
host->cmd = NULL;
......@@ -193,7 +193,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
{
void *base = host->base;
void __iomem *base = host->base;
char *ptr = buffer;
u32 status;
......@@ -222,7 +222,7 @@ static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int rema
static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
{
void *base = host->base;
void __iomem *base = host->base;
char *ptr = buffer;
do {
......@@ -251,7 +251,7 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
{
struct mmci_host *host = dev_id;
void *base = host->base;
void __iomem *base = host->base;
u32 status;
status = readl(base + MMCISTATUS);
......
......@@ -120,7 +120,7 @@
struct clk;
struct mmci_host {
void *base;
void __iomem *base;
struct mmc_request *mrq;
struct mmc_command *cmd;
struct mmc_data *data;
......
......@@ -813,7 +813,7 @@ static void ei_rx_overrun(struct net_device *dev)
* We wait at least 10ms.
*/
udelay(10*1000);
mdelay(10);
/*
* Reset RBCR[01] back to zero as per magic incantation.
......
......@@ -211,7 +211,7 @@ static void amd8111e_set_ext_phy(struct net_device *dev)
u32 bmcr,advert,tmp;
/* Determine mii register values to set the speed */
advert = amd8111e_mdio_read(dev, PHY_ID, MII_ADVERTISE);
advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
switch (lp->ext_phy_option){
......@@ -235,11 +235,11 @@ static void amd8111e_set_ext_phy(struct net_device *dev)
}
if(advert != tmp)
amd8111e_mdio_write(dev, PHY_ID, MII_ADVERTISE, tmp);
amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
/* Restart auto negotiation */
bmcr = amd8111e_mdio_read(dev, PHY_ID, MII_BMCR);
bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
amd8111e_mdio_write(dev, PHY_ID, MII_BMCR, bmcr);
amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
}
......@@ -350,6 +350,7 @@ static int amd8111e_init_ring(struct net_device *dev)
lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
wmb();
lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
}
......@@ -529,7 +530,7 @@ static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
writel(RUN, mmio + CMD0);
/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
writew( 0x8101, mmio + AUTOPOLL0);
writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
/* Clear RCV_RING_BASE_ADDR */
writel(0, mmio + RCV_RING_BASE_ADDR0);
......@@ -740,11 +741,11 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
do{
/* process receive packets until we use the quota*/
/* If we own the next entry, it's a new packet. Send it up. */
while(!(lp->rx_ring[rx_index].rx_flags & OWN_BIT)){
/* check if err summary bit is set */
if(le16_to_cpu(lp->rx_ring[rx_index].rx_flags)
& ERR_BIT){
while(1) {
status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
if (status & OWN_BIT)
break;
/*
* There is a tricky error noted by John Murphy,
* <murf@perftech.com> to Russ Nelson: Even with
......@@ -753,89 +754,88 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
* the last correctly noting the error.
*/
/* reseting flags */
lp->rx_ring[rx_index].rx_flags &=RESET_RX_FLAGS;
goto err_next_pkt;
if(status & ERR_BIT) {
/* reseting flags */
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
goto err_next_pkt;
}
/* check for STP and ENP */
status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
if(!((status & STP_BIT) && (status & ENP_BIT))){
/* reseting flags */
lp->rx_ring[rx_index].rx_flags &=RESET_RX_FLAGS;
goto err_next_pkt;
}
pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
if(!((status & STP_BIT) && (status & ENP_BIT))){
/* reseting flags */
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
goto err_next_pkt;
}
pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
#if AMD8111E_VLAN_TAG_USED
vtag = le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & TT_MASK;
/*MAC will strip vlan tag*/
if(lp->vlgrp != NULL && vtag !=0)
min_pkt_len =MIN_PKT_LEN - 4;
else
vtag = status & TT_MASK;
/*MAC will strip vlan tag*/
if(lp->vlgrp != NULL && vtag !=0)
min_pkt_len =MIN_PKT_LEN - 4;
else
#endif
min_pkt_len =MIN_PKT_LEN;
min_pkt_len =MIN_PKT_LEN;
if (pkt_len < min_pkt_len) {
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
lp->drv_rx_errors++;
goto err_next_pkt;
}
if(--rx_pkt_limit < 0)
goto rx_not_empty;
if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
/* if allocation fail,
ignore that pkt and go to next one */
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
lp->drv_rx_errors++;
goto err_next_pkt;
}
if (pkt_len < min_pkt_len) {
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
lp->drv_rx_errors++;
goto err_next_pkt;
}
if(--rx_pkt_limit < 0)
goto rx_not_empty;
if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
/* if allocation fail,
ignore that pkt and go to next one */
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
lp->drv_rx_errors++;
goto err_next_pkt;
}
skb_reserve(new_skb, 2);
skb = lp->rx_skbuff[rx_index];
pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
skb_put(skb, pkt_len);
skb->dev = dev;
lp->rx_skbuff[rx_index] = new_skb;
new_skb->dev = dev;
lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
skb_reserve(new_skb, 2);
skb = lp->rx_skbuff[rx_index];
pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
skb_put(skb, pkt_len);
skb->dev = dev;
lp->rx_skbuff[rx_index] = new_skb;
new_skb->dev = dev;
lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
new_skb->data,
lp->rx_buff_len-2,
PCI_DMA_FROMDEVICE);
skb->protocol = eth_type_trans(skb, dev);
skb->protocol = eth_type_trans(skb, dev);
#if AMD8111E_VLAN_TAG_USED
vtag = lp->rx_ring[rx_index].rx_flags & TT_MASK;
if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
amd8111e_vlan_rx(lp, skb,
lp->rx_ring[rx_index].tag_ctrl_info);
} else
if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
amd8111e_vlan_rx(lp, skb,
le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
} else
#endif
netif_receive_skb(skb);
/*COAL update rx coalescing parameters*/
lp->coal_conf.rx_packets++;
lp->coal_conf.rx_bytes += pkt_len;
num_rx_pkt++;
dev->last_rx = jiffies;
netif_receive_skb(skb);
/*COAL update rx coalescing parameters*/
lp->coal_conf.rx_packets++;
lp->coal_conf.rx_bytes += pkt_len;
num_rx_pkt++;
dev->last_rx = jiffies;
err_next_pkt:
lp->rx_ring[rx_index].buff_phy_addr
= cpu_to_le32(lp->rx_dma_addr[rx_index]);
lp->rx_ring[rx_index].buff_count =
err_next_pkt:
lp->rx_ring[rx_index].buff_phy_addr
= cpu_to_le32(lp->rx_dma_addr[rx_index]);
lp->rx_ring[rx_index].buff_count =
cpu_to_le16(lp->rx_buff_len-2);
lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
}
/* Check the interrupt status register for more packets in the
mean time. Process them since we have not used up our quota.*/
wmb();
lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
}
/* Check the interrupt status register for more packets in the
mean time. Process them since we have not used up our quota.*/
intr0 = readl(mmio + INT0);
/*Ack receive packets */
writel(intr0 & RINT0,mmio + INT0);
intr0 = readl(mmio + INT0);
/*Ack receive packets */
writel(intr0 & RINT0,mmio + INT0);
}while(intr0 & RINT0);
} while(intr0 & RINT0);
/* Receive descriptor is empty now */
dev->quota -= num_rx_pkt;
......@@ -873,11 +873,12 @@ static int amd8111e_rx(struct net_device *dev)
/* If we own the next entry, it's a new packet. Send it up. */
while(++num_rx_pkt <= max_rx_pkt){
if(lp->rx_ring[rx_index].rx_flags & OWN_BIT)
status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
if(status & OWN_BIT)
return 0;
/* check if err summary bit is set */
if(le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & ERR_BIT){
if(status & ERR_BIT){
/*
* There is a tricky error noted by John Murphy,
* <murf@perftech.com> to Russ Nelson: Even with full-sized
......@@ -888,7 +889,6 @@ static int amd8111e_rx(struct net_device *dev)
goto err_next_pkt;
}
/* check for STP and ENP */
status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
if(!((status & STP_BIT) && (status & ENP_BIT))){
/* reseting flags */
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
......@@ -897,7 +897,7 @@ static int amd8111e_rx(struct net_device *dev)
pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
#if AMD8111E_VLAN_TAG_USED
vtag = le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & TT_MASK;
vtag = status & TT_MASK;
/*MAC will strip vlan tag*/
if(lp->vlgrp != NULL && vtag !=0)
min_pkt_len =MIN_PKT_LEN - 4;
......@@ -931,12 +931,10 @@ static int amd8111e_rx(struct net_device *dev)
skb->protocol = eth_type_trans(skb, dev);
#if AMD8111E_VLAN_TAG_USED
vtag = lp->rx_ring[rx_index].rx_flags & TT_MASK;
#if AMD8111E_VLAN_TAG_USED
if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
amd8111e_vlan_rx(lp, skb,
lp->rx_ring[rx_index].tag_ctrl_info);
le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
} else
#endif
......@@ -952,6 +950,7 @@ static int amd8111e_rx(struct net_device *dev)
= cpu_to_le32(lp->rx_dma_addr[rx_index]);
lp->rx_ring[rx_index].buff_count =
cpu_to_le16(lp->rx_buff_len-2);
wmb();
lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
}
......@@ -1432,7 +1431,7 @@ static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
#if AMD8111E_VLAN_TAG_USED
if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
lp->tx_ring[tx_index].tag_ctrl_cmd |=
cpu_to_le32(TCC_VLAN_INSERT);
cpu_to_le16(TCC_VLAN_INSERT);
lp->tx_ring[tx_index].tag_ctrl_info =
cpu_to_le16(vlan_tx_tag_get(skb));
......@@ -1444,6 +1443,7 @@ static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
(u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
/* Set FCS and LTINT bits */
wmb();
lp->tx_ring[tx_index].tx_flags |=
cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
......@@ -1667,7 +1667,7 @@ static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
switch(cmd) {
case SIOCGMIIPHY:
data->phy_id = PHY_ID;
data->phy_id = lp->ext_phy_addr;
/* fallthru */
case SIOCGMIIREG:
......@@ -1940,6 +1940,26 @@ static void amd8111e_config_ipg(struct net_device* dev)
}
static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
{
struct amd8111e_priv *lp = netdev_priv(dev);
int i;
for (i = 0x1e; i >= 0; i--) {
u32 id1, id2;
if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
continue;
if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
continue;
lp->ext_phy_id = (id1 << 16) | id2;
lp->ext_phy_addr = i;
return;
}
lp->ext_phy_id = 0;
lp->ext_phy_addr = 1;
}
static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
......@@ -2010,12 +2030,6 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
lp->amd8111e_net_dev = dev;
lp->pm_cap = pm_cap;
/* setting mii default values */
lp->mii_if.dev = dev;
lp->mii_if.mdio_read = amd8111e_mdio_read;
lp->mii_if.mdio_write = amd8111e_mdio_write;
lp->mii_if.phy_id = PHY_ID;
spin_lock_init(&lp->lock);
lp->mmio = ioremap(reg_addr, reg_len);
......@@ -2063,7 +2077,15 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
dev->vlan_rx_register =amd8111e_vlan_rx_register;
dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
#endif
/* Probe the external PHY */
amd8111e_probe_ext_phy(dev);
/* setting mii default values */
lp->mii_if.dev = dev;
lp->mii_if.mdio_read = amd8111e_mdio_read;
lp->mii_if.mdio_write = amd8111e_mdio_write;
lp->mii_if.phy_id = lp->ext_phy_addr;
/* Set receive buffer length and set jumbo option*/
amd8111e_set_rx_buff_len(dev);
......@@ -2096,6 +2118,12 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
for (i = 0; i < 6; i++)
printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
printk( "\n");
if (lp->ext_phy_id)
printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
dev->name, lp->ext_phy_id, lp->ext_phy_addr);
else
printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
dev->name);
return 0;
err_iounmap:
iounmap(lp->mmio);
......
......@@ -649,7 +649,6 @@ typedef enum {
#define TCC_MASK 0x0003
/* driver ioctl parameters */
#define PHY_ID 0x01 /* currently it is fixed */
#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
/* crc generator constants */
......@@ -777,6 +776,8 @@ struct amd8111e_priv{
int options; /* Options enabled/disabled for the device */
unsigned long ext_phy_option;
int ext_phy_addr;
u32 ext_phy_id;
struct amd8111e_link_config link_config;
int pm_cap;
......
......@@ -40,6 +40,7 @@
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/device.h>
......@@ -56,14 +57,19 @@
#define NET_DEBUG 0
#define DEBUG_INIT 2
#define DRV_NAME "etherh"
#define DRV_VERSION "1.11"
static unsigned int net_debug = NET_DEBUG;
struct etherh_priv {
void *ioc_fast;
void *memc;
void __iomem *ioc_fast;
void __iomem *memc;
void __iomem *dma_base;
unsigned int id;
void *ctrl_port;
void __iomem *ctrl_port;
unsigned char ctrl;
u32 supported;
};
struct etherh_data {
......@@ -72,11 +78,7 @@ struct etherh_data {
unsigned long ctrlport_offset;
int ctrl_ioc;
const char name[16];
/*
* netdev flags and port
*/
unsigned short flags;
unsigned char if_port;
u32 supported;
unsigned char tx_start_page;
unsigned char stop_page;
};
......@@ -86,7 +88,7 @@ MODULE_DESCRIPTION("EtherH/EtherM driver");
MODULE_LICENSE("GPL");
static char version[] __initdata =
"EtherH/EtherM Driver (c) 2002 Russell King v1.09\n";
"EtherH/EtherM Driver (c) 2002-2004 Russell King " DRV_VERSION "\n";
#define ETHERH500_DATAPORT 0x800 /* MEMC */
#define ETHERH500_NS8390 0x000 /* MEMC */
......@@ -166,7 +168,8 @@ static void
etherh_setif(struct net_device *dev)
{
struct ei_device *ei_local = netdev_priv(dev);
unsigned long addr, flags;
unsigned long flags;
void __iomem *addr;
local_irq_save(flags);
......@@ -174,7 +177,7 @@ etherh_setif(struct net_device *dev)
switch (etherh_priv(dev)->id) {
case PROD_I3_ETHERLAN600:
case PROD_I3_ETHERLAN600A:
addr = dev->base_addr + EN0_RCNTHI;
addr = (void *)dev->base_addr + EN0_RCNTHI;
switch (dev->if_port) {
case IF_PORT_10BASE2:
......@@ -209,17 +212,19 @@ static int
etherh_getifstat(struct net_device *dev)
{
struct ei_device *ei_local = netdev_priv(dev);
void __iomem *addr;
int stat = 0;
switch (etherh_priv(dev)->id) {
case PROD_I3_ETHERLAN600:
case PROD_I3_ETHERLAN600A:
addr = (void *)dev->base_addr + EN0_RCNTHI;
switch (dev->if_port) {
case IF_PORT_10BASE2:
stat = 1;
break;
case IF_PORT_10BASET:
stat = readb(dev->base_addr+EN0_RCNTHI) & 4;
stat = readb(addr) & 4;
break;
}
break;
......@@ -276,8 +281,9 @@ static void
etherh_reset(struct net_device *dev)
{
struct ei_device *ei_local = netdev_priv(dev);
void __iomem *addr = (void *)dev->base_addr;
writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, dev->base_addr);
writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr);
/*
* See if we need to change the interface type.
......@@ -303,8 +309,8 @@ static void
etherh_block_output (struct net_device *dev, int count, const unsigned char *buf, int start_page)
{
struct ei_device *ei_local = netdev_priv(dev);
unsigned int addr, dma_addr;
unsigned long dma_start;
void __iomem *dma_base, *addr;
if (ei_local->dmaing) {
printk(KERN_ERR "%s: DMAing conflict in etherh_block_input: "
......@@ -321,8 +327,8 @@ etherh_block_output (struct net_device *dev, int count, const unsigned char *buf
ei_local->dmaing = 1;
addr = dev->base_addr;
dma_addr = dev->mem_start;
addr = (void *)dev->base_addr;
dma_base = etherh_priv(dev)->dma_base;
count = (count + 1) & ~1;
writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD);
......@@ -343,9 +349,9 @@ etherh_block_output (struct net_device *dev, int count, const unsigned char *buf
writeb (E8390_RWRITE | E8390_START, addr + E8390_CMD);
if (ei_local->word16)
writesw (dma_addr, buf, count >> 1);
writesw (dma_base, buf, count >> 1);
else
writesb (dma_addr, buf, count);
writesb (dma_base, buf, count);
dma_start = jiffies;
......@@ -369,8 +375,8 @@ static void
etherh_block_input (struct net_device *dev, int count, struct sk_buff *skb, int ring_offset)
{
struct ei_device *ei_local = netdev_priv(dev);
unsigned int addr, dma_addr;
unsigned char *buf;
void __iomem *dma_base, *addr;
if (ei_local->dmaing) {
printk(KERN_ERR "%s: DMAing conflict in etherh_block_input: "
......@@ -381,8 +387,8 @@ etherh_block_input (struct net_device *dev, int count, struct sk_buff *skb, int
ei_local->dmaing = 1;
addr = dev->base_addr;
dma_addr = dev->mem_start;
addr = (void *)dev->base_addr;
dma_base = etherh_priv(dev)->dma_base;
buf = skb->data;
writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD);
......@@ -393,11 +399,11 @@ etherh_block_input (struct net_device *dev, int count, struct sk_buff *skb, int
writeb (E8390_RREAD | E8390_START, addr + E8390_CMD);
if (ei_local->word16) {
readsw (dma_addr, buf, count >> 1);
readsw (dma_base, buf, count >> 1);
if (count & 1)
buf[count - 1] = readb (dma_addr);
buf[count - 1] = readb (dma_base);
} else
readsb (dma_addr, buf, count);
readsb (dma_base, buf, count);
writeb (ENISR_RDC, addr + EN0_ISR);
ei_local->dmaing = 0;
......@@ -410,7 +416,7 @@ static void
etherh_get_header (struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_page)
{
struct ei_device *ei_local = netdev_priv(dev);
unsigned int addr, dma_addr;
void __iomem *dma_base, *addr;
if (ei_local->dmaing) {
printk(KERN_ERR "%s: DMAing conflict in etherh_get_header: "
......@@ -421,8 +427,8 @@ etherh_get_header (struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_p
ei_local->dmaing = 1;
addr = dev->base_addr;
dma_addr = dev->mem_start;
addr = (void *)dev->base_addr;
dma_base = etherh_priv(dev)->dma_base;
writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD);
writeb (sizeof (*hdr), addr + EN0_RCNTLO);
......@@ -432,9 +438,9 @@ etherh_get_header (struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_p
writeb (E8390_RREAD | E8390_START, addr + E8390_CMD);
if (ei_local->word16)
readsw (dma_addr, hdr, sizeof (*hdr) >> 1);
readsw (dma_base, hdr, sizeof (*hdr) >> 1);
else
readsb (dma_addr, hdr, sizeof (*hdr));
readsb (dma_base, hdr, sizeof (*hdr));
writeb (ENISR_RDC, addr + EN0_ISR);
ei_local->dmaing = 0;
......@@ -522,16 +528,30 @@ static int __init etherh_addr(char *addr, struct expansion_card *ec)
struct in_chunk_dir cd;
char *s;
if (ecard_readchunk(&cd, ec, 0xf5, 0) && (s = strchr(cd.d.string, '('))) {
if (!ecard_readchunk(&cd, ec, 0xf5, 0)) {
printk(KERN_ERR "%s: unable to read podule description string\n",
ec->dev.bus_id);
goto no_addr;
}
s = strchr(cd.d.string, '(');
if (s) {
int i;
for (i = 0; i < 6; i++) {
addr[i] = simple_strtoul(s + 1, &s, 0x10);
if (*s != (i == 5? ')' : ':'))
break;
}
if (i == 6)
return 0;
}
printk(KERN_ERR "%s: unable to parse MAC address: %s\n",
ec->dev.bus_id, cd.d.string);
no_addr:
return -ENODEV;
}
......@@ -556,6 +576,62 @@ static int __init etherm_addr(char *addr)
return 0;
}
static void etherh_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
strlcpy(info->version, DRV_VERSION, sizeof(info->version));
strlcpy(info->bus_info, dev->class_dev.dev->bus_id,
sizeof(info->bus_info));
}
static int etherh_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
cmd->supported = etherh_priv(dev)->supported;
cmd->speed = SPEED_10;
cmd->duplex = DUPLEX_HALF;
cmd->port = dev->if_port == IF_PORT_10BASET ? PORT_TP : PORT_BNC;
cmd->autoneg = dev->flags & IFF_AUTOMEDIA ? AUTONEG_ENABLE : AUTONEG_DISABLE;
return 0;
}
static int etherh_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
switch (cmd->autoneg) {
case AUTONEG_ENABLE:
dev->flags |= IFF_AUTOMEDIA;
break;
case AUTONEG_DISABLE:
switch (cmd->port) {
case PORT_TP:
dev->if_port = IF_PORT_10BASET;
break;
case PORT_BNC:
dev->if_port = IF_PORT_10BASE2;
break;
default:
return -EINVAL;
}
dev->flags &= ~IFF_AUTOMEDIA;
break;
default:
return -EINVAL;
}
etherh_setif(dev);
return 0;
}
static struct ethtool_ops etherh_ethtool_ops = {
.get_settings = etherh_get_settings,
.set_settings = etherh_set_settings,
.get_drvinfo = etherh_get_drvinfo,
};
static u32 etherh_regoffsets[16];
static u32 etherm_regoffsets[16];
......@@ -587,10 +663,21 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
dev->stop = etherh_close;
dev->set_config = etherh_set_config;
dev->irq = ec->irq;
dev->if_port = data->if_port;
dev->flags |= data->flags;
dev->ethtool_ops = &etherh_ethtool_ops;
if (data->supported & SUPPORTED_Autoneg)
dev->flags |= IFF_AUTOMEDIA;
if (data->supported & SUPPORTED_TP) {
dev->flags |= IFF_PORTSEL;
dev->if_port = IF_PORT_10BASET;
} else if (data->supported & SUPPORTED_BNC) {
dev->flags |= IFF_PORTSEL;
dev->if_port = IF_PORT_10BASE2;
} else
dev->if_port = IF_PORT_UNKNOWN;
eh = etherh_priv(dev);
eh->supported = data->supported;
eh->ctrl = 0;
eh->id = ec->cid.product;
eh->memc = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), PAGE_SIZE);
......@@ -610,7 +697,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
}
dev->base_addr = (unsigned long)eh->memc + data->ns8390_offset;
dev->mem_start = (unsigned long)eh->memc + data->dataport_offset;
eh->dma_base = eh->memc + data->dataport_offset;
eh->ctrl_port += data->ctrlport_offset;
/*
......@@ -701,7 +788,7 @@ static struct etherh_data etherm_data = {
.dataport_offset = ETHERM_NS8390 + ETHERM_DATAPORT,
.ctrlport_offset = ETHERM_NS8390 + ETHERM_CTRLPORT,
.name = "ANT EtherM",
.if_port = IF_PORT_UNKNOWN,
.supported = SUPPORTED_10baseT_Half,
.tx_start_page = ETHERM_TX_START_PAGE,
.stop_page = ETHERM_STOP_PAGE,
};
......@@ -712,7 +799,7 @@ static struct etherh_data etherlan500_data = {
.ctrlport_offset = ETHERH500_CTRLPORT,
.ctrl_ioc = 1,
.name = "i3 EtherH 500",
.if_port = IF_PORT_UNKNOWN,
.supported = SUPPORTED_10baseT_Half,
.tx_start_page = ETHERH_TX_START_PAGE,
.stop_page = ETHERH_STOP_PAGE,
};
......@@ -722,8 +809,7 @@ static struct etherh_data etherlan600_data = {
.dataport_offset = ETHERH600_NS8390 + ETHERH600_DATAPORT,
.ctrlport_offset = ETHERH600_NS8390 + ETHERH600_CTRLPORT,
.name = "i3 EtherH 600",
.flags = IFF_PORTSEL | IFF_AUTOMEDIA,
.if_port = IF_PORT_10BASET,
.supported = SUPPORTED_10baseT_Half | SUPPORTED_TP | SUPPORTED_BNC | SUPPORTED_Autoneg,
.tx_start_page = ETHERH_TX_START_PAGE,
.stop_page = ETHERH_STOP_PAGE,
};
......@@ -733,8 +819,7 @@ static struct etherh_data etherlan600a_data = {
.dataport_offset = ETHERH600_NS8390 + ETHERH600_DATAPORT,
.ctrlport_offset = ETHERH600_NS8390 + ETHERH600_CTRLPORT,
.name = "i3 EtherH 600A",
.flags = IFF_PORTSEL | IFF_AUTOMEDIA,
.if_port = IF_PORT_10BASET,
.supported = SUPPORTED_10baseT_Half | SUPPORTED_TP | SUPPORTED_BNC | SUPPORTED_Autoneg,
.tx_start_page = ETHERH_TX_START_PAGE,
.stop_page = ETHERH_STOP_PAGE,
};
......@@ -752,7 +837,7 @@ static struct ecard_driver etherh_driver = {
.remove = __devexit_p(etherh_remove),
.id_table = etherh_ids,
.drv = {
.name = "etherh",
.name = DRV_NAME,
},
};
......
......@@ -245,7 +245,7 @@ smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,
while (!(DCSR(dma) & DCSR_STOPSTATE))
cpu_relax();
DCSR(dma) = 0;
dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE);
dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
}
#endif
......@@ -273,7 +273,7 @@ smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma,
}
len *= 2;
dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);
dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
DCSR(dma) = DCSR_NODESC;
DTADR(dma) = dmabuf;
DSADR(dma) = physaddr + reg;
......
......@@ -627,7 +627,7 @@ static void rhine_chip_reset(struct net_device *dev)
}
#ifdef USE_MMIO
static void __devinit enable_mmio(long pioaddr, u32 quirks)
static void enable_mmio(long pioaddr, u32 quirks)
{
int n;
if (quirks & rqRhineI) {
......
......@@ -745,7 +745,7 @@ static struct uart_driver amba_reg = {
static int pl011_probe(struct amba_device *dev, void *id)
{
struct uart_amba_port *uap;
void *base;
void __iomem *base;
int i, ret;
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
......
......@@ -112,6 +112,7 @@ struct stifb_info {
ngle_rom_t ngle_rom;
struct sti_struct *sti;
int deviceSpecificConfig;
u32 pseudo_palette[16];
};
static int __initdata bpp = 8; /* parameter from modprobe */
......@@ -1030,6 +1031,14 @@ stifb_setcolreg(u_int regno, u_int red, u_int green,
/* 0x100 is same as used in WRITE_IMAGE_COLOR() */
START_COLORMAPLOAD(fb, lutBltCtl.all);
SETUP_FB(fb);
/* info->var.bits_per_pixel == 32 */
if (regno < 16)
((u32 *)(info->pseudo_palette))[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
} else {
/* cleanup colormap hardware */
FINISH_IMAGE_COLORMAP_ACCESS(fb);
......@@ -1327,6 +1336,7 @@ stifb_init_fb(struct sti_struct *sti, int force_bpp)
info->screen_base = (void*) REGION_BASE(fb,1);
info->flags = FBINFO_DEFAULT;
info->currcon = -1;
info->pseudo_palette = &fb->pseudo_palette;
/* This has to been done !!! */
fb_alloc_cmap(&info->cmap, 256, 0);
......@@ -1383,6 +1393,7 @@ int __init
stifb_init(void)
{
struct sti_struct *sti;
struct sti_struct *def_sti;
int i;
#ifndef MODULE
......@@ -1397,9 +1408,19 @@ stifb_init(void)
return -ENXIO;
}
def_sti = sti_get_rom(0);
if (def_sti) {
for (i = 1; i < MAX_STI_ROMS; i++) {
sti = sti_get_rom(i);
if (sti == def_sti && bpp > 0)
stifb_force_bpp[i] = bpp;
}
stifb_init_fb(def_sti, stifb_force_bpp[i]);
}
for (i = 1; i < MAX_STI_ROMS; i++) {
sti = sti_get_rom(i);
if (!sti)
if (!sti || sti==def_sti)
break;
if (bpp > 0)
stifb_force_bpp[i] = bpp;
......
......@@ -22,9 +22,9 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
/*
* We don't support ins[lb]/outs[lb]. Make them fault.
......
......@@ -27,13 +27,13 @@ void __outw(u16 val, unsigned int port);
u32 __inl(unsigned int port);
void __outl(u32 val, unsigned int port);
u8 __readb(void *addr);
u16 __readw(void *addr);
u32 __readl(void *addr);
u8 __readb(void __iomem *addr);
u16 __readw(void __iomem *addr);
u32 __readl(void __iomem *addr);
void __writeb(u8 val, void *addr);
void __writew(u16 val, void *addr);
void __writel(u32 val, void *addr);
void __writeb(u8 val, void __iomem *addr);
void __writew(u16 val, void __iomem *addr);
void __writel(u32 val, void __iomem *addr);
/*
* Argh, someone forgot the IOCS16 line. We therefore have to handle
......@@ -64,7 +64,7 @@ void __writel(u32 val, void *addr);
#define writew(v,b) __writew(v,b)
#define writel(v,b) __writel(v,b)
#define __arch_ioremap(cookie,sz,c,a) ((void *)(cookie))
#define __arch_ioremap(cookie,sz,c,a) ((void __iomem *)(cookie))
#define __arch_iounmap(cookie) do { } while (0)
extern void insb(unsigned int port, void *buf, int sz);
......
......@@ -19,25 +19,27 @@
/*
* Translation of various region addresses to virtual addresses
*/
#define __io(a) (PCIO_BASE + (a))
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#if 1
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) (PCIMEM_BASE + (unsigned long)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) ((a) + PCIMEM_BASE)
#else
static inline unsigned long ___mem_pci(unsigned long a)
static inline void __iomem *___mem_pci(void __iomem *p)
{
unsigned long a = (unsigned long)p;
BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
return a;
return p;
}
static inline unsigned long ___mem_isa(unsigned long a)
static inline void __iomem *___mem_isa(void __iomem *p)
{
unsigned long a = (unsigned long)p;
BUG_ON(a >= 16*1048576);
return PCIMEM_BASE + a;
return p + PCIMEM_BASE;
}
#define __mem_pci(a) ___mem_pci((unsigned long)(a))
#define __mem_isa(a) ___mem_isa((unsigned long)(a))
#define __mem_pci(a) ___mem_pci(a)
#define __mem_isa(a) ___mem_isa(a)
#endif
#endif
......@@ -33,7 +33,7 @@
#define insw __arch_readsw
#define insl __arch_readsl*/
#define __io(a) (a)
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif
......@@ -18,7 +18,7 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) (a)
#define __mem_pci(a) (a)
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif
......@@ -22,7 +22,7 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) (a)
#define __mem_pci(a) (a)
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif
......@@ -22,8 +22,8 @@
#define IO_SPACE_LIMIT 0xffff
#define __io(a) (PCI_IO_VADDR + (a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) (PCI_MEMORY_VADDR + (unsigned long)(a))
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
#endif
......@@ -13,8 +13,8 @@
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((p))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(p) ((void __iomem *)(p))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif
......@@ -16,7 +16,7 @@
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_pci(a) (a)
/*
* Pick up VMALLOC_END
......
......@@ -46,7 +46,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
*/
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_pci(a) (a)
#else
......@@ -58,10 +58,10 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
* access registers. If something outside of PCI is ioremap'd, we
* fallback to the default.
*/
static inline void *
static inline void __iomem *
__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
{
extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
if((addr < 0x48000000) || (addr > 0x4fffffff))
return __ioremap(addr, size, flags, align);
......@@ -69,9 +69,9 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned
}
static inline void
__ixp4xx_iounmap(void *addr)
__ixp4xx_iounmap(void __iomem *addr)
{
extern void __iounmap(void *addr);
extern void __iounmap(void __iomem *addr);
if ((u32)addr >= VMALLOC_START)
__iounmap(addr);
......
......@@ -17,9 +17,9 @@
/*
* There are not real ISA nor PCI buses, so we fake it.
*/
#define __io_pci(a) (PCIO_BASE + (a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#define __ioaddr(p) __io_pci(p)
......
......@@ -14,8 +14,8 @@
#define IO_SPACE_LIMIT 0xffffffff
/* No ISA or PCI bus on this machine. */
#define __io(a) (a)
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif /* __ASM_ARCH_IO_H */
......@@ -40,9 +40,9 @@
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) (PCIO_BASE + (a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
/*
* ----------------------------------------------------------------------------
......
......@@ -12,8 +12,8 @@
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) (a)
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif
......@@ -250,6 +250,6 @@ DECLARE_IO(int,l,"")
/*
* 1:1 mapping for ioremapped regions.
*/
#define __mem_pci(x) ((unsigned long)(x))
#define __mem_pci(x) (x)
#endif
......@@ -198,7 +198,7 @@ struct s3c2410_dma_chan_s {
unsigned int flags; /* channel flags */
/* channel's hardware position and configuration */
unsigned long regs; /* channels registers */
void __iomem *regs; /* channels registers */
unsigned int irq; /* channel irq */
unsigned long addr_reg; /* data address register */
unsigned long dcon; /* default value of DCON */
......
......@@ -16,8 +16,8 @@
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) (PCIO_BASE + (a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif
......@@ -170,7 +170,7 @@ DECLARE_IO(long,l,"")
addr; \
})
#define __mem_pci(addr) addr
#define __mem_pci(addr) (addr)
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
......
......@@ -22,8 +22,8 @@
#define IO_SPACE_LIMIT 0xffff
#define __io(a) ((a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif
......@@ -141,7 +141,7 @@ struct clcd_fb {
struct clcd_panel *panel;
struct clcd_board *board;
void *board_data;
void *regs;
void __iomem *regs;
u32 clcd_cntl;
u32 cmap[16];
};
......
......@@ -39,21 +39,21 @@
* Generic IO read/write. These perform native-endian accesses. Note
* that some architectures will want to re-define __raw_{read,write}w.
*/
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
extern void __raw_readsb(void __iomem *addr, void *data, int bytelen);
extern void __raw_readsw(void __iomem *addr, void *data, int wordlen);
extern void __raw_readsl(void __iomem *addr, void *data, int longlen);
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_writeb(v,a) (*(volatile unsigned char __force *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short __force *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int __force *)(a) = (v))
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define __raw_readb(a) (*(volatile unsigned char __force *)(a))
#define __raw_readw(a) (*(volatile unsigned short __force *)(a))
#define __raw_readl(a) (*(volatile unsigned int __force *)(a))
/*
* Bad read/write accesses...
......@@ -156,17 +156,17 @@ extern void _memset_io(void __iomem *, int, size_t);
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define readsb(p,d,l) __raw_readsb((unsigned int)__mem_pci(p),d,l)
#define readsw(p,d,l) __raw_readsw((unsigned int)__mem_pci(p),d,l)
#define readsl(p,d,l) __raw_readsl((unsigned int)__mem_pci(p),d,l)
#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
#define writesb(p,d,l) __raw_writesb((unsigned int)__mem_pci(p),d,l)
#define writesw(p,d,l) __raw_writesw((unsigned int)__mem_pci(p),d,l)
#define writesl(p,d,l) __raw_writesl((unsigned int)__mem_pci(p),d,l)
#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
......@@ -268,8 +268,8 @@ isa_check_signature(unsigned long io_addr, const unsigned char *signature,
* ioremap takes a PCI memory address, as specified in
* Documentation/IO-mapping.txt.
*/
extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
extern void __iounmap(void *addr);
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
extern void __iounmap(void __iomem *addr);
#ifndef __arch_ioremap
#define ioremap(cookie,size) __ioremap(cookie,size,0,1)
......
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