Merge bk://gkernel.bkbits.net/libata-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Documentation/kernel-parameters.txt

@@ -53,6 +53,7 @@ restrictions referred to are that the relevant option is valid if:
 	NFS	Appropriate NFS support is enabled.
 	OSS	OSS sound support is enabled.
 	PARIDE	The ParIDE subsystem is enabled.
+	PARISC	The PA-RISC architecture is enabled.
 	PCI	PCI bus support is enabled.
 	PCMCIA	The PCMCIA subsystem is enabled.
 	PNP	Plug & Play support is enabled.
@@ -394,7 +395,7 @@ running once the system is up.
 	eicon=		[HW,ISDN] 
 			Format: <id>,<membase>,<irq>
 
-	eisa_irq_edge=	[PARISC]
+	eisa_irq_edge=	[PARISC,HW]
 			See header of drivers/parisc/eisa.c.
 
 	elanfreq=	[IA-32]
@@ -933,6 +934,11 @@ running once the system is up.
 	pd.		[PARIDE]
 			See Documentation/paride.txt.
 
+	pdcchassis=	[PARISC,HW] Disable/Enable PDC Chassis Status codes at
+			boot time.
+			Format: { 0 | 1 }
+			See arch/parisc/kernel/pdc_chassis.c
+
 	pf.		[PARIDE]
 			See Documentation/paride.txt.
 
@@ -1250,7 +1256,7 @@ running once the system is up.
 	st0x=		[HW,SCSI]
 			See header of drivers/scsi/seagate.c.
 
-	sti=		[HW]
+	sti=		[PARISC,HW]
 			Format: <num>
 			Set the STI (builtin display/keyboard on the HP-PARISC
 			machines) console (graphic card) which should be used

MAINTAINERS

@@ -1110,8 +1110,8 @@ P:	John Ronciak
 M:	john.ronciak@intel.com
 P:	Ganesh Venkatesan
 M:	ganesh.venkatesan@intel.com
-P:	Scott Feldman
-M:	scott.feldman@intel.com
+P:	Jesse Brandeburg
+M:	jesse.brandeburg@intel.com
 W:	http://sourceforge.net/projects/e1000/
 S:	Supported
 

arch/arm/common/amba.c

@@ -194,7 +194,7 @@ amba_attr(resource, "\t%08lx\t%08lx\t%08lx\n",
 int amba_device_register(struct amba_device *dev, struct resource *parent)
 {
 	u32 pid, cid;
-	void *tmp;
+	void __iomem *tmp;
 	int i, ret;
 
 	dev->dev.release = amba_device_release;

arch/arm/mach-ebsa110/io.c

@@ -27,9 +27,9 @@
 #include <asm/io.h>
 #include <asm/page.h>
 
-static u32 __isamem_convert_addr(void *addr)
+static void __iomem *__isamem_convert_addr(void __iomem *addr)
 {
-	u32 ret, a = (u32) addr;
+	u32 ret, a = (u32 __force) addr;
 
 	/*
 	 * The PCMCIA controller is wired up as follows:
@@ -53,41 +53,43 @@ static u32 __isamem_convert_addr(void *addr)
 	ret += 0xe8000000;
 
 	if ((a & 0x20000) == (a & 0x40000) >> 1)
-		return ret;
+		return (void __iomem *)ret;
 
 	BUG();
-	return 0;
+	return NULL;
 }
 
 /*
  * read[bwl] and write[bwl]
  */
-u8 __readb(void *addr)
+u8 __readb(void __iomem *addr)
 {
-	u32 ret, a = __isamem_convert_addr(addr);
+	void __iomem *a = __isamem_convert_addr(addr);
+	u32 ret;
 
-	if ((int)addr & 1)
+	if ((unsigned long)addr & 1)
 		ret = __raw_readl(a);
 	else
 		ret = __raw_readb(a);
 	return ret;
 }
 
-u16 __readw(void *addr)
+u16 __readw(void __iomem *addr)
 {
-	u32 a = __isamem_convert_addr(addr);
+	void __iomem *a = __isamem_convert_addr(addr);
 
-	if ((int)addr & 1)
+	if ((unsigned long)addr & 1)
 		BUG();
 
 	return __raw_readw(a);
 }
 
-u32 __readl(void *addr)
+u32 __readl(void __iomem *addr)
 {
-	u32 ret, a = __isamem_convert_addr(addr);
+	void __iomem *a = __isamem_convert_addr(addr);
+	u32 ret;
 
-	if ((int)addr & 3)
+	if ((unsigned long)addr & 3)
 		BUG();
 
 	ret = __raw_readw(a);
@@ -99,31 +101,31 @@ EXPORT_SYMBOL(__readb);
 EXPORT_SYMBOL(__readw);
 EXPORT_SYMBOL(__readl);
 
-void __writeb(u8 val, void *addr)
+void __writeb(u8 val, void __iomem *addr)
 {
-	u32 a = __isamem_convert_addr(addr);
+	void __iomem *a = __isamem_convert_addr(addr);
 
-	if ((int)addr & 1)
+	if ((unsigned long)addr & 1)
 		__raw_writel(val, a);
 	else
 		__raw_writeb(val, a);
 }
 
-void __writew(u16 val, void *addr)
+void __writew(u16 val, void __iomem *addr)
 {
-	u32 a = __isamem_convert_addr(addr);
+	void __iomem *a = __isamem_convert_addr(addr);
 
-	if ((int)addr & 1)
+	if ((unsigned long)addr & 1)
 		BUG();
 
 	__raw_writew(val, a);
 }
 
-void __writel(u32 val, void *addr)
+void __writel(u32 val, void __iomem *addr)
 {
-	u32 a = __isamem_convert_addr(addr);
+	void __iomem *a = __isamem_convert_addr(addr);
 
-	if ((int)addr & 3)
+	if ((unsigned long)addr & 3)
 		BUG();
 
 	__raw_writew(val, a);
@@ -153,7 +155,7 @@ u8 __inb8(unsigned int port)
 	if (SUPERIO_PORT(port))
 		ret = __raw_readb(ISAIO_BASE + (port << 2));
 	else {
-		u32 a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
@@ -180,7 +182,7 @@ u8 __inb16(unsigned int port)
 	if (SUPERIO_PORT(port))
 		ret = __raw_readb(ISAIO_BASE + (port << 2));
 	else {
-		u32 a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
@@ -200,7 +202,7 @@ u16 __inw(unsigned int port)
 	if (SUPERIO_PORT(port))
 		ret = __raw_readw(ISAIO_BASE + (port << 2));
 	else {
-		u32 a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
@@ -218,7 +220,7 @@ u16 __inw(unsigned int port)
  */
 u32 __inl(unsigned int port)
 {
-	u32 a;
+	void __iomem *a;
 
 	if (SUPERIO_PORT(port) || port & 3)
 		BUG();
@@ -241,7 +243,7 @@ void __outb8(u8 val, unsigned int port)
 	if (SUPERIO_PORT(port))
 		__raw_writeb(val, ISAIO_BASE + (port << 2));
 	else {
-		u32 a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does
@@ -261,7 +263,7 @@ void __outb16(u8 val, unsigned int port)
 	if (SUPERIO_PORT(port))
 		__raw_writeb(val, ISAIO_BASE + (port << 2));
 	else {
-		u32 a = ISAIO_BASE + ((port & ~1) << 1);
+		void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
 
 		/*
 		 * Shame nothing else does

arch/arm/mach-s3c2410/dma.c

@@ -52,7 +52,7 @@
 #include <asm/arch/map.h>
 
 /* io map for dma */
-static void *dma_base;
+static void __iomem *dma_base;
 
 /* dma channel state information */
 s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];
@@ -1065,7 +1065,7 @@ static int __init s3c2410_init_dma(void)
 		/* dma channel irqs are in order.. */
 		cp->number = channel;
 		cp->irq    = channel + IRQ_DMA0;
-		cp->regs   = (unsigned long)dma_base + (channel*0x40);
+		cp->regs   = dma_base + (channel*0x40);
 
 		/* point current stats somewhere */
 		cp->stats  = &cp->stats_store;
@@ -1075,7 +1075,7 @@ static int __init s3c2410_init_dma(void)
 
 		cp->load_timeout = 1<<18;
 
-		printk("DMA channel %d at %08lx, irq %d\n",
+		printk("DMA channel %d at %p, irq %d\n",
 		       cp->number, cp->regs, cp->irq);
 	}
 

arch/arm/mm/ioremap.c

@@ -130,7 +130,7 @@ remap_area_pages(unsigned long start, unsigned long phys_addr,
  * 'flags' are the extra L_PTE_ flags that you want to specify for this
  * mapping.  See include/asm-arm/proc-armv/pgtable.h for more information.
  */
-void *
+void __iomem *
 __ioremap(unsigned long phys_addr, size_t size, unsigned long flags,
 	  unsigned long align)
 {
@@ -161,11 +161,11 @@ __ioremap(unsigned long phys_addr, size_t size, unsigned long flags,
 		vfree(addr);
 		return NULL;
 	}
-	return (void *) (offset + (char *)addr);
+	return (void __iomem *) (offset + (char *)addr);
 }
 EXPORT_SYMBOL(__ioremap);
 
-void __iounmap(void *addr)
+void __iounmap(void __iomem *addr)
 {
 	vfree((void *) (PAGE_MASK & (unsigned long) addr));
 }

drivers/mmc/mmci.c

@@ -69,7 +69,7 @@ static void mmci_stop_data(struct mmci_host *host)
 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 {
 	unsigned int datactrl, timeout, irqmask;
-	void *base;
+	void __iomem *base;
 
 	DBG(host, "blksz %04x blks %04x flags %08x\n",
 	    1 << data->blksz_bits, data->blocks, data->flags);
@@ -108,7 +108,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 static void
 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 {
-	void *base = host->base;
+	void __iomem *base = host->base;
 
 	DBG(host, "op %02x arg %08x flags %08x\n",
 	    cmd->opcode, cmd->arg, cmd->flags);
@@ -169,7 +169,7 @@ static void
 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 	     unsigned int status)
 {
-	void *base = host->base;
+	void __iomem *base = host->base;
 
 	host->cmd = NULL;
 
@@ -193,7 +193,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 
 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
 {
-	void *base = host->base;
+	void __iomem *base = host->base;
 	char *ptr = buffer;
 	u32 status;
 
@@ -222,7 +222,7 @@ static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int rema
 
 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
 {
-	void *base = host->base;
+	void __iomem *base = host->base;
 	char *ptr = buffer;
 
 	do {
@@ -251,7 +251,7 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
 static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct mmci_host *host = dev_id;
-	void *base = host->base;
+	void __iomem *base = host->base;
 	u32 status;
 
 	status = readl(base + MMCISTATUS);

drivers/mmc/mmci.h

@@ -120,7 +120,7 @@
 struct clk;
 
 struct mmci_host {
-	void			*base;
+	void __iomem		*base;
 	struct mmc_request	*mrq;
 	struct mmc_command	*cmd;
 	struct mmc_data		*data;

drivers/net/8390.c

@@ -813,7 +813,7 @@ static void ei_rx_overrun(struct net_device *dev)
 	 * We wait at least 10ms.
 	 */
 
-	udelay(10*1000);
+	mdelay(10);
 
 	/*
 	 * Reset RBCR[01] back to zero as per magic incantation.

drivers/net/amd8111e.c

@@ -211,7 +211,7 @@ static void amd8111e_set_ext_phy(struct net_device *dev)
 	u32 bmcr,advert,tmp;
 	
 	/* Determine mii register values to set the speed */
-	advert = amd8111e_mdio_read(dev, PHY_ID, MII_ADVERTISE);
+	advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
 	tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 	switch (lp->ext_phy_option){
 
@@ -235,11 +235,11 @@ static void amd8111e_set_ext_phy(struct net_device *dev)
 	}
 
 	if(advert != tmp)
-		amd8111e_mdio_write(dev, PHY_ID, MII_ADVERTISE, tmp);
+		amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
 	/* Restart auto negotiation */
-	bmcr = amd8111e_mdio_read(dev, PHY_ID, MII_BMCR);
+	bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
 	bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
-	amd8111e_mdio_write(dev, PHY_ID, MII_BMCR, bmcr);
+	amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
 
 }
 
@@ -350,6 +350,7 @@ static int amd8111e_init_ring(struct net_device *dev)
 
 		lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
 		lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
+		wmb();
 		lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
 	}
 
@@ -529,7 +530,7 @@ static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
 	writel(RUN, mmio + CMD0);
 
 	/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
-	writew( 0x8101, mmio + AUTOPOLL0);
+	writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
 
 	/* Clear RCV_RING_BASE_ADDR */
 	writel(0, mmio + RCV_RING_BASE_ADDR0);
@@ -740,11 +741,11 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
 	do{   
 		/* process receive packets until we use the quota*/
 		/* If we own the next entry, it's a new packet. Send it up. */
-		while(!(lp->rx_ring[rx_index].rx_flags & OWN_BIT)){
+		while(1) {
+			status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
+			if (status & OWN_BIT)
+				break;
 
-			/* check if err summary bit is set */ 
-			if(le16_to_cpu(lp->rx_ring[rx_index].rx_flags) 
-								& ERR_BIT){
 			/* 
 			 * There is a tricky error noted by John Murphy,
 			 * <murf@perftech.com> to Russ Nelson: Even with
@@ -753,22 +754,21 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
 			 * the last correctly noting the error.
 			 */
 
+			if(status & ERR_BIT) {
 				/* reseting flags */
-			lp->rx_ring[rx_index].rx_flags &=RESET_RX_FLAGS;
+				lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 				goto err_next_pkt;
-
 			}
 			/* check for STP and ENP */
-		status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 			if(!((status & STP_BIT) && (status & ENP_BIT))){
 				/* reseting flags */
-			lp->rx_ring[rx_index].rx_flags &=RESET_RX_FLAGS;
+				lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 				goto err_next_pkt;
 			}
 			pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 
 #if AMD8111E_VLAN_TAG_USED		
-		vtag = le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & TT_MASK;
+			vtag = status & TT_MASK;
 			/*MAC will strip vlan tag*/ 
 			if(lp->vlgrp != NULL && vtag !=0)
 				min_pkt_len =MIN_PKT_LEN - 4;
@@ -800,19 +800,18 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
 			lp->rx_skbuff[rx_index] = new_skb;
 			new_skb->dev = dev;
 			lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
-			new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
+								   new_skb->data,
+								   lp->rx_buff_len-2,
+								   PCI_DMA_FROMDEVICE);
 	
 			skb->protocol = eth_type_trans(skb, dev);
 
 #if AMD8111E_VLAN_TAG_USED		
-		
-		vtag = lp->rx_ring[rx_index].rx_flags & TT_MASK;
 			if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
 				amd8111e_vlan_rx(lp, skb,
-				    lp->rx_ring[rx_index].tag_ctrl_info);
+					 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
 			} else
 #endif
-			
 				netif_receive_skb(skb);
 			/*COAL update rx coalescing parameters*/
 			lp->coal_conf.rx_packets++;
@@ -820,11 +819,12 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
 			num_rx_pkt++;
 			dev->last_rx = jiffies;
 	
-err_next_pkt:	
+		err_next_pkt:	
 			lp->rx_ring[rx_index].buff_phy_addr
 				= cpu_to_le32(lp->rx_dma_addr[rx_index]);
 			lp->rx_ring[rx_index].buff_count = 
 				cpu_to_le16(lp->rx_buff_len-2);
+			wmb();
 			lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 			rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 		}
@@ -835,7 +835,7 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
 		/*Ack receive packets */
 		writel(intr0 & RINT0,mmio + INT0);
 
-	}while(intr0 & RINT0);
+	} while(intr0 & RINT0);
 
 	/* Receive descriptor is empty now */
 	dev->quota -= num_rx_pkt;
@@ -873,11 +873,12 @@ static int amd8111e_rx(struct net_device *dev)
 	
 	/* If we own the next entry, it's a new packet. Send it up. */
 	while(++num_rx_pkt <= max_rx_pkt){
-		if(lp->rx_ring[rx_index].rx_flags & OWN_BIT)
+		status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
+		if(status & OWN_BIT)
 			return 0;
 	       
 		/* check if err summary bit is set */ 
-		if(le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & ERR_BIT){
+		if(status & ERR_BIT){
 			/* 
 			 * There is a tricky error noted by John Murphy,
 			 * <murf@perftech.com> to Russ Nelson: Even with full-sized
@@ -888,7 +889,6 @@ static int amd8111e_rx(struct net_device *dev)
 			goto err_next_pkt;
 		}
 		/* check for STP and ENP */
-		status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 		if(!((status & STP_BIT) && (status & ENP_BIT))){
 			/* reseting flags */
 			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
@@ -897,7 +897,7 @@ static int amd8111e_rx(struct net_device *dev)
 		pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 
 #if AMD8111E_VLAN_TAG_USED		
-		vtag = le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & TT_MASK;
+		vtag = status & TT_MASK;
 		/*MAC will strip vlan tag*/ 
 		if(lp->vlgrp != NULL && vtag !=0)
 			min_pkt_len =MIN_PKT_LEN - 4;
@@ -932,11 +932,9 @@ static int amd8111e_rx(struct net_device *dev)
 		skb->protocol = eth_type_trans(skb, dev);
 
 #if AMD8111E_VLAN_TAG_USED				
-		
-		vtag = lp->rx_ring[rx_index].rx_flags & TT_MASK;
 		if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
 			amd8111e_vlan_rx(lp, skb,
-				    lp->rx_ring[rx_index].tag_ctrl_info);
+				 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
 		} else
 #endif
 			
@@ -952,6 +950,7 @@ static int amd8111e_rx(struct net_device *dev)
 			 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
 		lp->rx_ring[rx_index].buff_count = 
 				cpu_to_le16(lp->rx_buff_len-2);
+		wmb();
 		lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 		rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 	}
@@ -1432,7 +1431,7 @@ static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
 #if AMD8111E_VLAN_TAG_USED
 	if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
 		lp->tx_ring[tx_index].tag_ctrl_cmd |= 
-				cpu_to_le32(TCC_VLAN_INSERT);	
+				cpu_to_le16(TCC_VLAN_INSERT);	
 		lp->tx_ring[tx_index].tag_ctrl_info = 
 				cpu_to_le16(vlan_tx_tag_get(skb));
 
@@ -1444,6 +1443,7 @@ static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
 	    (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
 
 	/*  Set FCS and LTINT bits */
+	wmb();
 	lp->tx_ring[tx_index].tx_flags |=
 	    cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
 
@@ -1667,7 +1667,7 @@ static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
 
 	switch(cmd) {
 	case SIOCGMIIPHY:
-		data->phy_id = PHY_ID;
+		data->phy_id = lp->ext_phy_addr;
 
 	/* fallthru */
 	case SIOCGMIIREG: 
@@ -1940,6 +1940,26 @@ static void amd8111e_config_ipg(struct net_device* dev)
 
 }
 
+static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
+{
+	struct amd8111e_priv *lp = netdev_priv(dev);
+	int i;
+
+	for (i = 0x1e; i >= 0; i--) {
+		u32 id1, id2;
+
+		if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
+			continue;
+		if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
+			continue;
+		lp->ext_phy_id = (id1 << 16) | id2;
+		lp->ext_phy_addr = i;
+		return;
+	}
+	lp->ext_phy_id = 0;
+	lp->ext_phy_addr = 1;
+}
+
 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
 				  const struct pci_device_id *ent)
 {
@@ -2010,12 +2030,6 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
 	lp->amd8111e_net_dev = dev;
 	lp->pm_cap = pm_cap;
 
-	/* setting mii default values */
-	lp->mii_if.dev = dev;
-	lp->mii_if.mdio_read = amd8111e_mdio_read;
-	lp->mii_if.mdio_write = amd8111e_mdio_write;
-	lp->mii_if.phy_id = PHY_ID;
-
 	spin_lock_init(&lp->lock);
 
 	lp->mmio = ioremap(reg_addr, reg_len);
@@ -2063,6 +2077,14 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
 	dev->vlan_rx_register =amd8111e_vlan_rx_register;
 	dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
 #endif	
+	/* Probe the external PHY */
+	amd8111e_probe_ext_phy(dev);
+
+	/* setting mii default values */
+	lp->mii_if.dev = dev;
+	lp->mii_if.mdio_read = amd8111e_mdio_read;
+	lp->mii_if.mdio_write = amd8111e_mdio_write;
+	lp->mii_if.phy_id = lp->ext_phy_addr;
 
 	/* Set receive buffer length and set jumbo option*/
 	amd8111e_set_rx_buff_len(dev);
@@ -2096,6 +2118,12 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
     	for (i = 0; i < 6; i++)
 		printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
     	printk( "\n");	
+	if (lp->ext_phy_id)
+		printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
+		       dev->name, lp->ext_phy_id, lp->ext_phy_addr);
+	else
+		printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
+		       dev->name);
     	return 0;
 err_iounmap:
 	iounmap(lp->mmio);

drivers/net/amd8111e.h

@@ -649,7 +649,6 @@ typedef enum {
 #define TCC_MASK		0x0003
 
 /* driver ioctl parameters */
-#define PHY_ID 			0x01	/* currently it is fixed */
 #define AMD8111E_REG_DUMP_LEN	 13*sizeof(u32) 
 
 /* crc generator constants */
@@ -777,6 +776,8 @@ struct amd8111e_priv{
 	int options;		/* Options enabled/disabled for the device */
 
 	unsigned long ext_phy_option;
+	int ext_phy_addr;
+	u32 ext_phy_id;
 	
 	struct amd8111e_link_config link_config;
 	int pm_cap;

drivers/net/smc91x.h

@@ -245,7 +245,7 @@ smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,
 	while (!(DCSR(dma) & DCSR_STOPSTATE))
 		cpu_relax();
 	DCSR(dma) = 0;
-	dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE);
+	dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
 }
 #endif
 
@@ -273,7 +273,7 @@ smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma,
 	}
 
 	len *= 2;
-	dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);
+	dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
 	DCSR(dma) = DCSR_NODESC;
 	DTADR(dma) = dmabuf;
 	DSADR(dma) = physaddr + reg;

drivers/net/via-rhine.c

@@ -627,7 +627,7 @@ static void rhine_chip_reset(struct net_device *dev)
 }
 
 #ifdef USE_MMIO
-static void __devinit enable_mmio(long pioaddr, u32 quirks)
+static void enable_mmio(long pioaddr, u32 quirks)
 {
 	int n;
 	if (quirks & rqRhineI) {

drivers/serial/amba-pl011.c

@@ -745,7 +745,7 @@ static struct uart_driver amba_reg = {
 static int pl011_probe(struct amba_device *dev, void *id)
 {
 	struct uart_amba_port *uap;
-	void *base;
+	void __iomem *base;
 	int i, ret;
 
 	for (i = 0; i < ARRAY_SIZE(amba_ports); i++)

drivers/video/stifb.c

@@ -112,6 +112,7 @@ struct stifb_info {
 	ngle_rom_t ngle_rom;
 	struct sti_struct *sti;
 	int deviceSpecificConfig;
+	u32 pseudo_palette[16];
 };
 
 static int __initdata bpp = 8;	/* parameter from modprobe */
@@ -1030,6 +1031,14 @@ stifb_setcolreg(u_int regno, u_int red, u_int green,
 				/* 0x100 is same as used in WRITE_IMAGE_COLOR() */
 		START_COLORMAPLOAD(fb, lutBltCtl.all);
 		SETUP_FB(fb);
+
+		/* info->var.bits_per_pixel == 32 */
+		if (regno < 16) 
+		  ((u32 *)(info->pseudo_palette))[regno] =
+			(red   << info->var.red.offset)   |
+			(green << info->var.green.offset) |
+			(blue  << info->var.blue.offset);
+
 	} else {
 		/* cleanup colormap hardware */
 		FINISH_IMAGE_COLORMAP_ACCESS(fb);
@@ -1327,6 +1336,7 @@ stifb_init_fb(struct sti_struct *sti, int force_bpp)
 	info->screen_base = (void*) REGION_BASE(fb,1);
 	info->flags = FBINFO_DEFAULT;
 	info->currcon = -1;
+	info->pseudo_palette = &fb->pseudo_palette;
 
 	/* This has to been done !!! */
 	fb_alloc_cmap(&info->cmap, 256, 0);
@@ -1383,6 +1393,7 @@ int __init
 stifb_init(void)
 {
 	struct sti_struct *sti;
+	struct sti_struct *def_sti;
 	int i;
 	
 #ifndef MODULE
@@ -1397,9 +1408,19 @@ stifb_init(void)
 		return -ENXIO;
 	}
 	
+	def_sti = sti_get_rom(0);
+	if (def_sti) {
 		for (i = 1; i < MAX_STI_ROMS; i++) {
 			sti = sti_get_rom(i);
-		if (!sti)
+			if (sti == def_sti && bpp > 0)
+				stifb_force_bpp[i] = bpp;
+		}
+		stifb_init_fb(def_sti, stifb_force_bpp[i]);
+	}
+
+	for (i = 1; i < MAX_STI_ROMS; i++) {
+		sti = sti_get_rom(i);
+		if (!sti || sti==def_sti)
 			break;
 		if (bpp > 0)
 			stifb_force_bpp[i] = bpp;

include/asm-arm/arch-clps711x/io.h

@@ -22,9 +22,9 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __io(a)			((a))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(a)			((void __iomem *)(a))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 /*
  * We don't support ins[lb]/outs[lb].  Make them fault.

include/asm-arm/arch-ebsa110/io.h

@@ -27,13 +27,13 @@ void __outw(u16 val, unsigned int port);
 u32 __inl(unsigned int port);
 void __outl(u32 val, unsigned int port);
 
-u8  __readb(void *addr);
-u16 __readw(void *addr);
-u32 __readl(void *addr);
+u8  __readb(void __iomem *addr);
+u16 __readw(void __iomem *addr);
+u32 __readl(void __iomem *addr);
 
-void __writeb(u8  val, void *addr);
-void __writew(u16 val, void *addr);
-void __writel(u32 val, void *addr);
+void __writeb(u8  val, void __iomem *addr);
+void __writew(u16 val, void __iomem *addr);
+void __writel(u32 val, void __iomem *addr);
 
 /*
  * Argh, someone forgot the IOCS16 line.  We therefore have to handle
@@ -64,7 +64,7 @@ void __writel(u32 val, void *addr);
 #define writew(v,b)		__writew(v,b)
 #define writel(v,b)		__writel(v,b)
 
-#define __arch_ioremap(cookie,sz,c,a)	((void *)(cookie))
+#define __arch_ioremap(cookie,sz,c,a)	((void __iomem *)(cookie))
 #define __arch_iounmap(cookie)		do { } while (0)
 
 extern void insb(unsigned int port, void *buf, int sz);

include/asm-arm/arch-ebsa285/io.h

@@ -19,25 +19,27 @@
 /*
  * Translation of various region addresses to virtual addresses
  */
-#define __io(a)			(PCIO_BASE + (a))
+#define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
 #if 1
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		(PCIMEM_BASE + (unsigned long)(a))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		((a) + PCIMEM_BASE)
 #else
 
-static inline unsigned long ___mem_pci(unsigned long a)
+static inline void __iomem *___mem_pci(void __iomem *p)
 {
+	unsigned long a = (unsigned long)p;
 	BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
-	return a;
+	return p;
 }
 
-static inline unsigned long ___mem_isa(unsigned long a)
+static inline void __iomem *___mem_isa(void __iomem *p)
 {
+	unsigned long a = (unsigned long)p;
 	BUG_ON(a >= 16*1048576);
-	return PCIMEM_BASE + a;
+	return p + PCIMEM_BASE;
 }
-#define __mem_pci(a)		___mem_pci((unsigned long)(a))
-#define __mem_isa(a)		___mem_isa((unsigned long)(a))
+#define __mem_pci(a)		___mem_pci(a)
+#define __mem_isa(a)		___mem_isa(a)
 #endif
 
 #endif

include/asm-arm/arch-epxa10db/io.h

@@ -33,7 +33,7 @@
 #define insw    __arch_readsw
 #define insl    __arch_readsl*/
 
-#define __io(a)			(a)
+#define __io(a)			((void __iomem *)(a))
 #define __mem_pci(a)            (a) 
 
 #endif

include/asm-arm/arch-h720x/io.h

@@ -18,7 +18,7 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __io(a) (a)
+#define __io(a)		((void __iomem *)(a))
 #define __mem_pci(a)	(a)
 
 #endif

include/asm-arm/arch-imx/io.h

@@ -22,7 +22,7 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __io(a)       (a)
+#define __io(a)		((void __iomem *)(a))
 #define __mem_pci(a)	(a)
 
 #endif

include/asm-arm/arch-integrator/io.h

@@ -22,8 +22,8 @@
 
 #define IO_SPACE_LIMIT 0xffff
 
-#define __io(a)			(PCI_IO_VADDR + (a))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		(PCI_MEMORY_VADDR + (unsigned long)(a))
+#define __io(a)			((void __iomem *)(PCI_IO_VADDR + (a)))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		((a) + PCI_MEMORY_VADDR)
 
 #endif

include/asm-arm/arch-iop3xx/io.h

@@ -13,8 +13,8 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __io(p)			((p))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(p)			((void __iomem *)(p))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 #endif

include/asm-arm/arch-ixp2000/io.h

@@ -16,7 +16,7 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define IO_SPACE_LIMIT		0xffffffff
-#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_pci(a)		(a)
 
 /*
  * Pick up VMALLOC_END

include/asm-arm/arch-ixp4xx/io.h

@@ -46,7 +46,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  */
 #ifndef	CONFIG_IXP4XX_INDIRECT_PCI
 
-#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_pci(a)		(a)
 
 #else
 
@@ -58,10 +58,10 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  * access registers. If something outside of PCI is ioremap'd, we
  * fallback to the default.
  */
-static inline void *
+static inline void __iomem *
 __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
 {
-	extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
+	extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
 	if((addr < 0x48000000) || (addr > 0x4fffffff))
 		return __ioremap(addr, size, flags, align);
 
@@ -69,9 +69,9 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned
 }
 
 static inline void
-__ixp4xx_iounmap(void *addr)
+__ixp4xx_iounmap(void __iomem *addr)
 {
-	extern void __iounmap(void *addr);
+	extern void __iounmap(void __iomem *addr);
 
 	if ((u32)addr >= VMALLOC_START)
 		__iounmap(addr);

include/asm-arm/arch-l7200/io.h

@@ -17,9 +17,9 @@
 /*
  * There are not real ISA nor PCI buses, so we fake it.
  */
-#define __io_pci(a)             (PCIO_BASE + (a))
-#define __mem_pci(a)            ((unsigned long)(a))
-#define __mem_isa(a)            ((unsigned long)(a))
+#define __io_pci(a)		((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 #define __ioaddr(p)             __io_pci(p)
 

include/asm-arm/arch-lh7a40x/io.h

@@ -14,8 +14,8 @@
 #define IO_SPACE_LIMIT 0xffffffff
 
 /* No ISA or PCI bus on this machine. */
-#define __io(a)			(a)
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(a)			((void __iomem *)(a))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 #endif /* __ASM_ARCH_IO_H */

include/asm-arm/arch-omap/io.h

@@ -40,9 +40,9 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)			(PCIO_BASE + (a))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 /*
  * ----------------------------------------------------------------------------

include/asm-arm/arch-pxa/io.h

@@ -12,8 +12,8 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)			(a)
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(a)			((void __iomem *)(a))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 #endif

include/asm-arm/arch-rpc/io.h

@@ -250,6 +250,6 @@ DECLARE_IO(int,l,"")
 /*
  * 1:1 mapping for ioremapped regions.
  */
-#define __mem_pci(x)	((unsigned long)(x))
+#define __mem_pci(x)	(x)
 
 #endif

include/asm-arm/arch-s3c2410/dma.h

@@ -198,7 +198,7 @@ struct s3c2410_dma_chan_s {
 	unsigned int           flags;        /* channel flags */
 
 	/* channel's hardware position and configuration */
-	unsigned long          regs;         /* channels registers */
+	void __iomem           *regs;        /* channels registers */
 	unsigned int           irq;          /* channel irq */
 	unsigned long          addr_reg;     /* data address register */
 	unsigned long          dcon;         /* default value of DCON */

include/asm-arm/arch-sa1100/io.h

@@ -16,8 +16,8 @@
  * We don't actually have real ISA nor PCI buses, but there is so many 
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)			(PCIO_BASE + (a))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 #endif

include/asm-arm/arch-shark/io.h

@@ -170,7 +170,7 @@ DECLARE_IO(long,l,"")
 	addr;									\
 })
 
-#define __mem_pci(addr) addr
+#define __mem_pci(addr) (addr)
 
 #define inb(p)	 	(__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
 #define inw(p)	 	(__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))

include/asm-arm/arch-versatile/io.h

@@ -22,8 +22,8 @@
 
 #define IO_SPACE_LIMIT 0xffff
 
-#define __io(a)			((a))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
+#define __io(a)			((void __iomem *)(a))
+#define __mem_pci(a)		(a)
+#define __mem_isa(a)		(a)
 
 #endif

include/asm-arm/hardware/amba_clcd.h

@@ -141,7 +141,7 @@ struct clcd_fb {
 	struct clcd_panel	*panel;
 	struct clcd_board	*board;
 	void			*board_data;
-	void			*regs;
+	void __iomem		*regs;
 	u32			clcd_cntl;
 	u32			cmap[16];
 };

include/asm-arm/io.h

@@ -39,21 +39,21 @@
  * Generic IO read/write.  These perform native-endian accesses.  Note
  * that some architectures will want to re-define __raw_{read,write}w.
  */
-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
+extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
+extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 
-extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
-extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
-extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+extern void __raw_readsb(void __iomem *addr, void *data, int bytelen);
+extern void __raw_readsw(void __iomem *addr, void *data, int wordlen);
+extern void __raw_readsl(void __iomem *addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
-#define __raw_writew(v,a)	(*(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
+#define __raw_writeb(v,a)	(*(volatile unsigned char __force  *)(a) = (v))
+#define __raw_writew(v,a)	(*(volatile unsigned short __force *)(a) = (v))
+#define __raw_writel(v,a)	(*(volatile unsigned int __force   *)(a) = (v))
 
-#define __raw_readb(a)		(*(volatile unsigned char  *)(a))
-#define __raw_readw(a)		(*(volatile unsigned short *)(a))
-#define __raw_readl(a)		(*(volatile unsigned int   *)(a))
+#define __raw_readb(a)		(*(volatile unsigned char __force  *)(a))
+#define __raw_readw(a)		(*(volatile unsigned short __force *)(a))
+#define __raw_readl(a)		(*(volatile unsigned int __force   *)(a))
 
 /*
  * Bad read/write accesses...
@@ -156,17 +156,17 @@ extern void _memset_io(void __iomem *, int, size_t);
 #define readw_relaxed(addr) readw(addr)
 #define readl_relaxed(addr) readl(addr)
 
-#define readsb(p,d,l)		__raw_readsb((unsigned int)__mem_pci(p),d,l)
-#define readsw(p,d,l)		__raw_readsw((unsigned int)__mem_pci(p),d,l)
-#define readsl(p,d,l)		__raw_readsl((unsigned int)__mem_pci(p),d,l)
+#define readsb(p,d,l)		__raw_readsb(__mem_pci(p),d,l)
+#define readsw(p,d,l)		__raw_readsw(__mem_pci(p),d,l)
+#define readsl(p,d,l)		__raw_readsl(__mem_pci(p),d,l)
 
 #define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
 #define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
 #define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
 
-#define writesb(p,d,l)		__raw_writesb((unsigned int)__mem_pci(p),d,l)
-#define writesw(p,d,l)		__raw_writesw((unsigned int)__mem_pci(p),d,l)
-#define writesl(p,d,l)		__raw_writesl((unsigned int)__mem_pci(p),d,l)
+#define writesb(p,d,l)		__raw_writesb(__mem_pci(p),d,l)
+#define writesw(p,d,l)		__raw_writesw(__mem_pci(p),d,l)
+#define writesl(p,d,l)		__raw_writesl(__mem_pci(p),d,l)
 
 #define memset_io(c,v,l)	_memset_io(__mem_pci(c),(v),(l))
 #define memcpy_fromio(a,c,l)	_memcpy_fromio((a),__mem_pci(c),(l))
@@ -268,8 +268,8 @@ isa_check_signature(unsigned long io_addr, const unsigned char *signature,
  * ioremap takes a PCI memory address, as specified in
  * Documentation/IO-mapping.txt.
  */
-extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
-extern void __iounmap(void *addr);
+extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
+extern void __iounmap(void __iomem *addr);
 
 #ifndef __arch_ioremap
 #define ioremap(cookie,size)		__ioremap(cookie,size,0,1)