Commit 90cf8e21 authored by Jiucheng Xu's avatar Jiucheng Xu Committed by Neil Armstrong

arm64: dts: meson: Add DDR PMU node

Add DDR PMU device node for G12 series SoC
Signed-off-by: default avatarJiucheng Xu <jiucheng.xu@amlogic.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20221109015818.194927-4-jiucheng.xu@amlogic.comSigned-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent 49f65e2e
...@@ -1705,6 +1705,12 @@ internal_ephy: ethernet_phy@8 { ...@@ -1705,6 +1705,12 @@ internal_ephy: ethernet_phy@8 {
}; };
}; };
pmu: pmu@ff638000 {
reg = <0x0 0xff638000 0x0 0x100>,
<0x0 0xff638c00 0x0 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
};
aobus: bus@ff800000 { aobus: bus@ff800000 {
compatible = "simple-bus"; compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>; reg = <0x0 0xff800000 0x0 0x100000>;
......
...@@ -134,3 +134,7 @@ map1 { ...@@ -134,3 +134,7 @@ map1 {
}; };
}; };
}; };
&pmu {
compatible = "amlogic,g12a-ddr-pmu";
};
...@@ -140,3 +140,7 @@ map1 { ...@@ -140,3 +140,7 @@ map1 {
&mali { &mali {
dma-coherent; dma-coherent;
}; };
&pmu {
compatible = "amlogic,g12b-ddr-pmu";
};
...@@ -521,6 +521,10 @@ &pcie { ...@@ -521,6 +521,10 @@ &pcie {
power-domains = <&pwrc PWRC_SM1_PCIE_ID>; power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
}; };
&pmu {
compatible = "amlogic,sm1-ddr-pmu";
};
&pwrc { &pwrc {
compatible = "amlogic,meson-sm1-pwrc"; compatible = "amlogic,meson-sm1-pwrc";
}; };
......
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