Commit 91207f62 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Peter Zijlstra

arm64/perf: Assert all platform event flags are within PERF_EVENT_FLAG_ARCH

Ensure all platform specific event flags are within PERF_EVENT_FLAG_ARCH.
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarJames Clark <james.clark@arm.com>
Link: https://lkml.kernel.org/r/20220907091924.439193-4-anshuman.khandual@arm.com
parent f67dd218
...@@ -44,7 +44,9 @@ ...@@ -44,7 +44,9 @@
* This allows us to perform the check, i.e, perfmon_capable(), * This allows us to perform the check, i.e, perfmon_capable(),
* in the context of the event owner, once, during the event_init(). * in the context of the event owner, once, during the event_init().
*/ */
#define SPE_PMU_HW_FLAGS_CX BIT(0) #define SPE_PMU_HW_FLAGS_CX 0x00001
static_assert((PERF_EVENT_FLAG_ARCH & SPE_PMU_HW_FLAGS_CX) == SPE_PMU_HW_FLAGS_CX);
static void set_spe_event_has_cx(struct perf_event *event) static void set_spe_event_has_cx(struct perf_event *event)
{ {
......
...@@ -24,10 +24,11 @@ ...@@ -24,10 +24,11 @@
/* /*
* ARM PMU hw_event flags * ARM PMU hw_event flags
*/ */
/* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
#define ARMPMU_EVT_64BIT 1 #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
/* Event uses a 47bit counter */
#define ARMPMU_EVT_47BIT 2 static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT);
static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT);
#define HW_OP_UNSUPPORTED 0xFFFF #define HW_OP_UNSUPPORTED 0xFFFF
#define C(_x) PERF_COUNT_HW_CACHE_##_x #define C(_x) PERF_COUNT_HW_CACHE_##_x
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment