Commit 926fd45b authored by Santosh Shilimkar's avatar Santosh Shilimkar Committed by Benoit Cousson

ARM: OMAP4: Add L2 Cache Controller in Device Tree

Provide PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
parent 11c27069
......@@ -30,12 +30,21 @@ aliases {
cpus {
cpu@0 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
};
};
L2: l2-cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;
cache-level = <2>;
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
......
......@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
......@@ -171,6 +172,9 @@ static int __init omap_l2_cache_init(void)
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
if (of_have_populated_dt())
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
else
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
/*
......
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