Commit 92c9e0c7 authored by Andreas Färber's avatar Andreas Färber Committed by Olof Johansson

ARM: dts: zynq: Enable PL clocks for Parallella

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 5305e4d6
...@@ -34,6 +34,10 @@ chosen { ...@@ -34,6 +34,10 @@ chosen {
}; };
}; };
&clkc {
fclk-enable = <0xf>;
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
......
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