Commit 9368931d authored by Alex Deucher's avatar Alex Deucher

drm/radeon: adjust default dispclk on DCE6 (v2)

Set the default to 600Mhz if it's not set in the bios,
and bump the default to 600Mhz if it's lower than that.

This fixes display issues with certain 4k DP monitors when
using 5.4 Ghz DP clocks.

v2: fix typo.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0fcb70c3
...@@ -1227,11 +1227,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) ...@@ -1227,11 +1227,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
rdev->clock.default_dispclk = rdev->clock.default_dispclk =
le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
if (rdev->clock.default_dispclk == 0) { if (rdev->clock.default_dispclk == 0) {
if (ASIC_IS_DCE5(rdev)) if (ASIC_IS_DCE6(rdev))
rdev->clock.default_dispclk = 60000; /* 600 Mhz */
else if (ASIC_IS_DCE5(rdev))
rdev->clock.default_dispclk = 54000; /* 540 Mhz */ rdev->clock.default_dispclk = 54000; /* 540 Mhz */
else else
rdev->clock.default_dispclk = 60000; /* 600 Mhz */ rdev->clock.default_dispclk = 60000; /* 600 Mhz */
} }
/* set a reasonable default for DP */
if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
rdev->clock.default_dispclk / 100);
rdev->clock.default_dispclk = 60000;
}
rdev->clock.dp_extclk = rdev->clock.dp_extclk =
le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
rdev->clock.current_dispclk = rdev->clock.default_dispclk; rdev->clock.current_dispclk = rdev->clock.default_dispclk;
......
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