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Commit 96004636 authored by Catalin Marinas's avatar Catalin Marinas
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Merge branch 'for-next/sysreg-hwcaps' into for-next/core 

* for-next/sysreg-hwcaps:
  : Make use of sysreg helpers for hwcaps
  arm64/cpufeature: Use helper macros to specify hwcaps
  arm64/cpufeature: Always use symbolic name for feature value in hwcaps
  arm64/sysreg: Initial unsigned annotations for ID registers
  arm64/sysreg: Initial annotation of signed ID registers
  arm64/sysreg: Allow enumerations to be declared as signed or unsigned
parents 156010ed bfffd469
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Showing with 321 additions and 298 deletions
arch/arm64/kernel/cpufeature.c
View file @ 96004636
...@@ -2750,13 +2750,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ...@@ -2750,13 +2750,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
{}, {},
}; };
#define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ #define HWCAP_CPUID_MATCH(reg, field, min_value) \
.matches = has_user_cpuid_feature, \ .matches = has_user_cpuid_feature, \
.sys_reg = reg, \ .sys_reg = SYS_##reg, \
.field_pos = field, \ .field_pos = reg##_##field##_SHIFT, \
.field_width = width, \ .field_width = reg##_##field##_WIDTH, \
.sign = s, \ .sign = reg##_##field##_SIGNED, \
.min_field_value = min_value, .min_field_value = reg##_##field##_##min_value,
#define __HWCAP_CAP(name, cap_type, cap) \ #define __HWCAP_CAP(name, cap_type, cap) \
.desc = name, \ .desc = name, \
...@@ -2764,10 +2764,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ...@@ -2764,10 +2764,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.hwcap_type = cap_type, \ .hwcap_type = cap_type, \
.hwcap = cap, \ .hwcap = cap, \
#define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \
{ \ { \
__HWCAP_CAP(#cap, cap_type, cap) \ __HWCAP_CAP(#cap, cap_type, cap) \
HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ HWCAP_CPUID_MATCH(reg, field, min_value) \
} }
#define HWCAP_MULTI_CAP(list, cap_type, cap) \ #define HWCAP_MULTI_CAP(list, cap_type, cap) \
...@@ -2786,121 +2786,114 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ...@@ -2786,121 +2786,114 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
#ifdef CONFIG_ARM64_PTR_AUTH #ifdef CONFIG_ARM64_PTR_AUTH
static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
{ {
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth)
4, FTR_UNSIGNED,
ID_AA64ISAR1_EL1_APA_PAuth)
}, },
{ {
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth)
4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth)
}, },
{ {
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth)
4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth)
}, },
{}, {},
}; };
static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
{ {
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP)
4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)
}, },
{ {
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP)
4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP)
}, },
{ {
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP)
4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP)
}, },
{}, {},
}; };
#endif #endif
static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16), HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
#ifdef CONFIG_ARM64_SVE #ifdef CONFIG_ARM64_SVE
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
#endif #endif
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SSBS_SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
#ifdef CONFIG_ARM64_BTI #ifdef CONFIG_ARM64_BTI
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_BT_IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
#endif #endif
#ifdef CONFIG_ARM64_PTR_AUTH #ifdef CONFIG_ARM64_PTR_AUTH
HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
#endif #endif
#ifdef CONFIG_ARM64_MTE #ifdef CONFIG_ARM64_MTE
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
#endif /* CONFIG_ARM64_MTE */ #endif /* CONFIG_ARM64_MTE */
HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_RPRFM_IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
#ifdef CONFIG_ARM64_SME #ifdef CONFIG_ARM64_SME
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME_IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_SMEver_SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_SMEver_SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16B16_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F16_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_BI32I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
#endif /* CONFIG_ARM64_SME */ #endif /* CONFIG_ARM64_SME */
{}, {},
}; };
...@@ -2930,23 +2923,23 @@ static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) ...@@ -2930,23 +2923,23 @@ static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
#ifdef CONFIG_COMPAT #ifdef CONFIG_COMPAT
HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_FPHP_SHIFT, 4, FTR_UNSIGNED, 3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_SIMDHP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
HWCAP_CAP(SYS_ID_PFR2_EL1, ID_PFR2_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
#endif #endif
{}, {},
}; };
......
arch/arm64/tools/gen-sysreg.awk
View file @ 96004636
...@@ -44,6 +44,11 @@ function define_field(reg, field, msb, lsb) { ...@@ -44,6 +44,11 @@ function define_field(reg, field, msb, lsb) {
define(reg "_" field "_WIDTH", msb - lsb + 1) define(reg "_" field "_WIDTH", msb - lsb + 1)
} }
# Print a field _SIGNED definition for a field
function define_field_sign(reg, field, sign) {
define(reg "_" field "_SIGNED", sign)
}
# Parse a "<msb>[:<lsb>]" string into the global variables @msb and @lsb # Parse a "<msb>[:<lsb>]" string into the global variables @msb and @lsb
function parse_bitdef(reg, field, bitdef, _bits) function parse_bitdef(reg, field, bitdef, _bits)
{ {
...@@ -233,6 +238,30 @@ END { ...@@ -233,6 +238,30 @@ END {
next next
} }
/^SignedEnum/ {
change_block("Enum<", "Sysreg", "Enum")
expect_fields(3)
field = $3
parse_bitdef(reg, field, $2)
define_field(reg, field, msb, lsb)
define_field_sign(reg, field, "true")
next
}
/^UnsignedEnum/ {
change_block("Enum<", "Sysreg", "Enum")
expect_fields(3)
field = $3
parse_bitdef(reg, field, $2)
define_field(reg, field, msb, lsb)
define_field_sign(reg, field, "false")
next
}
/^Enum/ { /^Enum/ {
change_block("Enum", "Sysreg", "Enum") change_block("Enum", "Sysreg", "Enum")
expect_fields(3) expect_fields(3)
......
arch/arm64/tools/sysreg
View file @ 96004636
...@@ -48,26 +48,26 @@ ...@@ -48,26 +48,26 @@
Sysreg ID_PFR0_EL1 3 0 0 1 0 Sysreg ID_PFR0_EL1 3 0 0 1 0
Res0 63:32 Res0 63:32
Enum 31:28 RAS UnsignedEnum 31:28 RAS
0b0000 NI 0b0000 NI
0b0001 RAS 0b0001 RAS
0b0010 RASv1p1 0b0010 RASv1p1
EndEnum EndEnum
Enum 27:24 DIT UnsignedEnum 27:24 DIT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 AMU UnsignedEnum 23:20 AMU
0b0000 NI 0b0000 NI
0b0001 AMUv1 0b0001 AMUv1
0b0010 AMUv1p1 0b0010 AMUv1p1
EndEnum EndEnum
Enum 19:16 CSV2 UnsignedEnum 19:16 CSV2
0b0000 UNDISCLOSED 0b0000 UNDISCLOSED
0b0001 IMP 0b0001 IMP
0b0010 CSV2p1 0b0010 CSV2p1
EndEnum EndEnum
Enum 15:12 State3 UnsignedEnum 15:12 State3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -76,12 +76,12 @@ Enum 11:8 State2 ...@@ -76,12 +76,12 @@ Enum 11:8 State2
0b0001 NO_CV 0b0001 NO_CV
0b0010 CV 0b0010 CV
EndEnum EndEnum
Enum 7:4 State1 UnsignedEnum 7:4 State1
0b0000 NI 0b0000 NI
0b0001 THUMB 0b0001 THUMB
0b0010 THUMB2 0b0010 THUMB2
EndEnum EndEnum
Enum 3:0 State0 UnsignedEnum 3:0 State0
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -89,12 +89,12 @@ EndSysreg ...@@ -89,12 +89,12 @@ EndSysreg
Sysreg ID_PFR1_EL1 3 0 0 1 1 Sysreg ID_PFR1_EL1 3 0 0 1 1
Res0 63:32 Res0 63:32
Enum 31:28 GIC UnsignedEnum 31:28 GIC
0b0000 NI 0b0000 NI
0b0001 GICv3 0b0001 GICv3
0b0010 GICv4p1 0b0010 GICv4p1
EndEnum EndEnum
Enum 27:24 Virt_frac UnsignedEnum 27:24 Virt_frac
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -103,16 +103,16 @@ Enum 23:20 Sec_frac ...@@ -103,16 +103,16 @@ Enum 23:20 Sec_frac
0b0001 WALK_DISABLE 0b0001 WALK_DISABLE
0b0010 SECURE_MEMORY 0b0010 SECURE_MEMORY
EndEnum EndEnum
Enum 19:16 GenTimer UnsignedEnum 19:16 GenTimer
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 ECV 0b0010 ECV
EndEnum EndEnum
Enum 15:12 Virtualization UnsignedEnum 15:12 Virtualization
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 MProgMod UnsignedEnum 11:8 MProgMod
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -121,7 +121,7 @@ Enum 7:4 Security ...@@ -121,7 +121,7 @@ Enum 7:4 Security
0b0001 EL3 0b0001 EL3
0b0001 NSACR_RFR 0b0001 NSACR_RFR
EndEnum EndEnum
Enum 3:0 ProgMod UnsignedEnum 3:0 ProgMod
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -129,11 +129,11 @@ EndSysreg ...@@ -129,11 +129,11 @@ EndSysreg
Sysreg ID_DFR0_EL1 3 0 0 1 2 Sysreg ID_DFR0_EL1 3 0 0 1 2
Res0 63:32 Res0 63:32
Enum 31:28 TraceFilt UnsignedEnum 31:28 TraceFilt
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 PerfMon UnsignedEnum 27:24 PerfMon
0b0000 NI 0b0000 NI
0b0001 PMUv1 0b0001 PMUv1
0b0010 PMUv2 0b0010 PMUv2
...@@ -192,7 +192,7 @@ Enum 31:28 InnerShr ...@@ -192,7 +192,7 @@ Enum 31:28 InnerShr
0b0001 HW 0b0001 HW
0b1111 IGNORED 0b1111 IGNORED
EndEnum EndEnum
Enum 27:24 FCSE UnsignedEnum 27:24 FCSE
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -369,7 +369,7 @@ Enum 27:24 Divide ...@@ -369,7 +369,7 @@ Enum 27:24 Divide
0b0001 xDIV_T32 0b0001 xDIV_T32
0b0010 xDIV_A32 0b0010 xDIV_A32
EndEnum EndEnum
Enum 23:20 Debug UnsignedEnum 23:20 Debug
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -380,19 +380,19 @@ Enum 19:16 Coproc ...@@ -380,19 +380,19 @@ Enum 19:16 Coproc
0b0011 MRRC 0b0011 MRRC
0b0100 MRRC2 0b0100 MRRC2
EndEnum EndEnum
Enum 15:12 CmpBranch UnsignedEnum 15:12 CmpBranch
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 BitField UnsignedEnum 11:8 BitField
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 BitCount UnsignedEnum 7:4 BitCount
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 Swap UnsignedEnum 3:0 Swap
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -562,33 +562,33 @@ EndSysreg ...@@ -562,33 +562,33 @@ EndSysreg
Sysreg ID_ISAR5_EL1 3 0 0 2 5 Sysreg ID_ISAR5_EL1 3 0 0 2 5
Res0 63:32 Res0 63:32
Enum 31:28 VCMA UnsignedEnum 31:28 VCMA
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 RDM UnsignedEnum 27:24 RDM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 23:20 Res0 23:20
Enum 19:16 CRC32 UnsignedEnum 19:16 CRC32
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 SHA2 UnsignedEnum 15:12 SHA2
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 SHA1 UnsignedEnum 11:8 SHA1
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 AES UnsignedEnum 7:4 AES
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 VMULL 0b0010 VMULL
EndEnum EndEnum
Enum 3:0 SEVL UnsignedEnum 3:0 SEVL
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -596,31 +596,31 @@ EndSysreg ...@@ -596,31 +596,31 @@ EndSysreg
Sysreg ID_ISAR6_EL1 3 0 0 2 7 Sysreg ID_ISAR6_EL1 3 0 0 2 7
Res0 63:28 Res0 63:28
Enum 27:24 I8MM UnsignedEnum 27:24 I8MM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 BF16 UnsignedEnum 23:20 BF16
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 19:16 SPECRES UnsignedEnum 19:16 SPECRES
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 SB UnsignedEnum 15:12 SB
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 FHM UnsignedEnum 11:8 FHM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 DP UnsignedEnum 7:4 DP
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 JSCVT UnsignedEnum 3:0 JSCVT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -628,37 +628,37 @@ EndSysreg ...@@ -628,37 +628,37 @@ EndSysreg
Sysreg ID_MMFR4_EL1 3 0 0 2 6 Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32 Res0 63:32
Enum 31:28 EVT UnsignedEnum 31:28 EVT
0b0000 NI 0b0000 NI
0b0001 NO_TLBIS 0b0001 NO_TLBIS
0b0010 TLBIS 0b0010 TLBIS
EndEnum EndEnum
Enum 27:24 CCIDX UnsignedEnum 27:24 CCIDX
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 LSM UnsignedEnum 23:20 LSM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 19:16 HPDS UnsignedEnum 19:16 HPDS
0b0000 NI 0b0000 NI
0b0001 AA32HPD 0b0001 AA32HPD
0b0010 HPDS2 0b0010 HPDS2
EndEnum EndEnum
Enum 15:12 CnP UnsignedEnum 15:12 CnP
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 XNX UnsignedEnum 11:8 XNX
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 AC2 UnsignedEnum 7:4 AC2
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 SpecSEI UnsignedEnum 3:0 SpecSEI
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -666,32 +666,32 @@ EndSysreg ...@@ -666,32 +666,32 @@ EndSysreg
Sysreg MVFR0_EL1 3 0 0 3 0 Sysreg MVFR0_EL1 3 0 0 3 0
Res0 63:32 Res0 63:32
Enum 31:28 FPRound UnsignedEnum 31:28 FPRound
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 FPShVec UnsignedEnum 27:24 FPShVec
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 FPSqrt UnsignedEnum 23:20 FPSqrt
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 19:16 FPDivide UnsignedEnum 19:16 FPDivide
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 FPTrap UnsignedEnum 15:12 FPTrap
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 FPDP UnsignedEnum 11:8 FPDP
0b0000 NI 0b0000 NI
0b0001 VFPv2 0b0001 VFPv2
0b0010 VFPv3 0b0010 VFPv3
EndEnum EndEnum
Enum 7:4 FPSP UnsignedEnum 7:4 FPSP
0b0000 NI 0b0000 NI
0b0001 VFPv2 0b0001 VFPv2
0b0010 VFPv3 0b0010 VFPv3
...@@ -705,38 +705,38 @@ EndSysreg ...@@ -705,38 +705,38 @@ EndSysreg
Sysreg MVFR1_EL1 3 0 0 3 1 Sysreg MVFR1_EL1 3 0 0 3 1
Res0 63:32 Res0 63:32
Enum 31:28 SIMDFMAC UnsignedEnum 31:28 SIMDFMAC
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 FPHP UnsignedEnum 27:24 FPHP
0b0000 NI 0b0000 NI
0b0001 FPHP 0b0001 FPHP
0b0010 FPHP_CONV 0b0010 FPHP_CONV
0b0011 FP16 0b0011 FP16
EndEnum EndEnum
Enum 23:20 SIMDHP UnsignedEnum 23:20 SIMDHP
0b0000 NI 0b0000 NI
0b0001 SIMDHP 0b0001 SIMDHP
0b0010 SIMDHP_FLOAT 0b0010 SIMDHP_FLOAT
EndEnum EndEnum
Enum 19:16 SIMDSP UnsignedEnum 19:16 SIMDSP
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 SIMDInt UnsignedEnum 15:12 SIMDInt
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 SIMDLS UnsignedEnum 11:8 SIMDLS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 FPDNaN UnsignedEnum 7:4 FPDNaN
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 FPFtZ UnsignedEnum 3:0 FPFtZ
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -761,15 +761,15 @@ EndSysreg ...@@ -761,15 +761,15 @@ EndSysreg
Sysreg ID_PFR2_EL1 3 0 0 3 4 Sysreg ID_PFR2_EL1 3 0 0 3 4
Res0 63:12 Res0 63:12
Enum 11:8 RAS_frac UnsignedEnum 11:8 RAS_frac
0b0000 NI 0b0000 NI
0b0001 RASv1p1 0b0001 RASv1p1
EndEnum EndEnum
Enum 7:4 SSBS UnsignedEnum 7:4 SSBS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 CSV3 UnsignedEnum 3:0 CSV3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -777,7 +777,7 @@ EndSysreg ...@@ -777,7 +777,7 @@ EndSysreg
Sysreg ID_DFR1_EL1 3 0 0 3 5 Sysreg ID_DFR1_EL1 3 0 0 3 5
Res0 63:8 Res0 63:8
Enum 7:4 HPMN0 UnsignedEnum 7:4 HPMN0
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -790,87 +790,87 @@ EndSysreg ...@@ -790,87 +790,87 @@ EndSysreg
Sysreg ID_MMFR5_EL1 3 0 0 3 6 Sysreg ID_MMFR5_EL1 3 0 0 3 6
Res0 63:8 Res0 63:8
Enum 7:4 nTLBPA UnsignedEnum 7:4 nTLBPA
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 ETS UnsignedEnum 3:0 ETS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
EndSysreg EndSysreg
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0 Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3 UnsignedEnum 63:60 CSV3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 59:56 CSV2 UnsignedEnum 59:56 CSV2
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 CSV2_2 0b0010 CSV2_2
0b0011 CSV2_3 0b0011 CSV2_3
EndEnum EndEnum
Enum 55:52 RME UnsignedEnum 55:52 RME
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 51:48 DIT UnsignedEnum 51:48 DIT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 47:44 AMU UnsignedEnum 47:44 AMU
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 V1P1 0b0010 V1P1
EndEnum EndEnum
Enum 43:40 MPAM UnsignedEnum 43:40 MPAM
0b0000 0 0b0000 0
0b0001 1 0b0001 1
EndEnum EndEnum
Enum 39:36 SEL2 UnsignedEnum 39:36 SEL2
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 35:32 SVE UnsignedEnum 35:32 SVE
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 31:28 RAS UnsignedEnum 31:28 RAS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 V1P1 0b0010 V1P1
EndEnum EndEnum
Enum 27:24 GIC UnsignedEnum 27:24 GIC
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 V4P1 0b0010 V4P1
EndEnum EndEnum
Enum 23:20 AdvSIMD SignedEnum 23:20 AdvSIMD
0b0000 IMP 0b0000 IMP
0b0001 FP16 0b0001 FP16
0b1111 NI 0b1111 NI
EndEnum EndEnum
Enum 19:16 FP SignedEnum 19:16 FP
0b0000 IMP 0b0000 IMP
0b0001 FP16 0b0001 FP16
0b1111 NI 0b1111 NI
EndEnum EndEnum
Enum 15:12 EL3 UnsignedEnum 15:12 EL3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 AARCH32 0b0010 AARCH32
EndEnum EndEnum
Enum 11:8 EL2 UnsignedEnum 11:8 EL2
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 AARCH32 0b0010 AARCH32
EndEnum EndEnum
Enum 7:4 EL1 UnsignedEnum 7:4 EL1
0b0001 IMP 0b0001 IMP
0b0010 AARCH32 0b0010 AARCH32
EndEnum EndEnum
Enum 3:0 EL0 UnsignedEnum 3:0 EL0
0b0001 IMP 0b0001 IMP
0b0010 AARCH32 0b0010 AARCH32
EndEnum EndEnum
...@@ -878,45 +878,45 @@ EndSysreg ...@@ -878,45 +878,45 @@ EndSysreg
Sysreg ID_AA64PFR1_EL1 3 0 0 4 1 Sysreg ID_AA64PFR1_EL1 3 0 0 4 1
Res0 63:40 Res0 63:40
Enum 39:36 NMI UnsignedEnum 39:36 NMI
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 35:32 CSV2_frac UnsignedEnum 35:32 CSV2_frac
0b0000 NI 0b0000 NI
0b0001 CSV2_1p1 0b0001 CSV2_1p1
0b0010 CSV2_1p2 0b0010 CSV2_1p2
EndEnum EndEnum
Enum 31:28 RNDR_trap UnsignedEnum 31:28 RNDR_trap
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 SME UnsignedEnum 27:24 SME
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 SME2 0b0010 SME2
EndEnum EndEnum
Res0 23:20 Res0 23:20
Enum 19:16 MPAM_frac UnsignedEnum 19:16 MPAM_frac
0b0000 MINOR_0 0b0000 MINOR_0
0b0001 MINOR_1 0b0001 MINOR_1
EndEnum EndEnum
Enum 15:12 RAS_frac UnsignedEnum 15:12 RAS_frac
0b0000 NI 0b0000 NI
0b0001 RASv1p1 0b0001 RASv1p1
EndEnum EndEnum
Enum 11:8 MTE UnsignedEnum 11:8 MTE
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 MTE2 0b0010 MTE2
0b0011 MTE3 0b0011 MTE3
EndEnum EndEnum
Enum 7:4 SSBS UnsignedEnum 7:4 SSBS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 SSBS2 0b0010 SSBS2
EndEnum EndEnum
Enum 3:0 BT UnsignedEnum 3:0 BT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -924,45 +924,45 @@ EndSysreg ...@@ -924,45 +924,45 @@ EndSysreg
Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
Res0 63:60 Res0 63:60
Enum 59:56 F64MM UnsignedEnum 59:56 F64MM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 55:52 F32MM UnsignedEnum 55:52 F32MM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 51:48 Res0 51:48
Enum 47:44 I8MM UnsignedEnum 47:44 I8MM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 43:40 SM4 UnsignedEnum 43:40 SM4
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 39:36 Res0 39:36
Enum 35:32 SHA3 UnsignedEnum 35:32 SHA3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 31:24 Res0 31:24
Enum 23:20 BF16 UnsignedEnum 23:20 BF16
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 EBF16 0b0010 EBF16
EndEnum EndEnum
Enum 19:16 BitPerm UnsignedEnum 19:16 BitPerm
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 15:8 Res0 15:8
Enum 7:4 AES UnsignedEnum 7:4 AES
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 PMULL128 0b0010 PMULL128
EndEnum EndEnum
Enum 3:0 SVEver UnsignedEnum 3:0 SVEver
0b0000 IMP 0b0000 IMP
0b0001 SVE2 0b0001 SVE2
0b0010 SVE2p1 0b0010 SVE2p1
...@@ -970,55 +970,56 @@ EndEnum ...@@ -970,55 +970,56 @@ EndEnum
EndSysreg EndSysreg
Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
Enum 63 FA64 UnsignedEnum 63 FA64
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Res0 62:60 Res0 62:60
Enum 59:56 SMEver UnsignedEnum 59:56 SMEver
0b0000 SME 0b0000 SME
0b0001 SME2 0b0001 SME2
0b0010 SME2p1 0b0010 SME2p1
0b0000 IMP
EndEnum EndEnum
Enum 55:52 I16I64 UnsignedEnum 55:52 I16I64
0b0000 NI 0b0000 NI
0b1111 IMP 0b1111 IMP
EndEnum EndEnum
Res0 51:49 Res0 51:49
Enum 48 F64F64 UnsignedEnum 48 F64F64
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Enum 47:44 I16I32 UnsignedEnum 47:44 I16I32
0b0000 NI 0b0000 NI
0b0101 IMP 0b0101 IMP
EndEnum EndEnum
Enum 43 B16B16 UnsignedEnum 43 B16B16
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Enum 42 F16F16 UnsignedEnum 42 F16F16
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Res0 41:40 Res0 41:40
Enum 39:36 I8I32 UnsignedEnum 39:36 I8I32
0b0000 NI 0b0000 NI
0b1111 IMP 0b1111 IMP
EndEnum EndEnum
Enum 35 F16F32 UnsignedEnum 35 F16F32
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Enum 34 B16F32 UnsignedEnum 34 B16F32
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Enum 33 BI32I32 UnsignedEnum 33 BI32I32
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
Enum 32 F32F32 UnsignedEnum 32 F32F32
0b0 NI 0b0 NI
0b1 IMP 0b1 IMP
EndEnum EndEnum
...@@ -1031,7 +1032,7 @@ Enum 63:60 HPMN0 ...@@ -1031,7 +1032,7 @@ Enum 63:60 HPMN0
0b0001 DEF 0b0001 DEF
EndEnum EndEnum
Res0 59:56 Res0 59:56
Enum 55:52 BRBE UnsignedEnum 55:52 BRBE
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 BRBE_V1P1 0b0010 BRBE_V1P1
...@@ -1041,19 +1042,19 @@ Enum 51:48 MTPMU ...@@ -1041,19 +1042,19 @@ Enum 51:48 MTPMU
0b0001 IMP 0b0001 IMP
0b1111 NI 0b1111 NI
EndEnum EndEnum
Enum 47:44 TraceBuffer UnsignedEnum 47:44 TraceBuffer
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 43:40 TraceFilt UnsignedEnum 43:40 TraceFilt
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 39:36 DoubleLock UnsignedEnum 39:36 DoubleLock
0b0000 IMP 0b0000 IMP
0b1111 NI 0b1111 NI
EndEnum EndEnum
Enum 35:32 PMSVer UnsignedEnum 35:32 PMSVer
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 V1P1 0b0010 V1P1
...@@ -1065,7 +1066,7 @@ Res0 27:24 ...@@ -1065,7 +1066,7 @@ Res0 27:24
Field 23:20 WRPs Field 23:20 WRPs
Res0 19:16 Res0 19:16
Field 15:12 BRPs Field 15:12 BRPs
Enum 11:8 PMUVer UnsignedEnum 11:8 PMUVer
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0100 V3P1 0b0100 V3P1
...@@ -1075,11 +1076,11 @@ Enum 11:8 PMUVer ...@@ -1075,11 +1076,11 @@ Enum 11:8 PMUVer
0b1000 V3P8 0b1000 V3P8
0b1111 IMP_DEF 0b1111 IMP_DEF
EndEnum EndEnum
Enum 7:4 TraceVer UnsignedEnum 7:4 TraceVer
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 DebugVer UnsignedEnum 3:0 DebugVer
0b0110 IMP 0b0110 IMP
0b0111 VHE 0b0111 VHE
0b1000 V8P2 0b1000 V8P2
...@@ -1109,66 +1110,66 @@ Res0 63:0 ...@@ -1109,66 +1110,66 @@ Res0 63:0
EndSysreg EndSysreg
Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0 Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
Enum 63:60 RNDR UnsignedEnum 63:60 RNDR
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 59:56 TLB UnsignedEnum 59:56 TLB
0b0000 NI 0b0000 NI
0b0001 OS 0b0001 OS
0b0010 RANGE 0b0010 RANGE
EndEnum EndEnum
Enum 55:52 TS UnsignedEnum 55:52 TS
0b0000 NI 0b0000 NI
0b0001 FLAGM 0b0001 FLAGM
0b0010 FLAGM2 0b0010 FLAGM2
EndEnum EndEnum
Enum 51:48 FHM UnsignedEnum 51:48 FHM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 47:44 DP UnsignedEnum 47:44 DP
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 43:40 SM4 UnsignedEnum 43:40 SM4
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 39:36 SM3 UnsignedEnum 39:36 SM3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 35:32 SHA3 UnsignedEnum 35:32 SHA3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 31:28 RDM UnsignedEnum 31:28 RDM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 TME UnsignedEnum 27:24 TME
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 ATOMIC UnsignedEnum 23:20 ATOMIC
0b0000 NI 0b0000 NI
0b0010 IMP 0b0010 IMP
EndEnum EndEnum
Enum 19:16 CRC32 UnsignedEnum 19:16 CRC32
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 SHA2 UnsignedEnum 15:12 SHA2
0b0000 NI 0b0000 NI
0b0001 SHA256 0b0001 SHA256
0b0010 SHA512 0b0010 SHA512
EndEnum EndEnum
Enum 11:8 SHA1 UnsignedEnum 11:8 SHA1
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 AES UnsignedEnum 7:4 AES
0b0000 NI 0b0000 NI
0b0001 AES 0b0001 AES
0b0010 PMULL 0b0010 PMULL
...@@ -1177,63 +1178,63 @@ Res0 3:0 ...@@ -1177,63 +1178,63 @@ Res0 3:0
EndSysreg EndSysreg
Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1 Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1
Enum 63:60 LS64 UnsignedEnum 63:60 LS64
0b0000 NI 0b0000 NI
0b0001 LS64 0b0001 LS64
0b0010 LS64_V 0b0010 LS64_V
0b0011 LS64_ACCDATA 0b0011 LS64_ACCDATA
EndEnum EndEnum
Enum 59:56 XS UnsignedEnum 59:56 XS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 55:52 I8MM UnsignedEnum 55:52 I8MM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 51:48 DGH UnsignedEnum 51:48 DGH
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 47:44 BF16 UnsignedEnum 47:44 BF16
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 EBF16 0b0010 EBF16
EndEnum EndEnum
Enum 43:40 SPECRES UnsignedEnum 43:40 SPECRES
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 39:36 SB UnsignedEnum 39:36 SB
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 35:32 FRINTTS UnsignedEnum 35:32 FRINTTS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 31:28 GPI UnsignedEnum 31:28 GPI
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 GPA UnsignedEnum 27:24 GPA
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 LRCPC UnsignedEnum 23:20 LRCPC
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 LRCPC2 0b0010 LRCPC2
EndEnum EndEnum
Enum 19:16 FCMA UnsignedEnum 19:16 FCMA
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 JSCVT UnsignedEnum 15:12 JSCVT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 API UnsignedEnum 11:8 API
0b0000 NI 0b0000 NI
0b0001 PAuth 0b0001 PAuth
0b0010 EPAC 0b0010 EPAC
...@@ -1241,7 +1242,7 @@ Enum 11:8 API ...@@ -1241,7 +1242,7 @@ Enum 11:8 API
0b0100 FPAC 0b0100 FPAC
0b0101 FPACCOMBINE 0b0101 FPACCOMBINE
EndEnum EndEnum
Enum 7:4 APA UnsignedEnum 7:4 APA
0b0000 NI 0b0000 NI
0b0001 PAuth 0b0001 PAuth
0b0010 EPAC 0b0010 EPAC
...@@ -1249,7 +1250,7 @@ Enum 7:4 APA ...@@ -1249,7 +1250,7 @@ Enum 7:4 APA
0b0100 FPAC 0b0100 FPAC
0b0101 FPACCOMBINE 0b0101 FPACCOMBINE
EndEnum EndEnum
Enum 3:0 DPB UnsignedEnum 3:0 DPB
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 DPB2 0b0010 DPB2
...@@ -1258,28 +1259,28 @@ EndSysreg ...@@ -1258,28 +1259,28 @@ EndSysreg
Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
Res0 63:56 Res0 63:56
Enum 55:52 CSSC UnsignedEnum 55:52 CSSC
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 51:48 RPRFM UnsignedEnum 51:48 RPRFM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 47:28 Res0 47:28
Enum 27:24 PAC_frac UnsignedEnum 27:24 PAC_frac
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 BC UnsignedEnum 23:20 BC
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 19:16 MOPS UnsignedEnum 19:16 MOPS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 APA3 UnsignedEnum 15:12 APA3
0b0000 NI 0b0000 NI
0b0001 PAuth 0b0001 PAuth
0b0010 EPAC 0b0010 EPAC
...@@ -1287,32 +1288,32 @@ Enum 15:12 APA3 ...@@ -1287,32 +1288,32 @@ Enum 15:12 APA3
0b0100 FPAC 0b0100 FPAC
0b0101 FPACCOMBINE 0b0101 FPACCOMBINE
EndEnum EndEnum
Enum 11:8 GPA3 UnsignedEnum 11:8 GPA3
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 RPRES UnsignedEnum 7:4 RPRES
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 WFxT UnsignedEnum 3:0 WFxT
0b0000 NI 0b0000 NI
0b0010 IMP 0b0010 IMP
EndEnum EndEnum
EndSysreg EndSysreg
Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0 Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0
Enum 63:60 ECV UnsignedEnum 63:60 ECV
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 CNTPOFF 0b0010 CNTPOFF
EndEnum EndEnum
Enum 59:56 FGT UnsignedEnum 59:56 FGT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 55:48 Res0 55:48
Enum 47:44 EXS UnsignedEnum 47:44 EXS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -1347,15 +1348,15 @@ Enum 23:20 TGRAN16 ...@@ -1347,15 +1348,15 @@ Enum 23:20 TGRAN16
0b0001 IMP 0b0001 IMP
0b0010 52_BIT 0b0010 52_BIT
EndEnum EndEnum
Enum 19:16 BIGENDEL0 UnsignedEnum 19:16 BIGENDEL0
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 SNSMEM UnsignedEnum 15:12 SNSMEM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 BIGEND UnsignedEnum 11:8 BIGEND
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -1375,62 +1376,62 @@ EndEnum ...@@ -1375,62 +1376,62 @@ EndEnum
EndSysreg EndSysreg
Sysreg ID_AA64MMFR1_EL1 3 0 0 7 1 Sysreg ID_AA64MMFR1_EL1 3 0 0 7 1
Enum 63:60 ECBHB UnsignedEnum 63:60 ECBHB
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 59:56 CMOW UnsignedEnum 59:56 CMOW
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 55:52 TIDCP1 UnsignedEnum 55:52 TIDCP1
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 51:48 nTLBPA UnsignedEnum 51:48 nTLBPA
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 47:44 AFP UnsignedEnum 47:44 AFP
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 43:40 HCX UnsignedEnum 43:40 HCX
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 39:36 ETS UnsignedEnum 39:36 ETS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 35:32 TWED UnsignedEnum 35:32 TWED
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 31:28 XNX UnsignedEnum 31:28 XNX
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 27:24 SpecSEI UnsignedEnum 27:24 SpecSEI
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 23:20 PAN UnsignedEnum 23:20 PAN
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 PAN2 0b0010 PAN2
0b0011 PAN3 0b0011 PAN3
EndEnum EndEnum
Enum 19:16 LO UnsignedEnum 19:16 LO
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 15:12 HPDS UnsignedEnum 15:12 HPDS
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 HPDS2 0b0010 HPDS2
EndEnum EndEnum
Enum 11:8 VH UnsignedEnum 11:8 VH
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -1438,7 +1439,7 @@ Enum 7:4 VMIDBits ...@@ -1438,7 +1439,7 @@ Enum 7:4 VMIDBits
0b0000 8 0b0000 8
0b0010 16 0b0010 16
EndEnum EndEnum
Enum 3:0 HAFDBS UnsignedEnum 3:0 HAFDBS
0b0000 NI 0b0000 NI
0b0001 AF 0b0001 AF
0b0010 DBM 0b0010 DBM
...@@ -1446,26 +1447,26 @@ EndEnum ...@@ -1446,26 +1447,26 @@ EndEnum
EndSysreg EndSysreg
Sysreg ID_AA64MMFR2_EL1 3 0 0 7 2 Sysreg ID_AA64MMFR2_EL1 3 0 0 7 2
Enum 63:60 E0PD UnsignedEnum 63:60 E0PD
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 59:56 EVT UnsignedEnum 59:56 EVT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 TTLBxS 0b0010 TTLBxS
EndEnum EndEnum
Enum 55:52 BBM UnsignedEnum 55:52 BBM
0b0000 0 0b0000 0
0b0001 1 0b0001 1
0b0010 2 0b0010 2
EndEnum EndEnum
Enum 51:48 TTL UnsignedEnum 51:48 TTL
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Res0 47:44 Res0 47:44
Enum 43:40 FWB UnsignedEnum 43:40 FWB
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -1473,7 +1474,7 @@ Enum 39:36 IDS ...@@ -1473,7 +1474,7 @@ Enum 39:36 IDS
0b0000 0x0 0b0000 0x0
0b0001 0x18 0b0001 0x18
EndEnum EndEnum
Enum 35:32 AT UnsignedEnum 35:32 AT
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
...@@ -1481,7 +1482,7 @@ Enum 31:28 ST ...@@ -1481,7 +1482,7 @@ Enum 31:28 ST
0b0000 39 0b0000 39
0b0001 48_47 0b0001 48_47
EndEnum EndEnum
Enum 27:24 NV UnsignedEnum 27:24 NV
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 NV2 0b0010 NV2
...@@ -1494,19 +1495,19 @@ Enum 19:16 VARange ...@@ -1494,19 +1495,19 @@ Enum 19:16 VARange
0b0000 48 0b0000 48
0b0001 52 0b0001 52
EndEnum EndEnum
Enum 15:12 IESB UnsignedEnum 15:12 IESB
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 11:8 LSM UnsignedEnum 11:8 LSM
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 7:4 UAO UnsignedEnum 7:4 UAO
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
Enum 3:0 CnP UnsignedEnum 3:0 CnP
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
EndEnum EndEnum
......
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