Commit 97bbdf02 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab

media: v4l: Add support for CSI-1 and CCP2 busses

CCP2 and CSI-1, are older single data lane serial busses.

[mchehab@s-opensource.com: don't use spaces for identation]
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarPavel Machek <pavel@ucw.cz>
Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent e07a41f9
...@@ -638,6 +638,9 @@ static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cf ...@@ -638,6 +638,9 @@ static unsigned int pxa_mbus_config_compatible(const struct v4l2_mbus_config *cf
mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK | mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK); V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
return (!mipi_lanes || !mipi_clock) ? 0 : common_flags; return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
default:
__WARN();
return -EINVAL;
} }
return 0; return 0;
} }
......
...@@ -508,6 +508,9 @@ unsigned int soc_mbus_config_compatible(const struct v4l2_mbus_config *cfg, ...@@ -508,6 +508,9 @@ unsigned int soc_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK | mipi_clock = common_flags & (V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK); V4L2_MBUS_CSI2_CONTINUOUS_CLOCK);
return (!mipi_lanes || !mipi_clock) ? 0 : common_flags; return (!mipi_lanes || !mipi_clock) ? 0 : common_flags;
default:
__WARN();
return -EINVAL;
} }
return 0; return 0;
} }
......
...@@ -154,6 +154,31 @@ static void v4l2_fwnode_endpoint_parse_parallel_bus( ...@@ -154,6 +154,31 @@ static void v4l2_fwnode_endpoint_parse_parallel_bus(
} }
void v4l2_fwnode_endpoint_parse_csi1_bus(struct fwnode_handle *fwnode,
struct v4l2_fwnode_endpoint *vep,
u32 bus_type)
{
struct v4l2_fwnode_bus_mipi_csi1 *bus = &vep->bus.mipi_csi1;
u32 v;
if (!fwnode_property_read_u32(fwnode, "clock-inv", &v))
bus->clock_inv = v;
if (!fwnode_property_read_u32(fwnode, "strobe", &v))
bus->strobe = v;
if (!fwnode_property_read_u32(fwnode, "data-lanes", &v))
bus->data_lane = v;
if (!fwnode_property_read_u32(fwnode, "clock-lanes", &v))
bus->clock_lane = v;
if (bus_type == V4L2_FWNODE_BUS_TYPE_CCP2)
vep->bus_type = V4L2_MBUS_CCP2;
else
vep->bus_type = V4L2_MBUS_CSI1;
}
/** /**
* v4l2_fwnode_endpoint_parse() - parse all fwnode node properties * v4l2_fwnode_endpoint_parse() - parse all fwnode node properties
* @fwnode: pointer to the endpoint's fwnode handle * @fwnode: pointer to the endpoint's fwnode handle
...@@ -187,6 +212,8 @@ int v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode, ...@@ -187,6 +212,8 @@ int v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode,
fwnode_property_read_u32(fwnode, "bus-type", &bus_type); fwnode_property_read_u32(fwnode, "bus-type", &bus_type);
switch (bus_type) {
case V4L2_FWNODE_BUS_TYPE_GUESS:
rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep); rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep);
if (rval) if (rval)
return rval; return rval;
...@@ -198,6 +225,15 @@ int v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode, ...@@ -198,6 +225,15 @@ int v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode,
v4l2_fwnode_endpoint_parse_parallel_bus(fwnode, vep); v4l2_fwnode_endpoint_parse_parallel_bus(fwnode, vep);
return 0; return 0;
case V4L2_FWNODE_BUS_TYPE_CCP2:
case V4L2_FWNODE_BUS_TYPE_CSI1:
v4l2_fwnode_endpoint_parse_csi1_bus(fwnode, vep, bus_type);
return 0;
default:
pr_warn("unsupported bus type %u\n", bus_type);
return -EINVAL;
}
} }
EXPORT_SYMBOL_GPL(v4l2_fwnode_endpoint_parse); EXPORT_SYMBOL_GPL(v4l2_fwnode_endpoint_parse);
......
...@@ -55,6 +55,24 @@ struct v4l2_fwnode_bus_parallel { ...@@ -55,6 +55,24 @@ struct v4l2_fwnode_bus_parallel {
unsigned char data_shift; unsigned char data_shift;
}; };
/**
* struct v4l2_fwnode_bus_mipi_csi1 - CSI-1/CCP2 data bus structure
* @clock_inv: polarity of clock/strobe signal
* false - not inverted, true - inverted
* @strobe: false - data/clock, true - data/strobe
* @lane_polarity: the polarities of the clock (index 0) and data lanes
index (1)
* @data_lane: the number of the data lane
* @clock_lane: the number of the clock lane
*/
struct v4l2_fwnode_bus_mipi_csi1 {
bool clock_inv;
bool strobe;
bool lane_polarity[2];
unsigned char data_lane;
unsigned char clock_lane;
};
/** /**
* struct v4l2_fwnode_endpoint - the endpoint data structure * struct v4l2_fwnode_endpoint - the endpoint data structure
* @base: fwnode endpoint of the v4l2_fwnode * @base: fwnode endpoint of the v4l2_fwnode
...@@ -72,6 +90,7 @@ struct v4l2_fwnode_endpoint { ...@@ -72,6 +90,7 @@ struct v4l2_fwnode_endpoint {
enum v4l2_mbus_type bus_type; enum v4l2_mbus_type bus_type;
union { union {
struct v4l2_fwnode_bus_parallel parallel; struct v4l2_fwnode_bus_parallel parallel;
struct v4l2_fwnode_bus_mipi_csi1 mipi_csi1;
struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2; struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2;
} bus; } bus;
u64 *link_frequencies; u64 *link_frequencies;
......
...@@ -69,11 +69,15 @@ ...@@ -69,11 +69,15 @@
* @V4L2_MBUS_PARALLEL: parallel interface with hsync and vsync * @V4L2_MBUS_PARALLEL: parallel interface with hsync and vsync
* @V4L2_MBUS_BT656: parallel interface with embedded synchronisation, can * @V4L2_MBUS_BT656: parallel interface with embedded synchronisation, can
* also be used for BT.1120 * also be used for BT.1120
* @V4L2_MBUS_CSI1: MIPI CSI-1 serial interface
* @V4L2_MBUS_CCP2: CCP2 (Compact Camera Port 2)
* @V4L2_MBUS_CSI2: MIPI CSI-2 serial interface * @V4L2_MBUS_CSI2: MIPI CSI-2 serial interface
*/ */
enum v4l2_mbus_type { enum v4l2_mbus_type {
V4L2_MBUS_PARALLEL, V4L2_MBUS_PARALLEL,
V4L2_MBUS_BT656, V4L2_MBUS_BT656,
V4L2_MBUS_CSI1,
V4L2_MBUS_CCP2,
V4L2_MBUS_CSI2, V4L2_MBUS_CSI2,
}; };
......
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