[PATCH] sn: A little re-formatting

From: Pat Gefre <pfg@sgi.com>

A little re-formatting
Added pcibr_lock()

include/asm-ia64/sn/pci/pcibr_private.h

@@ -93,7 +93,7 @@ extern uint32_t pcibr_debug_mask;
  * set, then the overhead for this macro is just an extra 'if' check.
  */
 /* For high frequency events (ie. map allocation, direct translation,...) */
-#if 1 || DEBUG
+#if DEBUG
 #define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args)
 #else	/* DEBUG */
 #define PCIBR_DEBUG(args)
@@ -296,7 +296,8 @@ struct pcibr_intr_wrap_s {
 	((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv)
 /*
  * Defines for individual WARs. Each is a bitmask of applicable
- * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, etc.
+ * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
+ * (3 << 1) == (rev A or rev B), etc
  */
 #define PV854697 (~0)     /* PIC: write 64bit regs as 64bits. permanent */
 #define PV854827 (~0)     /* PIC: fake widget 0xf presence bit. permanent */
@@ -370,6 +371,7 @@ struct pcibr_soft_s {
     short		    bs_int_ate_size;	/* number of internal ates */
     short		    bs_bridge_type;	/* see defines above */
     short		    bs_bridge_mode;	/* see defines above */
+
     int                     bs_rev_num;	/* revision number of Bridge */
 
     /* bs_dma_flags are the forced dma flags used on all DMAs. Used for
@@ -377,6 +379,7 @@ struct pcibr_soft_s {
      */
     unsigned                bs_dma_flags;	/* forced DMA flags */
 
+    nasid_t		    bs_nasid;		/* nasid this bus is on */
     moduleid_t		    bs_moduleid;	/* io brick moduleid */
     short		    bs_bricktype;	/* io brick type */
 
@@ -535,6 +538,10 @@ struct pcibr_soft_s {
 	 * Bridge interrupt bit.
 	 */
 	struct pcibr_intr_wrap_s  bsi_pcibr_intr_wrap;
+	/* The bus and interrupt bit, used for pcibr_setpciint().
+	 * The pci busnum is bit3, int_bits bit2:0
+	 */
+	uint32_t		bsi_int_bit;
 
     } bs_intr[8];
 
@@ -562,9 +569,6 @@ struct pcibr_soft_s {
      */
     struct br_errintr_info {
 	int                     bserr_toutcnt;
-#ifdef LATER
-	toid_t                  bserr_toutid;	/* Timeout started by errintr */
-#endif	/* LATER */
 	iopaddr_t               bserr_addr;	/* Address where error occured */
 	uint64_t		bserr_intstat;	/* interrupts active at error dump */
     } bs_errinfo;
@@ -669,17 +673,17 @@ struct pciio_piospace_s {
     size_t                  count;	/* size of PIO space */
 };
 
-/* Use io spin locks. This ensures that all the PIO writes from a particular
- * CPU to a particular IO device are synched before the start of the next
- * set of PIO operations to the same device.
+/* 
+ * pcibr_soft structure locking macros
  */
-#ifdef PCI_LATER
-#define pcibr_lock(pcibr_soft)		io_splock(pcibr_soft->bs_lock)
-#define pcibr_unlock(pcibr_soft, s)	io_spunlock(pcibr_soft->bs_lock,s)
-#else
-#define pcibr_lock(pcibr_soft)		1
-#define pcibr_unlock(pcibr_soft, s)	
-#endif	/* PCI_LATER */
+inline static unsigned long
+pcibr_lock(pcibr_soft_t pcibr_soft)
+{
+        unsigned long flag;
+        spin_lock_irqsave(&pcibr_soft->bs_lock, flag);
+        return(flag);
+}
+#define pcibr_unlock(pcibr_soft, flag)  spin_unlock_irqrestore(&pcibr_soft->bs_lock, flag)
 
 #define PCIBR_VALID_SLOT(ps, s)     (s < PCIBR_NUM_SLOTS(ps))
 #define PCIBR_D64_BASE_UNSET    (0xFFFFFFFFFFFFFFFF)
@@ -696,8 +700,7 @@ struct pcibr_list_s {
 };
 #endif /* PCIBR_SOFT_LIST */
 
-
-// Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot.
+/* Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. */
 #define DEV_PER_WIDGET (2*2*8)
 
 struct sn_flush_device_list {