Commit 98f29e8d authored by Chris Wilson's avatar Chris Wilson

drm/i915: Record space required for breadcrumb emission

In the next patch, we will use deferred breadcrumb emission. That requires
reserving sufficient space in the ringbuffer to emit the breadcrumb, which
first requires us to know how large the breadcrumb is.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-28-chris@chris-wilson.co.uk
parent 9b81d556
...@@ -434,6 +434,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, ...@@ -434,6 +434,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
* away, e.g. because a GPU scheduler has deferred it. * away, e.g. because a GPU scheduler has deferred it.
*/ */
req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
if (i915.enable_execlists) if (i915.enable_execlists)
ret = intel_logical_ring_alloc_request_extras(req); ret = intel_logical_ring_alloc_request_extras(req);
......
...@@ -1590,6 +1590,8 @@ static int gen8_emit_breadcrumb(struct drm_i915_gem_request *request) ...@@ -1590,6 +1590,8 @@ static int gen8_emit_breadcrumb(struct drm_i915_gem_request *request)
return intel_logical_ring_advance(request); return intel_logical_ring_advance(request);
} }
static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
static int gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request) static int gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request)
{ {
struct intel_ring *ring = request->ring; struct intel_ring *ring = request->ring;
...@@ -1621,6 +1623,8 @@ static int gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request) ...@@ -1621,6 +1623,8 @@ static int gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request)
return intel_logical_ring_advance(request); return intel_logical_ring_advance(request);
} }
static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
static int gen8_init_rcs_context(struct drm_i915_gem_request *req) static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
{ {
int ret; int ret;
...@@ -1695,6 +1699,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) ...@@ -1695,6 +1699,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->reset_hw = reset_common_ring; engine->reset_hw = reset_common_ring;
engine->emit_flush = gen8_emit_flush; engine->emit_flush = gen8_emit_flush;
engine->emit_breadcrumb = gen8_emit_breadcrumb; engine->emit_breadcrumb = gen8_emit_breadcrumb;
engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
engine->submit_request = execlists_submit_request; engine->submit_request = execlists_submit_request;
engine->irq_enable = gen8_logical_ring_enable_irq; engine->irq_enable = gen8_logical_ring_enable_irq;
...@@ -1817,6 +1822,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine) ...@@ -1817,6 +1822,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
engine->init_context = gen8_init_rcs_context; engine->init_context = gen8_init_rcs_context;
engine->emit_flush = gen8_emit_flush_render; engine->emit_flush = gen8_emit_flush_render;
engine->emit_breadcrumb = gen8_emit_breadcrumb_render; engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
ret = intel_engine_create_scratch(engine, 4096); ret = intel_engine_create_scratch(engine, 4096);
if (ret) if (ret)
......
...@@ -1348,6 +1348,8 @@ static int i9xx_emit_breadcrumb(struct drm_i915_gem_request *req) ...@@ -1348,6 +1348,8 @@ static int i9xx_emit_breadcrumb(struct drm_i915_gem_request *req)
return 0; return 0;
} }
static const int i9xx_emit_breadcrumb_sz = 4;
/** /**
* gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers
* *
...@@ -1401,6 +1403,8 @@ static int gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req) ...@@ -1401,6 +1403,8 @@ static int gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req)
return 0; return 0;
} }
static const int gen8_render_emit_breadcrumb_sz = 8;
/** /**
* intel_ring_sync - sync the waiter to the signaller on seqno * intel_ring_sync - sync the waiter to the signaller on seqno
* *
...@@ -2638,8 +2642,21 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, ...@@ -2638,8 +2642,21 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
engine->reset_hw = reset_ring_common; engine->reset_hw = reset_ring_common;
engine->emit_breadcrumb = i9xx_emit_breadcrumb; engine->emit_breadcrumb = i9xx_emit_breadcrumb;
if (i915.semaphores) engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
if (i915.semaphores) {
int num_rings;
engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
if (INTEL_GEN(dev_priv) >= 8) {
engine->emit_breadcrumb_sz += num_rings * 6;
} else {
engine->emit_breadcrumb_sz += num_rings * 3;
if (num_rings & 1)
engine->emit_breadcrumb_sz++;
}
}
engine->submit_request = i9xx_submit_request; engine->submit_request = i9xx_submit_request;
if (INTEL_GEN(dev_priv) >= 8) if (INTEL_GEN(dev_priv) >= 8)
...@@ -2667,9 +2684,17 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) ...@@ -2667,9 +2684,17 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
if (INTEL_GEN(dev_priv) >= 8) { if (INTEL_GEN(dev_priv) >= 8) {
engine->init_context = intel_rcs_ctx_init; engine->init_context = intel_rcs_ctx_init;
engine->emit_breadcrumb = gen8_render_emit_breadcrumb; engine->emit_breadcrumb = gen8_render_emit_breadcrumb;
engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz;
engine->emit_flush = gen8_render_ring_flush; engine->emit_flush = gen8_render_ring_flush;
if (i915.semaphores) if (i915.semaphores) {
int num_rings;
engine->semaphore.signal = gen8_rcs_signal; engine->semaphore.signal = gen8_rcs_signal;
num_rings =
hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
engine->emit_breadcrumb_sz += num_rings * 6;
}
} else if (INTEL_GEN(dev_priv) >= 6) { } else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init; engine->init_context = intel_rcs_ctx_init;
engine->emit_flush = gen7_render_ring_flush; engine->emit_flush = gen7_render_ring_flush;
......
...@@ -256,6 +256,7 @@ struct intel_engine_cs { ...@@ -256,6 +256,7 @@ struct intel_engine_cs {
#define I915_DISPATCH_PINNED BIT(1) #define I915_DISPATCH_PINNED BIT(1)
#define I915_DISPATCH_RS BIT(2) #define I915_DISPATCH_RS BIT(2)
int (*emit_breadcrumb)(struct drm_i915_gem_request *req); int (*emit_breadcrumb)(struct drm_i915_gem_request *req);
int emit_breadcrumb_sz;
/* Pass the request to the hardware queue (e.g. directly into /* Pass the request to the hardware queue (e.g. directly into
* the legacy ringbuffer or to the end of an execlist). * the legacy ringbuffer or to the end of an execlist).
......
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