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Commit 994c77ed authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents 

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220928145609.375860-4-dmitry.baryshkov@linaro.org
parent f565f923
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Showing with 60 additions and 60 deletions
drivers/clk/qcom/gcc-msm8939.c
View file @ 994c77ed
...@@ -614,7 +614,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { ...@@ -614,7 +614,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src", .name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -626,7 +626,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = { ...@@ -626,7 +626,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src", .name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6a_parent_data, .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -638,7 +638,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = { ...@@ -638,7 +638,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src", .name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc_parent_data, .parent_data = gcc_xo_gpll0_bimc_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
}, },
...@@ -651,7 +651,7 @@ static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = { ...@@ -651,7 +651,7 @@ static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "system_mm_noc_bfdcd_clk_src", .name = "system_mm_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6a_parent_data, .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -671,7 +671,7 @@ static struct clk_rcg2 camss_ahb_clk_src = { ...@@ -671,7 +671,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk_src", .name = "camss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -692,7 +692,7 @@ static struct clk_rcg2 apss_ahb_clk_src = { ...@@ -692,7 +692,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src", .name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -711,7 +711,7 @@ static struct clk_rcg2 csi0_clk_src = { ...@@ -711,7 +711,7 @@ static struct clk_rcg2 csi0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src", .name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -724,7 +724,7 @@ static struct clk_rcg2 csi1_clk_src = { ...@@ -724,7 +724,7 @@ static struct clk_rcg2 csi1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src", .name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -753,7 +753,7 @@ static struct clk_rcg2 gfx3d_clk_src = { ...@@ -753,7 +753,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src", .name = "gfx3d_clk_src",
.parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data, .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -782,7 +782,7 @@ static struct clk_rcg2 vfe0_clk_src = { ...@@ -782,7 +782,7 @@ static struct clk_rcg2 vfe0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src", .name = "vfe0_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data, .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -801,7 +801,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { ...@@ -801,7 +801,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src", .name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { ...@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src", .name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { ...@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src", .name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { ...@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src", .name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -866,7 +866,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { ...@@ -866,7 +866,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src", .name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { ...@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src", .name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -893,7 +893,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { ...@@ -893,7 +893,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src", .name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -907,7 +907,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { ...@@ -907,7 +907,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src", .name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -920,7 +920,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { ...@@ -920,7 +920,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src", .name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -934,7 +934,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { ...@@ -934,7 +934,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src", .name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -947,7 +947,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { ...@@ -947,7 +947,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src", .name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -961,7 +961,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { ...@@ -961,7 +961,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src", .name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -994,7 +994,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { ...@@ -994,7 +994,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src", .name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1008,7 +1008,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { ...@@ -1008,7 +1008,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src", .name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1028,7 +1028,7 @@ static struct clk_rcg2 cci_clk_src = { ...@@ -1028,7 +1028,7 @@ static struct clk_rcg2 cci_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src", .name = "cci_clk_src",
.parent_data = gcc_xo_gpll0a_parent_data, .parent_data = gcc_xo_gpll0a_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1048,7 +1048,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { ...@@ -1048,7 +1048,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src", .name = "camss_gp0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1062,7 +1062,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { ...@@ -1062,7 +1062,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src", .name = "camss_gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1082,7 +1082,7 @@ static struct clk_rcg2 jpeg0_clk_src = { ...@@ -1082,7 +1082,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src", .name = "jpeg0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1102,7 +1102,7 @@ static struct clk_rcg2 mclk0_clk_src = { ...@@ -1102,7 +1102,7 @@ static struct clk_rcg2 mclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src", .name = "mclk0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1116,7 +1116,7 @@ static struct clk_rcg2 mclk1_clk_src = { ...@@ -1116,7 +1116,7 @@ static struct clk_rcg2 mclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src", .name = "mclk1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1135,7 +1135,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { ...@@ -1135,7 +1135,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src", .name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1148,7 +1148,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { ...@@ -1148,7 +1148,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src", .name = "csi1phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1171,7 +1171,7 @@ static struct clk_rcg2 cpp_clk_src = { ...@@ -1171,7 +1171,7 @@ static struct clk_rcg2 cpp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src", .name = "cpp_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_parent_data, .parent_data = gcc_xo_gpll0_gpll2_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1193,7 +1193,7 @@ static struct clk_rcg2 crypto_clk_src = { ...@@ -1193,7 +1193,7 @@ static struct clk_rcg2 crypto_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src", .name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1212,7 +1212,7 @@ static struct clk_rcg2 gp1_clk_src = { ...@@ -1212,7 +1212,7 @@ static struct clk_rcg2 gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src", .name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1226,7 +1226,7 @@ static struct clk_rcg2 gp2_clk_src = { ...@@ -1226,7 +1226,7 @@ static struct clk_rcg2 gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src", .name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1240,7 +1240,7 @@ static struct clk_rcg2 gp3_clk_src = { ...@@ -1240,7 +1240,7 @@ static struct clk_rcg2 gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src", .name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1252,7 +1252,7 @@ static struct clk_rcg2 byte0_clk_src = { ...@@ -1252,7 +1252,7 @@ static struct clk_rcg2 byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src", .name = "byte0_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte_parent_data, .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
.ops = &clk_byte2_ops, .ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1265,7 +1265,7 @@ static struct clk_rcg2 byte1_clk_src = { ...@@ -1265,7 +1265,7 @@ static struct clk_rcg2 byte1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src", .name = "byte1_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte_parent_data, .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
.ops = &clk_byte2_ops, .ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1284,7 +1284,7 @@ static struct clk_rcg2 esc0_clk_src = { ...@@ -1284,7 +1284,7 @@ static struct clk_rcg2 esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src", .name = "esc0_clk_src",
.parent_data = gcc_xo_dsibyte_parent_data, .parent_data = gcc_xo_dsibyte_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1297,7 +1297,7 @@ static struct clk_rcg2 esc1_clk_src = { ...@@ -1297,7 +1297,7 @@ static struct clk_rcg2 esc1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src", .name = "esc1_clk_src",
.parent_data = gcc_xo_dsibyte_parent_data, .parent_data = gcc_xo_dsibyte_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1325,7 +1325,7 @@ static struct clk_rcg2 mdp_clk_src = { ...@@ -1325,7 +1325,7 @@ static struct clk_rcg2 mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src", .name = "mdp_clk_src",
.parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data, .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
.num_parents = 6, .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1338,7 +1338,7 @@ static struct clk_rcg2 pclk0_clk_src = { ...@@ -1338,7 +1338,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src", .name = "pclk0_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy_parent_data, .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
.ops = &clk_pixel_ops, .ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1352,7 +1352,7 @@ static struct clk_rcg2 pclk1_clk_src = { ...@@ -1352,7 +1352,7 @@ static struct clk_rcg2 pclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src", .name = "pclk1_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy_parent_data, .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
.ops = &clk_pixel_ops, .ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
...@@ -1371,7 +1371,7 @@ static struct clk_rcg2 vsync_clk_src = { ...@@ -1371,7 +1371,7 @@ static struct clk_rcg2 vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src", .name = "vsync_clk_src",
.parent_data = gcc_xo_gpll0a_parent_data, .parent_data = gcc_xo_gpll0a_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1390,7 +1390,7 @@ static struct clk_rcg2 pdm2_clk_src = { ...@@ -1390,7 +1390,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src", .name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1416,7 +1416,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { ...@@ -1416,7 +1416,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src", .name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_floor_ops,
}, },
}; };
...@@ -1430,7 +1430,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { ...@@ -1430,7 +1430,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src", .name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_floor_ops,
}, },
}; };
...@@ -1450,7 +1450,7 @@ static struct clk_rcg2 apss_tcu_clk_src = { ...@@ -1450,7 +1450,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src", .name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data, .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1473,7 +1473,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = { ...@@ -1473,7 +1473,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "bimc_gpu_clk_src", .name = "bimc_gpu_clk_src",
.parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data, .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
.flags = CLK_GET_RATE_NOCACHE, .flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1494,7 +1494,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { ...@@ -1494,7 +1494,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src", .name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1512,7 +1512,7 @@ static struct clk_rcg2 usb_fs_system_clk_src = { ...@@ -1512,7 +1512,7 @@ static struct clk_rcg2 usb_fs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_system_clk_src", .name = "usb_fs_system_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_parent_data, .parent_data = gcc_xo_gpll6_gpll0_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1530,7 +1530,7 @@ static struct clk_rcg2 usb_fs_ic_clk_src = { ...@@ -1530,7 +1530,7 @@ static struct clk_rcg2 usb_fs_ic_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_ic_clk_src", .name = "usb_fs_ic_clk_src",
.parent_data = gcc_xo_gpll6_gpll0a_parent_data, .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1556,7 +1556,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { ...@@ -1556,7 +1556,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_ahbfabric_clk_src", .name = "ultaudio_ahbfabric_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data, .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1635,7 +1635,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { ...@@ -1635,7 +1635,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_pri_i2s_clk_src", .name = "ultaudio_lpaif_pri_i2s_clk_src",
.parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data, .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1666,7 +1666,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { ...@@ -1666,7 +1666,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_sec_i2s_clk_src", .name = "ultaudio_lpaif_sec_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data, .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1697,7 +1697,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { ...@@ -1697,7 +1697,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_aux_i2s_clk_src", .name = "ultaudio_lpaif_aux_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data, .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1732,7 +1732,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = { ...@@ -1732,7 +1732,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_xo_clk_src", .name = "ultaudio_xo_clk_src",
.parent_data = gcc_xo_sleep_parent_data, .parent_data = gcc_xo_sleep_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1788,7 +1788,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = { ...@@ -1788,7 +1788,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "codec_digcodec_clk_src", .name = "codec_digcodec_clk_src",
.parent_data = gcc_xo_gpll1_emclk_sleep_parent_data, .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -1858,7 +1858,7 @@ static struct clk_rcg2 vcodec0_clk_src = { ...@@ -1858,7 +1858,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src", .name = "vcodec0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data, .parent_data = gcc_xo_gpll0_parent_data,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
......
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