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Commit 9aef85cc authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (21 commits)
  drm: only trust core drm ioctls - driver ioctls are a mess.
  drm/i915: add support for Intel series 4 chipsets.
  drm/radeon: add hier-z registers for r300 and r500 chipsets
  drm/radeon: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT
  drm/radeon: switch IGP gart to use radeon_write_agp_base()
  drm/radeon: Restore sw interrupt on resume
  drm/r500: add support for AGP based cards.
  drm/radeon: fix texture uploads with large 3d textures (bug 13980)
  drm/radeon: add initial r500 support.
  drm/radeon: init pipe setup in kernel code.
  drm/radeon: fixup radeon_do_engine_reset
  drm/radeon: fix pixcache and purge/cache flushing registers
  drm/radeon: write AGP_BASE_2 on chips that support it.
  drm/radeon: merge IGP chip setup and fixup RS400 vs RS480 support
  drm/radeon: IGP clean up register and magic numbers.
  drm/rs690: set base 2 to 0.
  drm/rs690: set all of gart base address.
  radeon: add production microcode from AMD
  drm: pcigart use proper pci map interfaces.
  drm: the sg alloc ioctl should write back the handle to userspace
  ...
parents fdfe6d3d 858a3685
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Showing with 2604 additions and 1070 deletions
drivers/char/drm/ati_pcigart.c
View file @ 9aef85cc
...@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info ...@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
for (i = 0; i < pages; i++) { for (i = 0; i < pages; i++) {
if (!entry->busaddr[i]) if (!entry->busaddr[i])
break; break;
pci_unmap_single(dev->pdev, entry->busaddr[i], pci_unmap_page(dev->pdev, entry->busaddr[i],
PAGE_SIZE, PCI_DMA_TODEVICE); PAGE_SIZE, PCI_DMA_TODEVICE);
} }
...@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga ...@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
for (i = 0; i < pages; i++) { for (i = 0; i < pages; i++) {
/* we need to support large memory configurations */ /* we need to support large memory configurations */
entry->busaddr[i] = pci_map_single(dev->pdev, entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
page_address(entry-> 0, PAGE_SIZE, PCI_DMA_TODEVICE);
pagelist[i]),
PAGE_SIZE, PCI_DMA_TODEVICE);
if (entry->busaddr[i] == 0) { if (entry->busaddr[i] == 0) {
DRM_ERROR("unable to map PCIGART pages!\n"); DRM_ERROR("unable to map PCIGART pages!\n");
drm_ati_pcigart_cleanup(dev, gart_info); drm_ati_pcigart_cleanup(dev, gart_info);
......
drivers/char/drm/drm.h
View file @ 9aef85cc
...@@ -628,7 +628,7 @@ struct drm_set_version { ...@@ -628,7 +628,7 @@ struct drm_set_version {
#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
......
drivers/char/drm/drm_drv.c
View file @ 9aef85cc
...@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp, ...@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
(nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
ioctl = &drm_ioctls[nr]; ioctl = &drm_ioctls[nr];
else cmd = ioctl->cmd;
} else
goto err_i1; goto err_i1;
/* Do not trust userspace, use our own definition */
func = ioctl->func; func = ioctl->func;
/* is there a local override? */ /* is there a local override? */
if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
func = dev->driver->dma_ioctl; func = dev->driver->dma_ioctl;
if (!func) { if (!func) {
DRM_DEBUG("no function\n"); DRM_DEBUG("no function\n");
retcode = -EINVAL; retcode = -EINVAL;
......
drivers/char/drm/drm_pciids.h
View file @ 9aef85cc
...@@ -103,20 +103,18 @@ ...@@ -103,20 +103,18 @@
{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
...@@ -411,4 +409,7 @@ ...@@ -411,4 +409,7 @@
{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0, 0, 0} {0, 0, 0}
drivers/char/drm/i915_drv.h
View file @ 9aef85cc
...@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); ...@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
(dev)->pci_device == 0x29A2 || \ (dev)->pci_device == 0x29A2 || \
(dev)->pci_device == 0x2A02 || \ (dev)->pci_device == 0x2A02 || \
(dev)->pci_device == 0x2A12 || \ (dev)->pci_device == 0x2A12 || \
(dev)->pci_device == 0x2A42) (dev)->pci_device == 0x2A42 || \
(dev)->pci_device == 0x2E02 || \
(dev)->pci_device == 0x2E12 || \
(dev)->pci_device == 0x2E22)
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
(dev)->pci_device == 0x2E12 || \
(dev)->pci_device == 0x2E22)
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
(dev)->pci_device == 0x29B2 || \ (dev)->pci_device == 0x29B2 || \
(dev)->pci_device == 0x29D2) (dev)->pci_device == 0x29D2)
...@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); ...@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
#define PRIMARY_RINGBUFFER_SIZE (128*1024) #define PRIMARY_RINGBUFFER_SIZE (128*1024)
......
drivers/char/drm/r300_cmdbuf.c
View file @ 9aef85cc
...@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev) ...@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R300_RE_CULL_CNTL, 1); ADD_RANGE(R300_RE_CULL_CNTL, 1);
ADD_RANGE(0x42C0, 2); ADD_RANGE(0x42C0, 2);
ADD_RANGE(R300_RS_CNTL_0, 2); ADD_RANGE(R300_RS_CNTL_0, 2);
ADD_RANGE(R300_RS_INTERP_0, 8);
ADD_RANGE(R300_RS_ROUTE_0, 8); ADD_RANGE(R300_SC_HYPERZ, 2);
ADD_RANGE(0x43A4, 2);
ADD_RANGE(0x43E8, 1); ADD_RANGE(0x43E8, 1);
ADD_RANGE(R300_PFS_CNTL_0, 3);
ADD_RANGE(R300_PFS_NODE_0, 4);
ADD_RANGE(R300_PFS_TEXI_0, 64);
ADD_RANGE(0x46A4, 5); ADD_RANGE(0x46A4, 5);
ADD_RANGE(R300_PFS_INSTR0_0, 64);
ADD_RANGE(R300_PFS_INSTR1_0, 64);
ADD_RANGE(R300_PFS_INSTR2_0, 64);
ADD_RANGE(R300_PFS_INSTR3_0, 64);
ADD_RANGE(R300_RE_FOG_STATE, 1); ADD_RANGE(R300_RE_FOG_STATE, 1);
ADD_RANGE(R300_FOG_COLOR_R, 3); ADD_RANGE(R300_FOG_COLOR_R, 3);
ADD_RANGE(R300_PP_ALPHA_TEST, 2); ADD_RANGE(R300_PP_ALPHA_TEST, 2);
...@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev) ...@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(0x4E50, 9); ADD_RANGE(0x4E50, 9);
ADD_RANGE(0x4E88, 1); ADD_RANGE(0x4E88, 1);
ADD_RANGE(0x4EA0, 2); ADD_RANGE(0x4EA0, 2);
ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); ADD_RANGE(R300_ZB_CNTL, 3);
ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); ADD_RANGE(R300_ZB_FORMAT, 4);
ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
ADD_RANGE(0x4F28, 1); ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
ADD_RANGE(0x4F30, 2); ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
ADD_RANGE(0x4F44, 1);
ADD_RANGE(0x4F54, 1);
ADD_RANGE(R300_TX_FILTER_0, 16); ADD_RANGE(R300_TX_FILTER_0, 16);
ADD_RANGE(R300_TX_FILTER1_0, 16); ADD_RANGE(R300_TX_FILTER1_0, 16);
...@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev) ...@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
/* Sporadic registers used as primitives are emitted */ /* Sporadic registers used as primitives are emitted */
ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
ADD_RANGE(0x4074, 16); ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
ADD_RANGE(R500_US_CONFIG, 2);
ADD_RANGE(R500_US_CODE_ADDR, 3);
ADD_RANGE(R500_US_FC_CTRL, 1);
ADD_RANGE(R500_RS_IP_0, 16);
ADD_RANGE(R500_RS_INST_0, 16);
ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
} else {
ADD_RANGE(R300_PFS_CNTL_0, 3);
ADD_RANGE(R300_PFS_NODE_0, 4);
ADD_RANGE(R300_PFS_TEXI_0, 64);
ADD_RANGE(R300_PFS_INSTR0_0, 64);
ADD_RANGE(R300_PFS_INSTR1_0, 64);
ADD_RANGE(R300_PFS_INSTR2_0, 64);
ADD_RANGE(R300_PFS_INSTR3_0, 64);
ADD_RANGE(R300_RS_INTERP_0, 8);
ADD_RANGE(R300_RS_ROUTE_0, 8);
} }
} }
...@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) ...@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
BEGIN_RING(6); BEGIN_RING(6);
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
OUT_RING(0x0); OUT_RING(0x0);
ADVANCE_RING(); ADVANCE_RING();
...@@ -828,6 +840,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, ...@@ -828,6 +840,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
return 0; return 0;
} }
/**
* Uploads user-supplied vertex program instructions or parameters onto
* the graphics card.
* Called by r300_do_cp_cmdbuf.
*/
static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
drm_radeon_kcmd_buffer_t *cmdbuf,
drm_r300_cmd_header_t header)
{
int sz;
int addr;
int type;
int clamp;
int stride;
RING_LOCALS;
sz = header.r500fp.count;
/* address is 9 bits 0 - 8, bit 1 of flags is part of address */
addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
addr |= (type << 16);
addr |= (clamp << 17);
stride = type ? 4 : 6;
DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
if (!sz)
return 0;
if (sz * stride * 4 > cmdbuf->bufsz)
return -EINVAL;
BEGIN_RING(3 + sz * stride);
OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
ADVANCE_RING();
cmdbuf->buf += sz * stride * 4;
cmdbuf->bufsz -= sz * stride * 4;
return 0;
}
/** /**
* Parses and validates a user-supplied command buffer and emits appropriate * Parses and validates a user-supplied command buffer and emits appropriate
* commands on the DMA ring buffer. * commands on the DMA ring buffer.
...@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, ...@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
} }
break; break;
case R300_CMD_R500FP:
if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
DRM_ERROR("Calling r500 command on r300 card\n");
ret = -EINVAL;
goto cleanup;
}
DRM_DEBUG("R300_CMD_R500FP\n");
ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
if (ret) {
DRM_ERROR("r300_emit_r500fp failed\n");
goto cleanup;
}
break;
default: default:
DRM_ERROR("bad cmd_type %i at %p\n", DRM_ERROR("bad cmd_type %i at %p\n",
header.header.cmd_type, header.header.cmd_type,
......
drivers/char/drm/r300_reg.h
View file @ 9aef85cc
...@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. ...@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
/* END: Rasterization / Interpolators - many guesses */ /* END: Rasterization / Interpolators - many guesses */
/* Hierarchical Z Enable */
#define R300_SC_HYPERZ 0x43a4
# define R300_SC_HYPERZ_DISABLE (0 << 0)
# define R300_SC_HYPERZ_ENABLE (1 << 0)
# define R300_SC_HYPERZ_MIN (0 << 1)
# define R300_SC_HYPERZ_MAX (1 << 1)
# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
#define R300_SC_EDGERULE 0x43a8
/* BEGIN: Scissors and cliprects */ /* BEGIN: Scissors and cliprects */
/* There are four clipping rectangles. Their corner coordinates are inclusive. /* There are four clipping rectangles. Their corner coordinates are inclusive.
...@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. ...@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Guess by Vladimir. /* Guess by Vladimir.
* Set to 0A before 3D operations, set to 02 afterwards. * Set to 0A before 3D operations, set to 02 afterwards.
*/ */
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
...@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. ...@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* for this. * for this.
* Bit (1<<8) is the "test" bit. so plain write is 6 - vd * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
*/ */
#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 #define R300_ZB_CNTL 0x4F00
# define R300_RB3D_Z_DISABLED_1 0x00000010 # define R300_STENCIL_ENABLE (1 << 0)
# define R300_RB3D_Z_DISABLED_2 0x00000014 # define R300_Z_ENABLE (1 << 1)
# define R300_RB3D_Z_TEST 0x00000012 # define R300_Z_WRITE_ENABLE (1 << 2)
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 # define R300_Z_SIGNED_COMPARE (1 << 3)
# define R300_RB3D_Z_WRITE_ONLY 0x00000006 # define R300_STENCIL_FRONT_BACK (1 << 4)
# define R300_RB3D_Z_TEST 0x00000012 #define R300_ZB_ZSTENCILCNTL 0x4f04
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
# define R300_RB3D_Z_WRITE_ONLY 0x00000006
# define R300_RB3D_STENCIL_ENABLE 0x00000001
#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
/* functions */ /* functions */
# define R300_ZS_NEVER 0 # define R300_ZS_NEVER 0
# define R300_ZS_LESS 1 # define R300_ZS_LESS 1
...@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. ...@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_ZS_INVERT 5 # define R300_ZS_INVERT 5
# define R300_ZS_INCR_WRAP 6 # define R300_ZS_INCR_WRAP 6
# define R300_ZS_DECR_WRAP 7 # define R300_ZS_DECR_WRAP 7
# define R300_Z_FUNC_SHIFT 0
/* front and back refer to operations done for front /* front and back refer to operations done for front
and back faces, i.e. separate stencil function support */ and back faces, i.e. separate stencil function support */
# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 # define R300_S_FRONT_FUNC_SHIFT 3
# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 # define R300_S_FRONT_SFAIL_OP_SHIFT 6
# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 # define R300_S_FRONT_ZPASS_OP_SHIFT 9
# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 # define R300_S_FRONT_ZFAIL_OP_SHIFT 12
# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 # define R300_S_BACK_FUNC_SHIFT 15
# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 # define R300_S_BACK_SFAIL_OP_SHIFT 18
# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 # define R300_S_BACK_ZPASS_OP_SHIFT 21
# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 # define R300_S_BACK_ZFAIL_OP_SHIFT 24
# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
#define R300_ZB_STENCILREFMASK 0x4f08
#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 # define R300_STENCILREF_SHIFT 0
# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 # define R300_STENCILREF_MASK 0x000000ff
# define R300_RB3D_ZS2_STENCIL_MASK 0xFF # define R300_STENCILMASK_SHIFT 8
# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 # define R300_STENCILMASK_MASK 0x0000ff00
# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 # define R300_STENCILWRITEMASK_SHIFT 16
# define R300_STENCILWRITEMASK_MASK 0x00ff0000
/* gap */ /* gap */
#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 #define R300_ZB_FORMAT 0x4f10
# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) # define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) # define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
/* 16 bit format or some aditional bit ? */ # define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
# define R300_DEPTH_FORMAT_UNK32 (32 << 0) /* reserved up to (15 << 0) */
# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
#define R300_RB3D_EARLY_Z 0x4F14 #define R300_ZB_ZTOP 0x4F14
# define R300_EARLY_Z_DISABLE (0 << 0) # define R300_ZTOP_DISABLE (0 << 0)
# define R300_EARLY_Z_ENABLE (1 << 0) # define R300_ZTOP_ENABLE (1 << 0)
/* gap */ /* gap */
#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
#define R300_ZB_BW_CNTL 0x4f1c
# define R300_HIZ_DISABLE (0 << 0)
# define R300_HIZ_ENABLE (1 << 0)
# define R300_HIZ_MIN (0 << 1)
# define R300_HIZ_MAX (1 << 1)
# define R300_FAST_FILL_DISABLE (0 << 2)
# define R300_FAST_FILL_ENABLE (1 << 2)
# define R300_RD_COMP_DISABLE (0 << 3)
# define R300_RD_COMP_ENABLE (1 << 3)
# define R300_WR_COMP_DISABLE (0 << 4)
# define R300_WR_COMP_ENABLE (1 << 4)
# define R300_ZB_CB_CLEAR_RMW (0 << 5)
# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
# define R500_BMASK_ENABLE (0 << 10)
# define R500_BMASK_DISABLE (1 << 10)
# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
# define R500_PEQ_PACKING_DISABLE (0 << 18)
# define R500_PEQ_PACKING_ENABLE (1 << 18)
# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
/* gap */ /* gap */
#define R300_RB3D_DEPTHOFFSET 0x4F20 /* Z Buffer Address Offset.
#define R300_RB3D_DEPTHPITCH 0x4F24 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ */
# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ #define R300_ZB_DEPTHOFFSET 0x4f20
# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ /* Z Buffer Pitch and Endian Control */
# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ #define R300_ZB_DEPTHPITCH 0x4f24
# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ # define R300_DEPTHPITCH_MASK 0x00003FFC
# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
# define R300_DEPTHMICROTILE_TILED (1 << 17)
# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
/* Z Buffer Clear Value */
#define R300_ZB_DEPTHCLEARVALUE 0x4f28
#define R300_ZB_ZMASK_OFFSET 0x4f30
#define R300_ZB_ZMASK_PITCH 0x4f34
#define R300_ZB_ZMASK_WRINDEX 0x4f38
#define R300_ZB_ZMASK_DWORD 0x4f3c
#define R300_ZB_ZMASK_RDINDEX 0x4f40
/* Hierarchical Z Memory Offset */
#define R300_ZB_HIZ_OFFSET 0x4f44
/* Hierarchical Z Write Index */
#define R300_ZB_HIZ_WRINDEX 0x4f48
/* Hierarchical Z Data */
#define R300_ZB_HIZ_DWORD 0x4f4c
/* Hierarchical Z Read Index */
#define R300_ZB_HIZ_RDINDEX 0x4f50
/* Hierarchical Z Pitch */
#define R300_ZB_HIZ_PITCH 0x4f54
/* Z Buffer Z Pass Counter Data */
#define R300_ZB_ZPASS_DATA 0x4f58
/* Z Buffer Z Pass Counter Address */
#define R300_ZB_ZPASS_ADDR 0x4f5c
/* Depth buffer X and Y coordinate offset */
#define R300_ZB_DEPTHXY_OFFSET 0x4f60
# define R300_DEPTHX_OFFSET_SHIFT 1
# define R300_DEPTHX_OFFSET_MASK 0x000007FE
# define R300_DEPTHY_OFFSET_SHIFT 17
# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
/* Sets the fifo sizes */
#define R500_ZB_FIFO_SIZE 0x4fd0
# define R500_OP_FIFO_SIZE_FULL (0 << 0)
# define R500_OP_FIFO_SIZE_HALF (1 << 0)
# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
/* Stencil Reference Value and Mask for backfacing quads */
/* R300_ZB_STENCILREFMASK handles front face */
#define R500_ZB_STENCILREFMASK_BF 0x4fd4
# define R500_STENCILREF_SHIFT 0
# define R500_STENCILREF_MASK 0x000000ff
# define R500_STENCILMASK_SHIFT 8
# define R500_STENCILMASK_MASK 0x0000ff00
# define R500_STENCILWRITEMASK_SHIFT 16
# define R500_STENCILWRITEMASK_MASK 0x00ff0000
/* BEGIN: Vertex program instruction set */ /* BEGIN: Vertex program instruction set */
...@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. ...@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ */
#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
#define R500_VAP_INDEX_OFFSET 0x208c
#define R500_GA_US_VECTOR_INDEX 0x4250
#define R500_GA_US_VECTOR_DATA 0x4254
#define R500_RS_IP_0 0x4074
#define R500_RS_INST_0 0x4320
#define R500_US_CONFIG 0x4600
#define R500_US_FC_CTRL 0x4624
#define R500_US_CODE_ADDR 0x4630
#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
#endif /* _R300_REG_H */ #endif /* _R300_REG_H */
drivers/char/drm/radeon_cp.c
View file @ 9aef85cc
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
/* /*
* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Fremont, California. * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* Copyright 2007 Advanced Micro Devices, Inc.
* All Rights Reserved. * All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
...@@ -34,789 +35,13 @@ ...@@ -34,789 +35,13 @@
#include "radeon_drv.h" #include "radeon_drv.h"
#include "r300_reg.h" #include "r300_reg.h"
#include "radeon_microcode.h"
#define RADEON_FIFO_DEBUG 0 #define RADEON_FIFO_DEBUG 0
static int radeon_do_cleanup_cp(struct drm_device * dev); static int radeon_do_cleanup_cp(struct drm_device * dev);
/* CP microcode (from ATI) */ static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
static const u32 R200_cp_microcode[][2] = {
{0x21007000, 0000000000},
{0x20007000, 0000000000},
{0x000000ab, 0x00000004},
{0x000000af, 0x00000004},
{0x66544a49, 0000000000},
{0x49494174, 0000000000},
{0x54517d83, 0000000000},
{0x498d8b64, 0000000000},
{0x49494949, 0000000000},
{0x49da493c, 0000000000},
{0x49989898, 0000000000},
{0xd34949d5, 0000000000},
{0x9dc90e11, 0000000000},
{0xce9b9b9b, 0000000000},
{0x000f0000, 0x00000016},
{0x352e232c, 0000000000},
{0x00000013, 0x00000004},
{0x000f0000, 0x00000016},
{0x352e272c, 0000000000},
{0x000f0001, 0x00000016},
{0x3239362f, 0000000000},
{0x000077ef, 0x00000002},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000020, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00000016, 0x00000004},
{0x0003802a, 0x00000002},
{0x040067e0, 0x00000002},
{0x00000016, 0x00000004},
{0x000077e0, 0x00000002},
{0x00065000, 0x00000002},
{0x000037e1, 0x00000002},
{0x040067e1, 0x00000006},
{0x000077e0, 0x00000002},
{0x000077e1, 0x00000002},
{0x000077e1, 0x00000006},
{0xffffffff, 0000000000},
{0x10000000, 0000000000},
{0x0003802a, 0x00000002},
{0x040067e0, 0x00000006},
{0x00007675, 0x00000002},
{0x00007676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0003802b, 0x00000002},
{0x04002676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0000002e, 0x00000018},
{0x0000002e, 0x00000018},
{0000000000, 0x00000006},
{0x0000002f, 0x00000018},
{0x0000002f, 0x00000018},
{0000000000, 0x00000006},
{0x01605000, 0x00000002},
{0x00065000, 0x00000002},
{0x00098000, 0x00000002},
{0x00061000, 0x00000002},
{0x64c0603d, 0x00000004},
{0x00080000, 0x00000016},
{0000000000, 0000000000},
{0x0400251d, 0x00000002},
{0x00007580, 0x00000002},
{0x00067581, 0x00000002},
{0x04002580, 0x00000002},
{0x00067581, 0x00000002},
{0x00000046, 0x00000004},
{0x00005000, 0000000000},
{0x00061000, 0x00000002},
{0x0000750e, 0x00000002},
{0x00019000, 0x00000002},
{0x00011055, 0x00000014},
{0x00000055, 0x00000012},
{0x0400250f, 0x00000002},
{0x0000504a, 0x00000004},
{0x00007565, 0x00000002},
{0x00007566, 0x00000002},
{0x00000051, 0x00000004},
{0x01e655b4, 0x00000002},
{0x4401b0dc, 0x00000002},
{0x01c110dc, 0x00000002},
{0x2666705d, 0x00000018},
{0x040c2565, 0x00000002},
{0x0000005d, 0x00000018},
{0x04002564, 0x00000002},
{0x00007566, 0x00000002},
{0x00000054, 0x00000004},
{0x00401060, 0x00000008},
{0x00101000, 0x00000002},
{0x000d80ff, 0x00000002},
{0x00800063, 0x00000008},
{0x000f9000, 0x00000002},
{0x000e00ff, 0x00000002},
{0000000000, 0x00000006},
{0x00000080, 0x00000018},
{0x00000054, 0x00000004},
{0x00007576, 0x00000002},
{0x00065000, 0x00000002},
{0x00009000, 0x00000002},
{0x00041000, 0x00000002},
{0x0c00350e, 0x00000002},
{0x00049000, 0x00000002},
{0x00051000, 0x00000002},
{0x01e785f8, 0x00000002},
{0x00200000, 0x00000002},
{0x00600073, 0x0000000c},
{0x00007563, 0x00000002},
{0x006075f0, 0x00000021},
{0x20007068, 0x00000004},
{0x00005068, 0x00000004},
{0x00007576, 0x00000002},
{0x00007577, 0x00000002},
{0x0000750e, 0x00000002},
{0x0000750f, 0x00000002},
{0x00a05000, 0x00000002},
{0x00600076, 0x0000000c},
{0x006075f0, 0x00000021},
{0x000075f8, 0x00000002},
{0x00000076, 0x00000004},
{0x000a750e, 0x00000002},
{0x0020750f, 0x00000002},
{0x00600079, 0x00000004},
{0x00007570, 0x00000002},
{0x00007571, 0x00000002},
{0x00007572, 0x00000006},
{0x00005000, 0x00000002},
{0x00a05000, 0x00000002},
{0x00007568, 0x00000002},
{0x00061000, 0x00000002},
{0x00000084, 0x0000000c},
{0x00058000, 0x00000002},
{0x0c607562, 0x00000002},
{0x00000086, 0x00000004},
{0x00600085, 0x00000004},
{0x400070dd, 0000000000},
{0x000380dd, 0x00000002},
{0x00000093, 0x0000001c},
{0x00065095, 0x00000018},
{0x040025bb, 0x00000002},
{0x00061096, 0x00000018},
{0x040075bc, 0000000000},
{0x000075bb, 0x00000002},
{0x000075bc, 0000000000},
{0x00090000, 0x00000006},
{0x00090000, 0x00000002},
{0x000d8002, 0x00000006},
{0x00005000, 0x00000002},
{0x00007821, 0x00000002},
{0x00007800, 0000000000},
{0x00007821, 0x00000002},
{0x00007800, 0000000000},
{0x01665000, 0x00000002},
{0x000a0000, 0x00000002},
{0x000671cc, 0x00000002},
{0x0286f1cd, 0x00000002},
{0x000000a3, 0x00000010},
{0x21007000, 0000000000},
{0x000000aa, 0x0000001c},
{0x00065000, 0x00000002},
{0x000a0000, 0x00000002},
{0x00061000, 0x00000002},
{0x000b0000, 0x00000002},
{0x38067000, 0x00000002},
{0x000a00a6, 0x00000004},
{0x20007000, 0000000000},
{0x01200000, 0x00000002},
{0x20077000, 0x00000002},
{0x01200000, 0x00000002},
{0x20007000, 0000000000},
{0x00061000, 0x00000002},
{0x0120751b, 0x00000002},
{0x8040750a, 0x00000002},
{0x8040750b, 0x00000002},
{0x00110000, 0x00000002},
{0x000380dd, 0x00000002},
{0x000000bd, 0x0000001c},
{0x00061096, 0x00000018},
{0x844075bd, 0x00000002},
{0x00061095, 0x00000018},
{0x840075bb, 0x00000002},
{0x00061096, 0x00000018},
{0x844075bc, 0x00000002},
{0x000000c0, 0x00000004},
{0x804075bd, 0x00000002},
{0x800075bb, 0x00000002},
{0x804075bc, 0x00000002},
{0x00108000, 0x00000002},
{0x01400000, 0x00000002},
{0x006000c4, 0x0000000c},
{0x20c07000, 0x00000020},
{0x000000c6, 0x00000012},
{0x00800000, 0x00000006},
{0x0080751d, 0x00000006},
{0x000025bb, 0x00000002},
{0x000040c0, 0x00000004},
{0x0000775c, 0x00000002},
{0x00a05000, 0x00000002},
{0x00661000, 0x00000002},
{0x0460275d, 0x00000020},
{0x00004000, 0000000000},
{0x00007999, 0x00000002},
{0x00a05000, 0x00000002},
{0x00661000, 0x00000002},
{0x0460299b, 0x00000020},
{0x00004000, 0000000000},
{0x01e00830, 0x00000002},
{0x21007000, 0000000000},
{0x00005000, 0x00000002},
{0x00038042, 0x00000002},
{0x040025e0, 0x00000002},
{0x000075e1, 0000000000},
{0x00000001, 0000000000},
{0x000380d9, 0x00000002},
{0x04007394, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
};
static const u32 radeon_cp_microcode[][2] = {
{0x21007000, 0000000000},
{0x20007000, 0000000000},
{0x000000b4, 0x00000004},
{0x000000b8, 0x00000004},
{0x6f5b4d4c, 0000000000},
{0x4c4c427f, 0000000000},
{0x5b568a92, 0000000000},
{0x4ca09c6d, 0000000000},
{0xad4c4c4c, 0000000000},
{0x4ce1af3d, 0000000000},
{0xd8afafaf, 0000000000},
{0xd64c4cdc, 0000000000},
{0x4cd10d10, 0000000000},
{0x000f0000, 0x00000016},
{0x362f242d, 0000000000},
{0x00000012, 0x00000004},
{0x000f0000, 0x00000016},
{0x362f282d, 0000000000},
{0x000380e7, 0x00000002},
{0x04002c97, 0x00000002},
{0x000f0001, 0x00000016},
{0x333a3730, 0000000000},
{0x000077ef, 0x00000002},
{0x00061000, 0x00000002},
{0x00000021, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000021, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00061000, 0x00000002},
{0x00000021, 0x0000001a},
{0x00004000, 0x0000001e},
{0x00000017, 0x00000004},
{0x0003802b, 0x00000002},
{0x040067e0, 0x00000002},
{0x00000017, 0x00000004},
{0x000077e0, 0x00000002},
{0x00065000, 0x00000002},
{0x000037e1, 0x00000002},
{0x040067e1, 0x00000006},
{0x000077e0, 0x00000002},
{0x000077e1, 0x00000002},
{0x000077e1, 0x00000006},
{0xffffffff, 0000000000},
{0x10000000, 0000000000},
{0x0003802b, 0x00000002},
{0x040067e0, 0x00000006},
{0x00007675, 0x00000002},
{0x00007676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0003802c, 0x00000002},
{0x04002676, 0x00000002},
{0x00007677, 0x00000002},
{0x00007678, 0x00000006},
{0x0000002f, 0x00000018},
{0x0000002f, 0x00000018},
{0000000000, 0x00000006},
{0x00000030, 0x00000018},
{0x00000030, 0x00000018},
{0000000000, 0x00000006},
{0x01605000, 0x00000002},
{0x00065000, 0x00000002},
{0x00098000, 0x00000002},
{0x00061000, 0x00000002},
{0x64c0603e, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00080000, 0x00000016},
{0000000000, 0000000000},
{0x0400251d, 0x00000002},
{0x00007580, 0x00000002},
{0x00067581, 0x00000002},
{0x04002580, 0x00000002},
{0x00067581, 0x00000002},
{0x00000049, 0x00000004},
{0x00005000, 0000000000},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00061000, 0x00000002},
{0x0000750e, 0x00000002},
{0x00019000, 0x00000002},
{0x00011055, 0x00000014},
{0x00000055, 0x00000012},
{0x0400250f, 0x00000002},
{0x0000504f, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00007565, 0x00000002},
{0x00007566, 0x00000002},
{0x00000058, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x01e655b4, 0x00000002},
{0x4401b0e4, 0x00000002},
{0x01c110e4, 0x00000002},
{0x26667066, 0x00000018},
{0x040c2565, 0x00000002},
{0x00000066, 0x00000018},
{0x04002564, 0x00000002},
{0x00007566, 0x00000002},
{0x0000005d, 0x00000004},
{0x00401069, 0x00000008},
{0x00101000, 0x00000002},
{0x000d80ff, 0x00000002},
{0x0080006c, 0x00000008},
{0x000f9000, 0x00000002},
{0x000e00ff, 0x00000002},
{0000000000, 0x00000006},
{0x0000008f, 0x00000018},
{0x0000005b, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00007576, 0x00000002},
{0x00065000, 0x00000002},
{0x00009000, 0x00000002},
{0x00041000, 0x00000002},
{0x0c00350e, 0x00000002},
{0x00049000, 0x00000002},
{0x00051000, 0x00000002},
{0x01e785f8, 0x00000002},
{0x00200000, 0x00000002},
{0x0060007e, 0x0000000c},
{0x00007563, 0x00000002},
{0x006075f0, 0x00000021},
{0x20007073, 0x00000004},
{0x00005073, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00007576, 0x00000002},
{0x00007577, 0x00000002},
{0x0000750e, 0x00000002},
{0x0000750f, 0x00000002},
{0x00a05000, 0x00000002},
{0x00600083, 0x0000000c},
{0x006075f0, 0x00000021},
{0x000075f8, 0x00000002},
{0x00000083, 0x00000004},
{0x000a750e, 0x00000002},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x0020750f, 0x00000002},
{0x00600086, 0x00000004},
{0x00007570, 0x00000002},
{0x00007571, 0x00000002},
{0x00007572, 0x00000006},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00005000, 0x00000002},
{0x00a05000, 0x00000002},
{0x00007568, 0x00000002},
{0x00061000, 0x00000002},
{0x00000095, 0x0000000c},
{0x00058000, 0x00000002},
{0x0c607562, 0x00000002},
{0x00000097, 0x00000004},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x00600096, 0x00000004},
{0x400070e5, 0000000000},
{0x000380e6, 0x00000002},
{0x040025c5, 0x00000002},
{0x000380e5, 0x00000002},
{0x000000a8, 0x0000001c},
{0x000650aa, 0x00000018},
{0x040025bb, 0x00000002},
{0x000610ab, 0x00000018},
{0x040075bc, 0000000000},
{0x000075bb, 0x00000002},
{0x000075bc, 0000000000},
{0x00090000, 0x00000006},
{0x00090000, 0x00000002},
{0x000d8002, 0x00000006},
{0x00007832, 0x00000002},
{0x00005000, 0x00000002},
{0x000380e7, 0x00000002},
{0x04002c97, 0x00000002},
{0x00007820, 0x00000002},
{0x00007821, 0x00000002},
{0x00007800, 0000000000},
{0x01200000, 0x00000002},
{0x20077000, 0x00000002},
{0x01200000, 0x00000002},
{0x20007000, 0x00000002},
{0x00061000, 0x00000002},
{0x0120751b, 0x00000002},
{0x8040750a, 0x00000002},
{0x8040750b, 0x00000002},
{0x00110000, 0x00000002},
{0x000380e5, 0x00000002},
{0x000000c6, 0x0000001c},
{0x000610ab, 0x00000018},
{0x844075bd, 0x00000002},
{0x000610aa, 0x00000018},
{0x840075bb, 0x00000002},
{0x000610ab, 0x00000018},
{0x844075bc, 0x00000002},
{0x000000c9, 0x00000004},
{0x804075bd, 0x00000002},
{0x800075bb, 0x00000002},
{0x804075bc, 0x00000002},
{0x00108000, 0x00000002},
{0x01400000, 0x00000002},
{0x006000cd, 0x0000000c},
{0x20c07000, 0x00000020},
{0x000000cf, 0x00000012},
{0x00800000, 0x00000006},
{0x0080751d, 0x00000006},
{0000000000, 0000000000},
{0x0000775c, 0x00000002},
{0x00a05000, 0x00000002},
{0x00661000, 0x00000002},
{0x0460275d, 0x00000020},
{0x00004000, 0000000000},
{0x01e00830, 0x00000002},
{0x21007000, 0000000000},
{0x6464614d, 0000000000},
{0x69687420, 0000000000},
{0x00000073, 0000000000},
{0000000000, 0000000000},
{0x00005000, 0x00000002},
{0x000380d0, 0x00000002},
{0x040025e0, 0x00000002},
{0x000075e1, 0000000000},
{0x00000001, 0000000000},
{0x000380e0, 0x00000002},
{0x04002394, 0x00000002},
{0x00005000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0x00000008, 0000000000},
{0x00000004, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
};
static const u32 R300_cp_microcode[][2] = {
{0x4200e000, 0000000000},
{0x4000e000, 0000000000},
{0x000000af, 0x00000008},
{0x000000b3, 0x00000008},
{0x6c5a504f, 0000000000},
{0x4f4f497a, 0000000000},
{0x5a578288, 0000000000},
{0x4f91906a, 0000000000},
{0x4f4f4f4f, 0000000000},
{0x4fe24f44, 0000000000},
{0x4f9c9c9c, 0000000000},
{0xdc4f4fde, 0000000000},
{0xa1cd4f4f, 0000000000},
{0xd29d9d9d, 0000000000},
{0x4f0f9fd7, 0000000000},
{0x000ca000, 0x00000004},
{0x000d0012, 0x00000038},
{0x0000e8b4, 0x00000004},
{0x000d0014, 0x00000038},
{0x0000e8b6, 0x00000004},
{0x000d0016, 0x00000038},
{0x0000e854, 0x00000004},
{0x000d0018, 0x00000038},
{0x0000e855, 0x00000004},
{0x000d001a, 0x00000038},
{0x0000e856, 0x00000004},
{0x000d001c, 0x00000038},
{0x0000e857, 0x00000004},
{0x000d001e, 0x00000038},
{0x0000e824, 0x00000004},
{0x000d0020, 0x00000038},
{0x0000e825, 0x00000004},
{0x000d0022, 0x00000038},
{0x0000e830, 0x00000004},
{0x000d0024, 0x00000038},
{0x0000f0c0, 0x00000004},
{0x000d0026, 0x00000038},
{0x0000f0c1, 0x00000004},
{0x000d0028, 0x00000038},
{0x0000f041, 0x00000004},
{0x000d002a, 0x00000038},
{0x0000f184, 0x00000004},
{0x000d002c, 0x00000038},
{0x0000f185, 0x00000004},
{0x000d002e, 0x00000038},
{0x0000f186, 0x00000004},
{0x000d0030, 0x00000038},
{0x0000f187, 0x00000004},
{0x000d0032, 0x00000038},
{0x0000f180, 0x00000004},
{0x000d0034, 0x00000038},
{0x0000f393, 0x00000004},
{0x000d0036, 0x00000038},
{0x0000f38a, 0x00000004},
{0x000d0038, 0x00000038},
{0x0000f38e, 0x00000004},
{0x0000e821, 0x00000004},
{0x0140a000, 0x00000004},
{0x00000043, 0x00000018},
{0x00cce800, 0x00000004},
{0x001b0001, 0x00000004},
{0x08004800, 0x00000004},
{0x001b0001, 0x00000004},
{0x08004800, 0x00000004},
{0x001b0001, 0x00000004},
{0x08004800, 0x00000004},
{0x0000003a, 0x00000008},
{0x0000a000, 0000000000},
{0x02c0a000, 0x00000004},
{0x000ca000, 0x00000004},
{0x00130000, 0x00000004},
{0x000c2000, 0x00000004},
{0xc980c045, 0x00000008},
{0x2000451d, 0x00000004},
{0x0000e580, 0x00000004},
{0x000ce581, 0x00000004},
{0x08004580, 0x00000004},
{0x000ce581, 0x00000004},
{0x0000004c, 0x00000008},
{0x0000a000, 0000000000},
{0x000c2000, 0x00000004},
{0x0000e50e, 0x00000004},
{0x00032000, 0x00000004},
{0x00022056, 0x00000028},
{0x00000056, 0x00000024},
{0x0800450f, 0x00000004},
{0x0000a050, 0x00000008},
{0x0000e565, 0x00000004},
{0x0000e566, 0x00000004},
{0x00000057, 0x00000008},
{0x03cca5b4, 0x00000004},
{0x05432000, 0x00000004},
{0x00022000, 0x00000004},
{0x4ccce063, 0x00000030},
{0x08274565, 0x00000004},
{0x00000063, 0x00000030},
{0x08004564, 0x00000004},
{0x0000e566, 0x00000004},
{0x0000005a, 0x00000008},
{0x00802066, 0x00000010},
{0x00202000, 0x00000004},
{0x001b00ff, 0x00000004},
{0x01000069, 0x00000010},
{0x001f2000, 0x00000004},
{0x001c00ff, 0x00000004},
{0000000000, 0x0000000c},
{0x00000085, 0x00000030},
{0x0000005a, 0x00000008},
{0x0000e576, 0x00000004},
{0x000ca000, 0x00000004},
{0x00012000, 0x00000004},
{0x00082000, 0x00000004},
{0x1800650e, 0x00000004},
{0x00092000, 0x00000004},
{0x000a2000, 0x00000004},
{0x000f0000, 0x00000004},
{0x00400000, 0x00000004},
{0x00000079, 0x00000018},
{0x0000e563, 0x00000004},
{0x00c0e5f9, 0x000000c2},
{0x0000006e, 0x00000008},
{0x0000a06e, 0x00000008},
{0x0000e576, 0x00000004},
{0x0000e577, 0x00000004},
{0x0000e50e, 0x00000004},
{0x0000e50f, 0x00000004},
{0x0140a000, 0x00000004},
{0x0000007c, 0x00000018},
{0x00c0e5f9, 0x000000c2},
{0x0000007c, 0x00000008},
{0x0014e50e, 0x00000004},
{0x0040e50f, 0x00000004},
{0x00c0007f, 0x00000008},
{0x0000e570, 0x00000004},
{0x0000e571, 0x00000004},
{0x0000e572, 0x0000000c},
{0x0000a000, 0x00000004},
{0x0140a000, 0x00000004},
{0x0000e568, 0x00000004},
{0x000c2000, 0x00000004},
{0x00000089, 0x00000018},
{0x000b0000, 0x00000004},
{0x18c0e562, 0x00000004},
{0x0000008b, 0x00000008},
{0x00c0008a, 0x00000008},
{0x000700e4, 0x00000004},
{0x00000097, 0x00000038},
{0x000ca099, 0x00000030},
{0x080045bb, 0x00000004},
{0x000c209a, 0x00000030},
{0x0800e5bc, 0000000000},
{0x0000e5bb, 0x00000004},
{0x0000e5bc, 0000000000},
{0x00120000, 0x0000000c},
{0x00120000, 0x00000004},
{0x001b0002, 0x0000000c},
{0x0000a000, 0x00000004},
{0x0000e821, 0x00000004},
{0x0000e800, 0000000000},
{0x0000e821, 0x00000004},
{0x0000e82e, 0000000000},
{0x02cca000, 0x00000004},
{0x00140000, 0x00000004},
{0x000ce1cc, 0x00000004},
{0x050de1cd, 0x00000004},
{0x000000a7, 0x00000020},
{0x4200e000, 0000000000},
{0x000000ae, 0x00000038},
{0x000ca000, 0x00000004},
{0x00140000, 0x00000004},
{0x000c2000, 0x00000004},
{0x00160000, 0x00000004},
{0x700ce000, 0x00000004},
{0x001400aa, 0x00000008},
{0x4000e000, 0000000000},
{0x02400000, 0x00000004},
{0x400ee000, 0x00000004},
{0x02400000, 0x00000004},
{0x4000e000, 0000000000},
{0x000c2000, 0x00000004},
{0x0240e51b, 0x00000004},
{0x0080e50a, 0x00000005},
{0x0080e50b, 0x00000005},
{0x00220000, 0x00000004},
{0x000700e4, 0x00000004},
{0x000000c1, 0x00000038},
{0x000c209a, 0x00000030},
{0x0880e5bd, 0x00000005},
{0x000c2099, 0x00000030},
{0x0800e5bb, 0x00000005},
{0x000c209a, 0x00000030},
{0x0880e5bc, 0x00000005},
{0x000000c4, 0x00000008},
{0x0080e5bd, 0x00000005},
{0x0000e5bb, 0x00000005},
{0x0080e5bc, 0x00000005},
{0x00210000, 0x00000004},
{0x02800000, 0x00000004},
{0x00c000c8, 0x00000018},
{0x4180e000, 0x00000040},
{0x000000ca, 0x00000024},
{0x01000000, 0x0000000c},
{0x0100e51d, 0x0000000c},
{0x000045bb, 0x00000004},
{0x000080c4, 0x00000008},
{0x0000f3ce, 0x00000004},
{0x0140a000, 0x00000004},
{0x00cc2000, 0x00000004},
{0x08c053cf, 0x00000040},
{0x00008000, 0000000000},
{0x0000f3d2, 0x00000004},
{0x0140a000, 0x00000004},
{0x00cc2000, 0x00000004},
{0x08c053d3, 0x00000040},
{0x00008000, 0000000000},
{0x0000f39d, 0x00000004},
{0x0140a000, 0x00000004},
{0x00cc2000, 0x00000004},
{0x08c0539e, 0x00000040},
{0x00008000, 0000000000},
{0x03c00830, 0x00000004},
{0x4200e000, 0000000000},
{0x0000a000, 0x00000004},
{0x200045e0, 0x00000004},
{0x0000e5e1, 0000000000},
{0x00000001, 0000000000},
{0x000700e1, 0x00000004},
{0x0800e394, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
{0000000000, 0000000000},
};
static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
{ {
u32 ret; u32 ret;
RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
...@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) ...@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
return ret; return ret;
} }
static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
{
u32 ret;
RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
ret = RADEON_READ(RS480_NB_MC_DATA);
RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
return ret;
}
static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
{ {
u32 ret;
RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
return RADEON_READ(RS690_MC_DATA); ret = RADEON_READ(RS690_MC_DATA);
RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
return ret;
}
static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
{
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
return RS690_READ_MCIND(dev_priv, addr);
else
return RS480_READ_MCIND(dev_priv, addr);
} }
u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
{ {
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
else else
return RADEON_READ(RADEON_MC_FB_LOCATION); return RADEON_READ(RADEON_MC_FB_LOCATION);
} }
...@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) ...@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
{ {
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
else else
RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
} }
...@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) ...@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
{ {
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
else else
RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
} }
static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
{
u32 agp_base_hi = upper_32_bits(agp_base);
u32 agp_base_lo = agp_base & 0xffffffff;
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
RADEON_WRITE(RS480_AGP_BASE_2, 0);
} else {
RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
}
}
static int RADEON_READ_PLL(struct drm_device * dev, int addr) static int RADEON_READ_PLL(struct drm_device * dev, int addr)
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
...@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) ...@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
return RADEON_READ(RADEON_PCIE_DATA); return RADEON_READ(RADEON_PCIE_DATA);
} }
static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
{
u32 ret;
RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
ret = RADEON_READ(RADEON_IGPGART_DATA);
RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
return ret;
}
#if RADEON_FIFO_DEBUG #if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv) static void radeon_status(drm_radeon_private_t * dev_priv)
{ {
...@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) ...@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
tmp |= RADEON_RB3D_DC_FLUSH_ALL; tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
for (i = 0; i < dev_priv->usec_timeout; i++) { for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
& RADEON_RB3D_DC_BUSY)) { & RADEON_RB3D_DC_BUSY)) {
return 0; return 0;
}
DRM_UDELAY(1);
}
} else {
/* 3D */
tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
/* 2D */
tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
& RADEON_RB3D_DC_BUSY)) {
return 0;
}
DRM_UDELAY(1);
} }
DRM_UDELAY(1);
} }
#if RADEON_FIFO_DEBUG #if RADEON_FIFO_DEBUG
...@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) ...@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
return -EBUSY; return -EBUSY;
} }
static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
{
uint32_t gb_tile_config, gb_pipe_sel = 0;
/* RS4xx/RS6xx/R4xx/R5xx */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
} else {
/* R3xx */
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
dev_priv->num_gb_pipes = 2;
} else {
/* R3Vxx */
dev_priv->num_gb_pipes = 1;
}
}
DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
switch (dev_priv->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
default:
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
}
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
}
RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
radeon_do_wait_for_idle(dev_priv);
RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
R300_DC_AUTOFLUSH_ENABLE |
R300_DC_DC_DISABLE_IGNORE_PE));
}
/* ================================================================ /* ================================================================
* CP control, initialization * CP control, initialization
*/ */
...@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ...@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
radeon_do_wait_for_idle(dev_priv); radeon_do_wait_for_idle(dev_priv);
RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
if (dev_priv->microcode_version == UCODE_R200) { ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
DRM_INFO("Loading R100 Microcode\n");
for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
R100_cp_microcode[i][1]);
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R100_cp_microcode[i][0]);
}
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
DRM_INFO("Loading R200 Microcode\n"); DRM_INFO("Loading R200 Microcode\n");
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
...@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ...@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R200_cp_microcode[i][0]); R200_cp_microcode[i][0]);
} }
} else if (dev_priv->microcode_version == UCODE_R300) { } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
DRM_INFO("Loading R300 Microcode\n"); DRM_INFO("Loading R300 Microcode\n");
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
...@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ...@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R300_cp_microcode[i][0]); R300_cp_microcode[i][0]);
} }
} else { } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
DRM_INFO("Loading R400 Microcode\n");
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
radeon_cp_microcode[i][1]); R420_cp_microcode[i][1]);
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
radeon_cp_microcode[i][0]); R420_cp_microcode[i][0]);
}
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
DRM_INFO("Loading RS690 Microcode\n");
for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
RS690_cp_microcode[i][1]);
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
RS690_cp_microcode[i][0]);
}
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
DRM_INFO("Loading R500 Microcode\n");
for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
R520_cp_microcode[i][1]);
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R520_cp_microcode[i][0]);
} }
} }
} }
...@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) ...@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
static int radeon_do_engine_reset(struct drm_device * dev) static int radeon_do_engine_reset(struct drm_device * dev)
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
radeon_do_pixcache_flush(dev_priv); radeon_do_pixcache_flush(dev_priv);
if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
/* may need something similar for newer chips */
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
...@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev) ...@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
RADEON_FORCEON_YCLKB | RADEON_FORCEON_YCLKB |
RADEON_FORCEON_MC | RADEON_FORCEON_MC |
RADEON_FORCEON_AIC)); RADEON_FORCEON_AIC));
}
rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_CP |
RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_HI |
RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_SE |
RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_RE |
RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_PP |
RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_E2 |
RADEON_SOFT_RESET_RB)); RADEON_SOFT_RESET_RB));
RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_READ(RADEON_RBBM_SOFT_RESET);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
~(RADEON_SOFT_RESET_CP | ~(RADEON_SOFT_RESET_CP |
RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_HI |
RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_SE |
RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_RE |
RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_PP |
RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_E2 |
RADEON_SOFT_RESET_RB))); RADEON_SOFT_RESET_RB)));
RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_READ(RADEON_RBBM_SOFT_RESET);
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
} }
/* setup the raster pipes */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
radeon_init_pipes(dev_priv);
/* Reset the CP ring */ /* Reset the CP ring */
radeon_do_cp_reset(dev_priv); radeon_do_cp_reset(dev_priv);
...@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, ...@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
#if __OS_HAS_AGP #if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) { if (dev_priv->flags & RADEON_IS_AGP) {
RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); radeon_write_agp_base(dev_priv, dev->agp->base);
radeon_write_agp_location(dev_priv, radeon_write_agp_location(dev_priv,
(((dev_priv->gart_vm_start - 1 + (((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) | dev_priv->gart_size) & 0xffff0000) |
...@@ -1338,103 +711,71 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv) ...@@ -1338,103 +711,71 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
/* Enable or disable IGP GART on the chip */ /* Enable or disable IGP GART on the chip */
static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
{
u32 temp, tmp;
tmp = RADEON_READ(RADEON_AIC_CNTL);
if (on) {
DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
dev_priv->gart_vm_start,
(long)dev_priv->gart_info.bus_addr,
dev_priv->gart_size);
RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
dev_priv->gart_info.bus_addr);
temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
dev_priv->gart_size = 32*1024*1024;
radeon_write_agp_location(dev_priv,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
(dev_priv->gart_vm_start >> 16)));
temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
}
}
/* Enable or disable RS690 GART on the chip */
static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
{ {
u32 temp; u32 temp;
if (on) { if (on) {
DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
dev_priv->gart_vm_start, dev_priv->gart_vm_start,
(long)dev_priv->gart_info.bus_addr, (long)dev_priv->gart_info.bus_addr,
dev_priv->gart_size); dev_priv->gart_size);
temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
RS690_BLOCK_GFX_D3_EN));
else
IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); RS480_VA_SIZE_32MB));
temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
RS480_TLB_ENABLE |
RS480_GTW_LAC_EN |
RS480_1LEVEL_GART));
RS690_WRITE_MCIND(RS690_MC_GART_BASE, temp = dev_priv->gart_info.bus_addr & 0xfffff000;
dev_priv->gart_info.bus_addr); temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
IGP_WRITE_MCIND(RS480_GART_BASE, temp);
temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
RS480_REQ_TYPE_SNOOP_DIS));
RS690_WRITE_MCIND(RS690_MC_AGP_BASE, radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
(unsigned int)dev_priv->gart_vm_start);
dev_priv->gart_size = 32*1024*1024; dev_priv->gart_size = 32*1024*1024;
temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
0xffff0000) | (dev_priv->gart_vm_start >> 16)); 0xffff0000) | (dev_priv->gart_vm_start >> 16));
RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); radeon_write_agp_location(dev_priv, temp);
temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); RS480_VA_SIZE_32MB));
do { do {
temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
if ((temp & RS690_MC_GART_CLEAR_STATUS) == if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
RS690_MC_GART_CLEAR_DONE)
break; break;
DRM_UDELAY(1); DRM_UDELAY(1);
} while (1); } while (1);
RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
RS690_MC_GART_CC_CLEAR); RS480_GART_CACHE_INVALIDATE);
do { do {
temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
if ((temp & RS690_MC_GART_CLEAR_STATUS) == if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
RS690_MC_GART_CLEAR_DONE)
break; break;
DRM_UDELAY(1); DRM_UDELAY(1);
} while (1); } while (1);
RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
RS690_MC_GART_CC_NO_CHANGE);
} else { } else {
RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
} }
} }
...@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) ...@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
{ {
u32 tmp; u32 tmp;
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
radeon_set_rs690gart(dev_priv, on); (dev_priv->flags & RADEON_IS_IGPGART)) {
return;
}
if (dev_priv->flags & RADEON_IS_IGPGART) {
radeon_set_igpgart(dev_priv, on); radeon_set_igpgart(dev_priv, on);
return; return;
} }
...@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev) ...@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
radeon_cp_init_ring_buffer(dev, dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv);
radeon_do_engine_reset(dev); radeon_do_engine_reset(dev);
radeon_enable_interrupt(dev);
DRM_DEBUG("radeon_do_resume_cp() complete\n"); DRM_DEBUG("radeon_do_resume_cp() complete\n");
......
drivers/char/drm/radeon_drm.h
View file @ 9aef85cc
...@@ -240,6 +240,7 @@ typedef union { ...@@ -240,6 +240,7 @@ typedef union {
# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
#define R300_CMD_SCRATCH 8 #define R300_CMD_SCRATCH 8
#define R300_CMD_R500FP 9
typedef union { typedef union {
unsigned int u; unsigned int u;
...@@ -268,6 +269,9 @@ typedef union { ...@@ -268,6 +269,9 @@ typedef union {
struct { struct {
unsigned char cmd_type, reg, n_bufs, flags; unsigned char cmd_type, reg, n_bufs, flags;
} scratch; } scratch;
struct {
unsigned char cmd_type, count, adrlo, adrhi_flags;
} r500fp;
} drm_r300_cmd_header_t; } drm_r300_cmd_header_t;
#define RADEON_FRONT 0x1 #define RADEON_FRONT 0x1
...@@ -278,6 +282,9 @@ typedef union { ...@@ -278,6 +282,9 @@ typedef union {
#define RADEON_USE_HIERZ 0x40000000 #define RADEON_USE_HIERZ 0x40000000
#define RADEON_USE_COMP_ZBUF 0x20000000 #define RADEON_USE_COMP_ZBUF 0x20000000
#define R500FP_CONSTANT_TYPE (1 << 1)
#define R500FP_CONSTANT_CLAMP (1 << 2)
/* Primitive types /* Primitive types
*/ */
#define RADEON_POINTS 0x1 #define RADEON_POINTS 0x1
...@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect { ...@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_CARD_TYPE 12 #define RADEON_PARAM_CARD_TYPE 12
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ #define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
typedef struct drm_radeon_getparam { typedef struct drm_radeon_getparam {
int param; int param;
......
drivers/char/drm/radeon_drv.h
View file @ 9aef85cc
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
#define DRIVER_NAME "radeon" #define DRIVER_NAME "radeon"
#define DRIVER_DESC "ATI Radeon" #define DRIVER_DESC "ATI Radeon"
#define DRIVER_DATE "20060524" #define DRIVER_DATE "20080528"
/* Interface history: /* Interface history:
* *
...@@ -98,9 +98,10 @@ ...@@ -98,9 +98,10 @@
* 1.26- Add support for variable size PCI(E) gart aperture * 1.26- Add support for variable size PCI(E) gart aperture
* 1.27- Add support for IGP GART * 1.27- Add support for IGP GART
* 1.28- Add support for VBL on CRTC2 * 1.28- Add support for VBL on CRTC2
* 1.29- R500 3D cmd buffer support
*/ */
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 28 #define DRIVER_MINOR 29
#define DRIVER_PATCHLEVEL 0 #define DRIVER_PATCHLEVEL 0
/* /*
...@@ -122,7 +123,7 @@ enum radeon_family { ...@@ -122,7 +123,7 @@ enum radeon_family {
CHIP_RV380, CHIP_RV380,
CHIP_R420, CHIP_R420,
CHIP_RV410, CHIP_RV410,
CHIP_RS400, CHIP_RS480,
CHIP_RS690, CHIP_RS690,
CHIP_RV515, CHIP_RV515,
CHIP_R520, CHIP_R520,
...@@ -294,6 +295,7 @@ typedef struct drm_radeon_private { ...@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
int vblank_crtc; int vblank_crtc;
uint32_t irq_enable_reg; uint32_t irq_enable_reg;
int irq_enabled; int irq_enabled;
uint32_t r500_disp_irq_reg;
struct radeon_surface surfaces[RADEON_MAX_SURFACES]; struct radeon_surface surfaces[RADEON_MAX_SURFACES];
struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
...@@ -307,6 +309,8 @@ typedef struct drm_radeon_private { ...@@ -307,6 +309,8 @@ typedef struct drm_radeon_private {
/* starting from here on, data is preserved accross an open */ /* starting from here on, data is preserved accross an open */
uint32_t flags; /* see radeon_chip_flags */ uint32_t flags; /* see radeon_chip_flags */
unsigned long fb_aper_offset; unsigned long fb_aper_offset;
int num_gb_pipes;
} drm_radeon_private_t; } drm_radeon_private_t;
typedef struct drm_radeon_buf_priv { typedef struct drm_radeon_buf_priv {
...@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); ...@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
extern void radeon_driver_irq_preinstall(struct drm_device * dev); extern void radeon_driver_irq_preinstall(struct drm_device * dev);
extern void radeon_driver_irq_postinstall(struct drm_device * dev); extern void radeon_driver_irq_postinstall(struct drm_device * dev);
extern void radeon_driver_irq_uninstall(struct drm_device * dev); extern void radeon_driver_irq_uninstall(struct drm_device * dev);
extern void radeon_enable_interrupt(struct drm_device *dev);
extern int radeon_vblank_crtc_get(struct drm_device *dev); extern int radeon_vblank_crtc_get(struct drm_device *dev);
extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
...@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_PCIE_DATA 0x0034 #define RADEON_PCIE_DATA 0x0034
#define RADEON_PCIE_TX_GART_CNTL 0x10 #define RADEON_PCIE_TX_GART_CNTL 0x10
# define RADEON_PCIE_TX_GART_EN (1 << 0) # define RADEON_PCIE_TX_GART_EN (1 << 0)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
#define RADEON_PCIE_TX_GART_BASE 0x13 #define RADEON_PCIE_TX_GART_BASE 0x13
...@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_PCIE_TX_GART_END_LO 0x16 #define RADEON_PCIE_TX_GART_END_LO 0x16
#define RADEON_PCIE_TX_GART_END_HI 0x17 #define RADEON_PCIE_TX_GART_END_HI 0x17
#define RADEON_IGPGART_INDEX 0x168 #define RS480_NB_MC_INDEX 0x168
#define RADEON_IGPGART_DATA 0x16c # define RS480_NB_MC_IND_WR_EN (1 << 8)
#define RADEON_IGPGART_UNK_18 0x18 #define RS480_NB_MC_DATA 0x16c
#define RADEON_IGPGART_CTRL 0x2b
#define RADEON_IGPGART_BASE_ADDR 0x2c
#define RADEON_IGPGART_FLUSH 0x2e
#define RADEON_IGPGART_ENABLE 0x38
#define RADEON_IGPGART_UNK_39 0x39
#define RS690_MC_INDEX 0x78 #define RS690_MC_INDEX 0x78
# define RS690_MC_INDEX_MASK 0x1ff # define RS690_MC_INDEX_MASK 0x1ff
...@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define RS690_MC_INDEX_WR_ACK 0x7f # define RS690_MC_INDEX_WR_ACK 0x7f
#define RS690_MC_DATA 0x7c #define RS690_MC_DATA 0x7c
#define RS690_MC_MISC_CNTL 0x18 /* MC indirect registers */
#define RS690_MC_GART_FEATURE_ID 0x2b #define RS480_MC_MISC_CNTL 0x18
#define RS690_MC_GART_BASE 0x2c # define RS480_DISABLE_GTW (1 << 1)
#define RS690_MC_GART_CACHE_CNTL 0x2e /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
# define RS690_MC_GART_CC_NO_CHANGE 0x0 # define RS480_GART_INDEX_REG_EN (1 << 12)
# define RS690_MC_GART_CC_CLEAR 0x1 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
# define RS690_MC_GART_CLEAR_STATUS (1 << 1) #define RS480_K8_FB_LOCATION 0x1e
# define RS690_MC_GART_CLEAR_DONE (0 << 1) #define RS480_GART_FEATURE_ID 0x2b
# define RS690_MC_GART_CLEAR_PENDING (1 << 1) # define RS480_HANG_EN (1 << 11)
#define RS690_MC_AGP_SIZE 0x38 # define RS480_TLB_ENABLE (1 << 18)
# define RS690_MC_GART_DIS 0x0 # define RS480_P2P_ENABLE (1 << 19)
# define RS690_MC_GART_EN 0x1 # define RS480_GTW_LAC_EN (1 << 25)
# define RS690_MC_AGP_SIZE_32MB (0 << 1) # define RS480_2LEVEL_GART (0 << 30)
# define RS690_MC_AGP_SIZE_64MB (1 << 1) # define RS480_1LEVEL_GART (1 << 30)
# define RS690_MC_AGP_SIZE_128MB (2 << 1) # define RS480_PDC_EN (1 << 31)
# define RS690_MC_AGP_SIZE_256MB (3 << 1) #define RS480_GART_BASE 0x2c
# define RS690_MC_AGP_SIZE_512MB (4 << 1) #define RS480_GART_CACHE_CNTRL 0x2e
# define RS690_MC_AGP_SIZE_1GB (5 << 1) # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
# define RS690_MC_AGP_SIZE_2GB (6 << 1) #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
#define RS690_MC_AGP_MODE_CONTROL 0x39 # define RS480_GART_EN (1 << 0)
# define RS480_VA_SIZE_32MB (0 << 1)
# define RS480_VA_SIZE_64MB (1 << 1)
# define RS480_VA_SIZE_128MB (2 << 1)
# define RS480_VA_SIZE_256MB (3 << 1)
# define RS480_VA_SIZE_512MB (4 << 1)
# define RS480_VA_SIZE_1GB (5 << 1)
# define RS480_VA_SIZE_2GB (6 << 1)
#define RS480_AGP_MODE_CNTL 0x39
# define RS480_POST_GART_Q_SIZE (1 << 18)
# define RS480_NONGART_SNOOP (1 << 19)
# define RS480_AGP_RD_BUF_SIZE (1 << 20)
# define RS480_REQ_TYPE_SNOOP_SHIFT 22
# define RS480_REQ_TYPE_SNOOP_MASK 0x3
# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
#define RS480_MC_MISC_UMA_CNTL 0x5f
#define RS480_MC_MCLK_CNTL 0x7a
#define RS480_MC_UMA_DUALCH_CNTL 0x86
#define RS690_MC_FB_LOCATION 0x100 #define RS690_MC_FB_LOCATION 0x100
#define RS690_MC_AGP_LOCATION 0x101 #define RS690_MC_AGP_LOCATION 0x101
#define RS690_MC_AGP_BASE 0x102 #define RS690_MC_AGP_BASE 0x102
#define RS690_MC_AGP_BASE_2 0x103
#define R520_MC_IND_INDEX 0x70 #define R520_MC_IND_INDEX 0x70
#define R520_MC_IND_WR_EN (1<<24) #define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74 #define R520_MC_IND_DATA 0x74
#define RV515_MC_FB_LOCATION 0x01 #define RV515_MC_FB_LOCATION 0x01
#define RV515_MC_AGP_LOCATION 0x02 #define RV515_MC_AGP_LOCATION 0x02
#define RV515_MC_AGP_BASE 0x03
#define RV515_MC_AGP_BASE_2 0x04
#define R520_MC_FB_LOCATION 0x04 #define R520_MC_FB_LOCATION 0x04
#define R520_MC_AGP_LOCATION 0x05 #define R520_MC_AGP_LOCATION 0x05
#define R520_MC_AGP_BASE 0x06
#define R520_MC_AGP_BASE_2 0x07
#define RADEON_MPP_TB_CONFIG 0x01c0 #define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
#define RS480_AGP_BASE_2 0x0164
#define RADEON_AGP_BASE 0x0170 #define RADEON_AGP_BASE 0x0170
/* pipe config regs */
#define R400_GB_PIPE_SELECT 0x402c
#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
#define R500_SU_REG_DEST 0x42c8
#define R300_GB_TILE_CONFIG 0x4018
# define R300_ENABLE_TILING (1 << 0)
# define R300_PIPE_COUNT_RV350 (0 << 1)
# define R300_PIPE_COUNT_R300 (3 << 1)
# define R300_PIPE_COUNT_R420_3P (6 << 1)
# define R300_PIPE_COUNT_R420 (7 << 1)
# define R300_TILE_SIZE_8 (0 << 4)
# define R300_TILE_SIZE_16 (1 << 4)
# define R300_TILE_SIZE_32 (2 << 4)
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_DST_PIPE_CONFIG 0x170c
# define R300_PIPE_AUTO_CONFIG (1 << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
#define RADEON_RB3D_COLOROFFSET 0x1c40 #define RADEON_RB3D_COLOROFFSET 0x1c40
#define RADEON_RB3D_COLORPITCH 0x1c48 #define RADEON_RB3D_COLORPITCH 0x1c48
...@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_PP_TXFILTER_1 0x1c6c #define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84 #define RADEON_PP_TXFILTER_2 0x1c84
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
# define RADEON_RB2D_DC_FLUSH (3 << 0) #define R300_DSTCACHE_CTLSTAT 0x1714
# define RADEON_RB2D_DC_FREE (3 << 2) # define R300_RB2D_DC_FLUSH (3 << 0)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf # define R300_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_BUSY (1 << 31) # define R300_RB2D_DC_FLUSH_ALL 0xf
# define R300_RB2D_DC_BUSY (1 << 31)
#define RADEON_RB3D_CNTL 0x1c3c #define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1) # define RADEON_PLANE_MASK_ENABLE (1 << 1)
...@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define RADEON_RB3D_ZC_FREE (1 << 2) # define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
# define RADEON_RB3D_ZC_BUSY (1 << 31) # define RADEON_RB3D_ZC_BUSY (1 << 31)
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_FLUSH_ALL 0x3
# define R300_ZC_BUSY (1 << 31)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
# define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf # define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31) # define RADEON_RB3D_DC_BUSY (1 << 31)
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FINISH (1 << 4)
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4) # define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4) # define RADEON_Z_TEST_ALWAYS (7 << 4)
...@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define R200_VAP_PVS_CNTL_1 0x22D0 #define R200_VAP_PVS_CNTL_1 0x22D0
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
#define R500_D1CRTC_FRAME_COUNT 0x60a4
#define R500_D2CRTC_FRAME_COUNT 0x68a4
#define R500_D1MODE_V_COUNTER 0x6530
#define R500_D2MODE_V_COUNTER 0x6d30
#define R500_D1MODE_VBLANK_STATUS 0x6534
#define R500_D2MODE_VBLANK_STATUS 0x6d34
#define R500_VBLANK_OCCURED (1<<0)
#define R500_VBLANK_ACK (1<<4)
#define R500_VBLANK_STAT (1<<12)
#define R500_VBLANK_INT (1<<16)
#define R500_DxMODE_INT_MASK 0x6540
#define R500_D1MODE_INT_MASK (1<<0)
#define R500_D2MODE_INT_MASK (1<<8)
#define R500_DISP_INTERRUPT_STATUS 0x7edc
#define R500_D1_VBLANK_INTERRUPT (1 << 4)
#define R500_D2_VBLANK_INTERRUPT (1 << 5)
/* Constants */ /* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
...@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, ...@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
#define RADEON_WRITE_PLL( addr, val ) \ #define RADEON_WRITE_PLL(addr, val) \
do { \ do { \
RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
} while (0) } while (0)
#define RADEON_WRITE_IGPGART( addr, val ) \ #define RADEON_WRITE_PCIE(addr, val) \
do { \ do { \
RADEON_WRITE( RADEON_IGPGART_INDEX, \ RADEON_WRITE8(RADEON_PCIE_INDEX, \
((addr) & 0x7f) | (1 << 8)); \ ((addr) & 0xff)); \
RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
} while (0) } while (0)
#define RADEON_WRITE_PCIE( addr, val ) \ #define R500_WRITE_MCIND(addr, val) \
do { \ do { \
RADEON_WRITE8( RADEON_PCIE_INDEX, \ RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
((addr) & 0xff)); \ RADEON_WRITE(R520_MC_IND_DATA, (val)); \
RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ RADEON_WRITE(R520_MC_IND_INDEX, 0); \
} while (0) } while (0)
#define RADEON_WRITE_MCIND( addr, val ) \ #define RS480_WRITE_MCIND(addr, val) \
do { \ do { \
RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ RADEON_WRITE(RS480_NB_MC_INDEX, \
RADEON_WRITE(R520_MC_IND_DATA, (val)); \ ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
RADEON_WRITE(R520_MC_IND_INDEX, 0); \ RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
} while (0) RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
} while (0)
#define RS690_WRITE_MCIND( addr, val ) \ #define RS690_WRITE_MCIND(addr, val) \
do { \ do { \
RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
RADEON_WRITE(RS690_MC_DATA, val); \ RADEON_WRITE(RS690_MC_DATA, val); \
RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
} while (0) } while (0)
#define IGP_WRITE_MCIND(addr, val) \
do { \
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
RS690_WRITE_MCIND(addr, val); \
else \
RS480_WRITE_MCIND(addr, val); \
} while (0)
#define CP_PACKET0( reg, n ) \ #define CP_PACKET0( reg, n ) \
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
#define CP_PACKET0_TABLE( reg, n ) \ #define CP_PACKET0_TABLE( reg, n ) \
...@@ -1154,23 +1241,43 @@ do { \ ...@@ -1154,23 +1241,43 @@ do { \
} while (0) } while (0)
#define RADEON_FLUSH_CACHE() do { \ #define RADEON_FLUSH_CACHE() do { \
OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
OUT_RING( RADEON_RB3D_DC_FLUSH ); \ OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
OUT_RING(RADEON_RB3D_DC_FLUSH); \
} else { \
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
OUT_RING(RADEON_RB3D_DC_FLUSH); \
} \
} while (0) } while (0)
#define RADEON_PURGE_CACHE() do { \ #define RADEON_PURGE_CACHE() do { \
OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
} else { \
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
} \
} while (0) } while (0)
#define RADEON_FLUSH_ZCACHE() do { \ #define RADEON_FLUSH_ZCACHE() do { \
OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
OUT_RING(RADEON_RB3D_ZC_FLUSH); \
} else { \
OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
OUT_RING(R300_ZC_FLUSH); \
} \
} while (0) } while (0)
#define RADEON_PURGE_ZCACHE() do { \ #define RADEON_PURGE_ZCACHE() do { \
OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
} else { \
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
OUT_RING(R300_ZC_FLUSH_ALL); \
} \
} while (0) } while (0)
/* ================================================================ /* ================================================================
......
drivers/char/drm/radeon_irq.c
View file @ 9aef85cc
...@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr ...@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
return radeon_wait_irq(dev, irqwait->irq_seq); return radeon_wait_irq(dev, irqwait->irq_seq);
} }
static void radeon_enable_interrupt(struct drm_device *dev) void radeon_enable_interrupt(struct drm_device *dev)
{ {
drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
......
drivers/char/drm/radeon_microcode.h 0 → 100644
View file @ 9aef85cc
/*
* Copyright 2007 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef RADEON_MICROCODE_H
#define RADEON_MICROCODE_H
/* production radeon ucode r1xx-r6xx */
static const u32 R100_cp_microcode[][2] = {
{ 0x21007000, 0000000000 },
{ 0x20007000, 0000000000 },
{ 0x000000b4, 0x00000004 },
{ 0x000000b8, 0x00000004 },
{ 0x6f5b4d4c, 0000000000 },
{ 0x4c4c427f, 0000000000 },
{ 0x5b568a92, 0000000000 },
{ 0x4ca09c6d, 0000000000 },
{ 0xad4c4c4c, 0000000000 },
{ 0x4ce1af3d, 0000000000 },
{ 0xd8afafaf, 0000000000 },
{ 0xd64c4cdc, 0000000000 },
{ 0x4cd10d10, 0000000000 },
{ 0x000f0000, 0x00000016 },
{ 0x362f242d, 0000000000 },
{ 0x00000012, 0x00000004 },
{ 0x000f0000, 0x00000016 },
{ 0x362f282d, 0000000000 },
{ 0x000380e7, 0x00000002 },
{ 0x04002c97, 0x00000002 },
{ 0x000f0001, 0x00000016 },
{ 0x333a3730, 0000000000 },
{ 0x000077ef, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x00000021, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00061000, 0x00000002 },
{ 0x00000021, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00061000, 0x00000002 },
{ 0x00000021, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00000017, 0x00000004 },
{ 0x0003802b, 0x00000002 },
{ 0x040067e0, 0x00000002 },
{ 0x00000017, 0x00000004 },
{ 0x000077e0, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x000037e1, 0x00000002 },
{ 0x040067e1, 0x00000006 },
{ 0x000077e0, 0x00000002 },
{ 0x000077e1, 0x00000002 },
{ 0x000077e1, 0x00000006 },
{ 0xffffffff, 0000000000 },
{ 0x10000000, 0000000000 },
{ 0x0003802b, 0x00000002 },
{ 0x040067e0, 0x00000006 },
{ 0x00007675, 0x00000002 },
{ 0x00007676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0003802c, 0x00000002 },
{ 0x04002676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0000002f, 0x00000018 },
{ 0x0000002f, 0x00000018 },
{ 0000000000, 0x00000006 },
{ 0x00000030, 0x00000018 },
{ 0x00000030, 0x00000018 },
{ 0000000000, 0x00000006 },
{ 0x01605000, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x00098000, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x64c0603e, 0x00000004 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00080000, 0x00000016 },
{ 0000000000, 0000000000 },
{ 0x0400251d, 0x00000002 },
{ 0x00007580, 0x00000002 },
{ 0x00067581, 0x00000002 },
{ 0x04002580, 0x00000002 },
{ 0x00067581, 0x00000002 },
{ 0x00000049, 0x00000004 },
{ 0x00005000, 0000000000 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x0000750e, 0x00000002 },
{ 0x00019000, 0x00000002 },
{ 0x00011055, 0x00000014 },
{ 0x00000055, 0x00000012 },
{ 0x0400250f, 0x00000002 },
{ 0x0000504f, 0x00000004 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00007565, 0x00000002 },
{ 0x00007566, 0x00000002 },
{ 0x00000058, 0x00000004 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x01e655b4, 0x00000002 },
{ 0x4401b0e4, 0x00000002 },
{ 0x01c110e4, 0x00000002 },
{ 0x26667066, 0x00000018 },
{ 0x040c2565, 0x00000002 },
{ 0x00000066, 0x00000018 },
{ 0x04002564, 0x00000002 },
{ 0x00007566, 0x00000002 },
{ 0x0000005d, 0x00000004 },
{ 0x00401069, 0x00000008 },
{ 0x00101000, 0x00000002 },
{ 0x000d80ff, 0x00000002 },
{ 0x0080006c, 0x00000008 },
{ 0x000f9000, 0x00000002 },
{ 0x000e00ff, 0x00000002 },
{ 0000000000, 0x00000006 },
{ 0x0000008f, 0x00000018 },
{ 0x0000005b, 0x00000004 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00007576, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x00009000, 0x00000002 },
{ 0x00041000, 0x00000002 },
{ 0x0c00350e, 0x00000002 },
{ 0x00049000, 0x00000002 },
{ 0x00051000, 0x00000002 },
{ 0x01e785f8, 0x00000002 },
{ 0x00200000, 0x00000002 },
{ 0x0060007e, 0x0000000c },
{ 0x00007563, 0x00000002 },
{ 0x006075f0, 0x00000021 },
{ 0x20007073, 0x00000004 },
{ 0x00005073, 0x00000004 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00007576, 0x00000002 },
{ 0x00007577, 0x00000002 },
{ 0x0000750e, 0x00000002 },
{ 0x0000750f, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00600083, 0x0000000c },
{ 0x006075f0, 0x00000021 },
{ 0x000075f8, 0x00000002 },
{ 0x00000083, 0x00000004 },
{ 0x000a750e, 0x00000002 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x0020750f, 0x00000002 },
{ 0x00600086, 0x00000004 },
{ 0x00007570, 0x00000002 },
{ 0x00007571, 0x00000002 },
{ 0x00007572, 0x00000006 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00005000, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00007568, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x00000095, 0x0000000c },
{ 0x00058000, 0x00000002 },
{ 0x0c607562, 0x00000002 },
{ 0x00000097, 0x00000004 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x00600096, 0x00000004 },
{ 0x400070e5, 0000000000 },
{ 0x000380e6, 0x00000002 },
{ 0x040025c5, 0x00000002 },
{ 0x000380e5, 0x00000002 },
{ 0x000000a8, 0x0000001c },
{ 0x000650aa, 0x00000018 },
{ 0x040025bb, 0x00000002 },
{ 0x000610ab, 0x00000018 },
{ 0x040075bc, 0000000000 },
{ 0x000075bb, 0x00000002 },
{ 0x000075bc, 0000000000 },
{ 0x00090000, 0x00000006 },
{ 0x00090000, 0x00000002 },
{ 0x000d8002, 0x00000006 },
{ 0x00007832, 0x00000002 },
{ 0x00005000, 0x00000002 },
{ 0x000380e7, 0x00000002 },
{ 0x04002c97, 0x00000002 },
{ 0x00007820, 0x00000002 },
{ 0x00007821, 0x00000002 },
{ 0x00007800, 0000000000 },
{ 0x01200000, 0x00000002 },
{ 0x20077000, 0x00000002 },
{ 0x01200000, 0x00000002 },
{ 0x20007000, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x0120751b, 0x00000002 },
{ 0x8040750a, 0x00000002 },
{ 0x8040750b, 0x00000002 },
{ 0x00110000, 0x00000002 },
{ 0x000380e5, 0x00000002 },
{ 0x000000c6, 0x0000001c },
{ 0x000610ab, 0x00000018 },
{ 0x844075bd, 0x00000002 },
{ 0x000610aa, 0x00000018 },
{ 0x840075bb, 0x00000002 },
{ 0x000610ab, 0x00000018 },
{ 0x844075bc, 0x00000002 },
{ 0x000000c9, 0x00000004 },
{ 0x804075bd, 0x00000002 },
{ 0x800075bb, 0x00000002 },
{ 0x804075bc, 0x00000002 },
{ 0x00108000, 0x00000002 },
{ 0x01400000, 0x00000002 },
{ 0x006000cd, 0x0000000c },
{ 0x20c07000, 0x00000020 },
{ 0x000000cf, 0x00000012 },
{ 0x00800000, 0x00000006 },
{ 0x0080751d, 0x00000006 },
{ 0000000000, 0000000000 },
{ 0x0000775c, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00661000, 0x00000002 },
{ 0x0460275d, 0x00000020 },
{ 0x00004000, 0000000000 },
{ 0x01e00830, 0x00000002 },
{ 0x21007000, 0000000000 },
{ 0x6464614d, 0000000000 },
{ 0x69687420, 0000000000 },
{ 0x00000073, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x00005000, 0x00000002 },
{ 0x000380d0, 0x00000002 },
{ 0x040025e0, 0x00000002 },
{ 0x000075e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000380e0, 0x00000002 },
{ 0x04002394, 0x00000002 },
{ 0x00005000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x00000008, 0000000000 },
{ 0x00000004, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32 R200_cp_microcode[][2] = {
{ 0x21007000, 0000000000 },
{ 0x20007000, 0000000000 },
{ 0x000000bf, 0x00000004 },
{ 0x000000c3, 0x00000004 },
{ 0x7a685e5d, 0000000000 },
{ 0x5d5d5588, 0000000000 },
{ 0x68659197, 0000000000 },
{ 0x5da19f78, 0000000000 },
{ 0x5d5d5d5d, 0000000000 },
{ 0x5dee5d50, 0000000000 },
{ 0xf2acacac, 0000000000 },
{ 0xe75df9e9, 0000000000 },
{ 0xb1dd0e11, 0000000000 },
{ 0xe2afafaf, 0000000000 },
{ 0x000f0000, 0x00000016 },
{ 0x452f232d, 0000000000 },
{ 0x00000013, 0x00000004 },
{ 0x000f0000, 0x00000016 },
{ 0x452f272d, 0000000000 },
{ 0x000f0001, 0x00000016 },
{ 0x3e4d4a37, 0000000000 },
{ 0x000077ef, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x00000020, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00061000, 0x00000002 },
{ 0x00000020, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00061000, 0x00000002 },
{ 0x00000020, 0x0000001a },
{ 0x00004000, 0x0000001e },
{ 0x00000016, 0x00000004 },
{ 0x0003802a, 0x00000002 },
{ 0x040067e0, 0x00000002 },
{ 0x00000016, 0x00000004 },
{ 0x000077e0, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x000037e1, 0x00000002 },
{ 0x040067e1, 0x00000006 },
{ 0x000077e0, 0x00000002 },
{ 0x000077e1, 0x00000002 },
{ 0x000077e1, 0x00000006 },
{ 0xffffffff, 0000000000 },
{ 0x10000000, 0000000000 },
{ 0x07f007f0, 0000000000 },
{ 0x0003802a, 0x00000002 },
{ 0x040067e0, 0x00000006 },
{ 0x0003802c, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002743, 0x00000002 },
{ 0x00007675, 0x00000002 },
{ 0x00007676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0003802c, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002743, 0x00000002 },
{ 0x00007676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0003802b, 0x00000002 },
{ 0x04002676, 0x00000002 },
{ 0x00007677, 0x00000002 },
{ 0x0003802c, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002743, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0003802c, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002741, 0x00000002 },
{ 0x04002743, 0x00000002 },
{ 0x00007678, 0x00000006 },
{ 0x0000002f, 0x00000018 },
{ 0x0000002f, 0x00000018 },
{ 0000000000, 0x00000006 },
{ 0x00000037, 0x00000018 },
{ 0x00000037, 0x00000018 },
{ 0000000000, 0x00000006 },
{ 0x01605000, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x00098000, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x64c06051, 0x00000004 },
{ 0x00080000, 0x00000016 },
{ 0000000000, 0000000000 },
{ 0x0400251d, 0x00000002 },
{ 0x00007580, 0x00000002 },
{ 0x00067581, 0x00000002 },
{ 0x04002580, 0x00000002 },
{ 0x00067581, 0x00000002 },
{ 0x0000005a, 0x00000004 },
{ 0x00005000, 0000000000 },
{ 0x00061000, 0x00000002 },
{ 0x0000750e, 0x00000002 },
{ 0x00019000, 0x00000002 },
{ 0x00011064, 0x00000014 },
{ 0x00000064, 0x00000012 },
{ 0x0400250f, 0x00000002 },
{ 0x0000505e, 0x00000004 },
{ 0x00007565, 0x00000002 },
{ 0x00007566, 0x00000002 },
{ 0x00000065, 0x00000004 },
{ 0x01e655b4, 0x00000002 },
{ 0x4401b0f0, 0x00000002 },
{ 0x01c110f0, 0x00000002 },
{ 0x26667071, 0x00000018 },
{ 0x040c2565, 0x00000002 },
{ 0x00000071, 0x00000018 },
{ 0x04002564, 0x00000002 },
{ 0x00007566, 0x00000002 },
{ 0x00000068, 0x00000004 },
{ 0x00401074, 0x00000008 },
{ 0x00101000, 0x00000002 },
{ 0x000d80ff, 0x00000002 },
{ 0x00800077, 0x00000008 },
{ 0x000f9000, 0x00000002 },
{ 0x000e00ff, 0x00000002 },
{ 0000000000, 0x00000006 },
{ 0x00000094, 0x00000018 },
{ 0x00000068, 0x00000004 },
{ 0x00007576, 0x00000002 },
{ 0x00065000, 0x00000002 },
{ 0x00009000, 0x00000002 },
{ 0x00041000, 0x00000002 },
{ 0x0c00350e, 0x00000002 },
{ 0x00049000, 0x00000002 },
{ 0x00051000, 0x00000002 },
{ 0x01e785f8, 0x00000002 },
{ 0x00200000, 0x00000002 },
{ 0x00600087, 0x0000000c },
{ 0x00007563, 0x00000002 },
{ 0x006075f0, 0x00000021 },
{ 0x2000707c, 0x00000004 },
{ 0x0000507c, 0x00000004 },
{ 0x00007576, 0x00000002 },
{ 0x00007577, 0x00000002 },
{ 0x0000750e, 0x00000002 },
{ 0x0000750f, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x0060008a, 0x0000000c },
{ 0x006075f0, 0x00000021 },
{ 0x000075f8, 0x00000002 },
{ 0x0000008a, 0x00000004 },
{ 0x000a750e, 0x00000002 },
{ 0x0020750f, 0x00000002 },
{ 0x0060008d, 0x00000004 },
{ 0x00007570, 0x00000002 },
{ 0x00007571, 0x00000002 },
{ 0x00007572, 0x00000006 },
{ 0x00005000, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00007568, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x00000098, 0x0000000c },
{ 0x00058000, 0x00000002 },
{ 0x0c607562, 0x00000002 },
{ 0x0000009a, 0x00000004 },
{ 0x00600099, 0x00000004 },
{ 0x400070f1, 0000000000 },
{ 0x000380f1, 0x00000002 },
{ 0x000000a7, 0x0000001c },
{ 0x000650a9, 0x00000018 },
{ 0x040025bb, 0x00000002 },
{ 0x000610aa, 0x00000018 },
{ 0x040075bc, 0000000000 },
{ 0x000075bb, 0x00000002 },
{ 0x000075bc, 0000000000 },
{ 0x00090000, 0x00000006 },
{ 0x00090000, 0x00000002 },
{ 0x000d8002, 0x00000006 },
{ 0x00005000, 0x00000002 },
{ 0x00007821, 0x00000002 },
{ 0x00007800, 0000000000 },
{ 0x00007821, 0x00000002 },
{ 0x00007800, 0000000000 },
{ 0x01665000, 0x00000002 },
{ 0x000a0000, 0x00000002 },
{ 0x000671cc, 0x00000002 },
{ 0x0286f1cd, 0x00000002 },
{ 0x000000b7, 0x00000010 },
{ 0x21007000, 0000000000 },
{ 0x000000be, 0x0000001c },
{ 0x00065000, 0x00000002 },
{ 0x000a0000, 0x00000002 },
{ 0x00061000, 0x00000002 },
{ 0x000b0000, 0x00000002 },
{ 0x38067000, 0x00000002 },
{ 0x000a00ba, 0x00000004 },
{ 0x20007000, 0000000000 },
{ 0x01200000, 0x00000002 },
{ 0x20077000, 0x00000002 },
{ 0x01200000, 0x00000002 },
{ 0x20007000, 0000000000 },
{ 0x00061000, 0x00000002 },
{ 0x0120751b, 0x00000002 },
{ 0x8040750a, 0x00000002 },
{ 0x8040750b, 0x00000002 },
{ 0x00110000, 0x00000002 },
{ 0x000380f1, 0x00000002 },
{ 0x000000d1, 0x0000001c },
{ 0x000610aa, 0x00000018 },
{ 0x844075bd, 0x00000002 },
{ 0x000610a9, 0x00000018 },
{ 0x840075bb, 0x00000002 },
{ 0x000610aa, 0x00000018 },
{ 0x844075bc, 0x00000002 },
{ 0x000000d4, 0x00000004 },
{ 0x804075bd, 0x00000002 },
{ 0x800075bb, 0x00000002 },
{ 0x804075bc, 0x00000002 },
{ 0x00108000, 0x00000002 },
{ 0x01400000, 0x00000002 },
{ 0x006000d8, 0x0000000c },
{ 0x20c07000, 0x00000020 },
{ 0x000000da, 0x00000012 },
{ 0x00800000, 0x00000006 },
{ 0x0080751d, 0x00000006 },
{ 0x000025bb, 0x00000002 },
{ 0x000040d4, 0x00000004 },
{ 0x0000775c, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00661000, 0x00000002 },
{ 0x0460275d, 0x00000020 },
{ 0x00004000, 0000000000 },
{ 0x00007999, 0x00000002 },
{ 0x00a05000, 0x00000002 },
{ 0x00661000, 0x00000002 },
{ 0x0460299b, 0x00000020 },
{ 0x00004000, 0000000000 },
{ 0x01e00830, 0x00000002 },
{ 0x21007000, 0000000000 },
{ 0x00005000, 0x00000002 },
{ 0x00038056, 0x00000002 },
{ 0x040025e0, 0x00000002 },
{ 0x000075e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000380ed, 0x00000002 },
{ 0x04007394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000078c4, 0x00000002 },
{ 0x000078c5, 0x00000002 },
{ 0x000078c6, 0x00000002 },
{ 0x00007924, 0x00000002 },
{ 0x00007925, 0x00000002 },
{ 0x00007926, 0x00000002 },
{ 0x000000f2, 0x00000004 },
{ 0x00007924, 0x00000002 },
{ 0x00007925, 0x00000002 },
{ 0x00007926, 0x00000002 },
{ 0x000000f9, 0x00000004 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32 R300_cp_microcode[][2] = {
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x000000ae, 0x00000008 },
{ 0x000000b2, 0x00000008 },
{ 0x67554b4a, 0000000000 },
{ 0x4a4a4475, 0000000000 },
{ 0x55527d83, 0000000000 },
{ 0x4a8c8b65, 0000000000 },
{ 0x4aef4af6, 0000000000 },
{ 0x4ae14a4a, 0000000000 },
{ 0xe4979797, 0000000000 },
{ 0xdb4aebdd, 0000000000 },
{ 0x9ccc4a4a, 0000000000 },
{ 0xd1989898, 0000000000 },
{ 0x4a0f9ad6, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000f041, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000f184, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000f185, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000f186, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000f187, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000080, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x00012000, 0x00000004 },
{ 0x00082000, 0x00000004 },
{ 0x1800650e, 0x00000004 },
{ 0x00092000, 0x00000004 },
{ 0x000a2000, 0x00000004 },
{ 0x000f0000, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x00000074, 0x00000018 },
{ 0x0000e563, 0x00000004 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0000a069, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000077, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000077, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0007a, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000084, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000086, 0x00000008 },
{ 0x00c00085, 0x00000008 },
{ 0x000700e3, 0x00000004 },
{ 0x00000092, 0x00000038 },
{ 0x000ca094, 0x00000030 },
{ 0x080045bb, 0x00000004 },
{ 0x000c2095, 0x00000030 },
{ 0x0800e5bc, 0000000000 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x00120000, 0x0000000c },
{ 0x00120000, 0x00000004 },
{ 0x001b0002, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x000000a4, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x000000a1, 0x00000008 },
{ 0x000000a6, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x000000ad, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x001400a9, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700e3, 0x00000004 },
{ 0x000000c0, 0x00000038 },
{ 0x000c2095, 0x00000030 },
{ 0x0880e5bd, 0x00000005 },
{ 0x000c2094, 0x00000030 },
{ 0x0800e5bb, 0x00000005 },
{ 0x000c2095, 0x00000030 },
{ 0x0880e5bc, 0x00000005 },
{ 0x000000c3, 0x00000008 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000c7, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000c9, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080c3, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700e0, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000e4, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000eb, 0x00000008 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000f3, 0x00000034 },
{ 0x000000f0, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32 R420_cp_microcode[][2] = {
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x00000099, 0x00000008 },
{ 0x0000009d, 0x00000008 },
{ 0x4a554b4a, 0000000000 },
{ 0x4a4a4467, 0000000000 },
{ 0x55526f75, 0000000000 },
{ 0x4a7e7d65, 0000000000 },
{ 0xd9d3dff6, 0000000000 },
{ 0x4ac54a4a, 0000000000 },
{ 0xc8828282, 0000000000 },
{ 0xbf4acfc1, 0000000000 },
{ 0x87b04a4a, 0000000000 },
{ 0xb5838383, 0000000000 },
{ 0x4a0f85ba, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000f041, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000f184, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000f185, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000f186, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000f187, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000072, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000069, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0006c, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000076, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000078, 0x00000008 },
{ 0x00c00077, 0x00000008 },
{ 0x000700c7, 0x00000004 },
{ 0x00000080, 0x00000038 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x0000008f, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x0000008c, 0x00000008 },
{ 0x00000091, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x00000098, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x00140094, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700c7, 0x00000004 },
{ 0x000000a4, 0x00000038 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000ab, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000ad, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080a7, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700c4, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000c8, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000cf, 0x00000008 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000d7, 0x00000034 },
{ 0x000000d4, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0x0000e1cc, 0x00000004 },
{ 0x0500e1cd, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x000000de, 0x00000034 },
{ 0x000000da, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x0019e1cc, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x0500a000, 0x00000004 },
{ 0x080041cd, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32 RS600_cp_microcode[][2] = {
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x000000a0, 0x00000008 },
{ 0x000000a4, 0x00000008 },
{ 0x4a554b4a, 0000000000 },
{ 0x4a4a4467, 0000000000 },
{ 0x55526f75, 0000000000 },
{ 0x4a7e7d65, 0000000000 },
{ 0x4ae74af6, 0000000000 },
{ 0x4ad34a4a, 0000000000 },
{ 0xd6898989, 0000000000 },
{ 0xcd4addcf, 0000000000 },
{ 0x8ebe4ae2, 0000000000 },
{ 0xc38a8a8a, 0000000000 },
{ 0x4a0f8cc8, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000f041, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000f184, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000f185, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000f186, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000f187, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000072, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000069, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0006c, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000076, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000078, 0x00000008 },
{ 0x00c00077, 0x00000008 },
{ 0x000700d5, 0x00000004 },
{ 0x00000084, 0x00000038 },
{ 0x000ca086, 0x00000030 },
{ 0x080045bb, 0x00000004 },
{ 0x000c2087, 0x00000030 },
{ 0x0800e5bc, 0000000000 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x00120000, 0x0000000c },
{ 0x00120000, 0x00000004 },
{ 0x001b0002, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x00000096, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x00000093, 0x00000008 },
{ 0x00000098, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x0000009f, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x0014009b, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700d5, 0x00000004 },
{ 0x000000b2, 0x00000038 },
{ 0x000c2087, 0x00000030 },
{ 0x0880e5bd, 0x00000005 },
{ 0x000c2086, 0x00000030 },
{ 0x0800e5bb, 0x00000005 },
{ 0x000c2087, 0x00000030 },
{ 0x0880e5bc, 0x00000005 },
{ 0x000000b5, 0x00000008 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000b9, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000bb, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080b5, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700d2, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000d6, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000dd, 0x00000008 },
{ 0x00e00116, 0000000000 },
{ 0x000700e1, 0x00000004 },
{ 0x0800401c, 0x00000004 },
{ 0x200050e7, 0x00000004 },
{ 0x0000e01d, 0x00000004 },
{ 0x000000e4, 0x00000008 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000eb, 0x00000034 },
{ 0x000000e8, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32 RS690_cp_microcode[][2] = {
{ 0x000000dd, 0x00000008 },
{ 0x000000df, 0x00000008 },
{ 0x000000a0, 0x00000008 },
{ 0x000000a4, 0x00000008 },
{ 0x4a554b4a, 0000000000 },
{ 0x4a4a4467, 0000000000 },
{ 0x55526f75, 0000000000 },
{ 0x4a7e7d65, 0000000000 },
{ 0x4ad74af6, 0000000000 },
{ 0x4ac94a4a, 0000000000 },
{ 0xcc898989, 0000000000 },
{ 0xc34ad3c5, 0000000000 },
{ 0x8e4a4a4a, 0000000000 },
{ 0x4a8a8a8a, 0000000000 },
{ 0x4a0f8c4a, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000f041, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000f184, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000f185, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000f186, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000f187, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000072, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000069, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0006c, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000076, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000078, 0x00000008 },
{ 0x00c00077, 0x00000008 },
{ 0x000700cb, 0x00000004 },
{ 0x00000084, 0x00000038 },
{ 0x000ca086, 0x00000030 },
{ 0x080045bb, 0x00000004 },
{ 0x000c2087, 0x00000030 },
{ 0x0800e5bc, 0000000000 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x00120000, 0x0000000c },
{ 0x00120000, 0x00000004 },
{ 0x001b0002, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x00000096, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x00000093, 0x00000008 },
{ 0x00000098, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x0000009f, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x0014009b, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x00100000, 0x0000002c },
{ 0x00004000, 0000000000 },
{ 0x080045c8, 0x00000004 },
{ 0x00240005, 0x00000004 },
{ 0x08004d0b, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700cb, 0x00000004 },
{ 0x000000b7, 0x00000038 },
{ 0x000c2087, 0x00000030 },
{ 0x0880e5bd, 0x00000005 },
{ 0x000c2086, 0x00000030 },
{ 0x0800e5bb, 0x00000005 },
{ 0x000c2087, 0x00000030 },
{ 0x0880e5bc, 0x00000005 },
{ 0x000000ba, 0x00000008 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000be, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000c0, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080ba, 0x00000008 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700c8, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000cc, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000d3, 0x00000008 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000db, 0x00000034 },
{ 0x000000d8, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0x000000e1, 0x00000030 },
{ 0x4200e000, 0000000000 },
{ 0x000000e1, 0x00000030 },
{ 0x4000e000, 0000000000 },
{ 0x0025001b, 0x00000004 },
{ 0x00230000, 0x00000004 },
{ 0x00250005, 0x00000004 },
{ 0x000000e6, 0x00000034 },
{ 0000000000, 0x0000000c },
{ 0x00244000, 0x00000004 },
{ 0x080045c8, 0x00000004 },
{ 0x00240005, 0x00000004 },
{ 0x08004d0b, 0x0000000c },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32 R520_cp_microcode[][2] = {
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x00000099, 0x00000008 },
{ 0x0000009d, 0x00000008 },
{ 0x4a554b4a, 0000000000 },
{ 0x4a4a4467, 0000000000 },
{ 0x55526f75, 0000000000 },
{ 0x4a7e7d65, 0000000000 },
{ 0xe0dae6f6, 0000000000 },
{ 0x4ac54a4a, 0000000000 },
{ 0xc8828282, 0000000000 },
{ 0xbf4acfc1, 0000000000 },
{ 0x87b04ad5, 0000000000 },
{ 0xb5838383, 0000000000 },
{ 0x4a0f85ba, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000072, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000069, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0006c, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000076, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000078, 0x00000008 },
{ 0x00c00077, 0x00000008 },
{ 0x000700c7, 0x00000004 },
{ 0x00000080, 0x00000038 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x0000008f, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x0000008c, 0x00000008 },
{ 0x00000091, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x00000098, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x00140094, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700c7, 0x00000004 },
{ 0x000000a4, 0x00000038 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000ab, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000ad, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080a7, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700c4, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000c8, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000cf, 0x00000008 },
{ 0xdeadbeef, 0000000000 },
{ 0x00000116, 0000000000 },
{ 0x000700d3, 0x00000004 },
{ 0x080050e7, 0x00000004 },
{ 0x000700d4, 0x00000004 },
{ 0x0800401c, 0x00000004 },
{ 0x0000e01d, 0000000000 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000de, 0x00000034 },
{ 0x000000db, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0x0000e1cc, 0x00000004 },
{ 0x0500e1cd, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x000000e5, 0x00000034 },
{ 0x000000e1, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x0019e1cc, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x0500a000, 0x00000004 },
{ 0x080041cd, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
#endif
drivers/char/drm/radeon_state.c
View file @ 9aef85cc
...@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, ...@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
u32 height; u32 height;
int i; int i;
u32 texpitch, microtile; u32 texpitch, microtile;
u32 offset; u32 offset, byte_offset;
RING_LOCALS; RING_LOCALS;
if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
...@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, ...@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
} else } else
microtile = 0; microtile = 0;
/* this might fail for zero-sized uploads - are those illegal? */
if (!radeon_check_offset(dev_priv, tex->offset + image->height *
blit_width - 1)) {
DRM_ERROR("Invalid final destination offset\n");
return -EINVAL;
}
DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
do { do {
...@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, ...@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
} }
#undef RADEON_COPY_MT #undef RADEON_COPY_MT
byte_offset = (image->y & ~2047) * blit_width;
buf->file_priv = file_priv; buf->file_priv = file_priv;
buf->used = size; buf->used = size;
offset = dev_priv->gart_buffers_offset + buf->offset; offset = dev_priv->gart_buffers_offset + buf->offset;
...@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, ...@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
RADEON_DP_SRC_SOURCE_MEMORY | RADEON_DP_SRC_SOURCE_MEMORY |
RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
OUT_RING((spitch << 22) | (offset >> 10)); OUT_RING((spitch << 22) | (offset >> 10));
OUT_RING((texpitch << 22) | (tex->offset >> 10)); OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
OUT_RING(0); OUT_RING(0);
OUT_RING((image->x << 16) | image->y); OUT_RING((image->x << 16) | (image->y % 2048));
OUT_RING((image->width << 16) | height); OUT_RING((image->width << 16) | height);
RADEON_WAIT_UNTIL_2D_IDLE(); RADEON_WAIT_UNTIL_2D_IDLE();
ADVANCE_RING(); ADVANCE_RING();
...@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil ...@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
case RADEON_PARAM_FB_LOCATION: case RADEON_PARAM_FB_LOCATION:
value = radeon_read_fb_location(dev_priv); value = radeon_read_fb_location(dev_priv);
break; break;
case RADEON_PARAM_NUM_GB_PIPES:
value = dev_priv->num_gb_pipes;
break;
default: default:
DRM_DEBUG("Invalid parameter %d\n", param->param); DRM_DEBUG("Invalid parameter %d\n", param->param);
return -EINVAL; return -EINVAL;
......
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