drm/nouveau/pci: switch to instanced constructor

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

@@ -60,7 +60,6 @@ struct nvkm_device {
 		struct notifier_block nb;
 	} acpi;
 
-	struct nvkm_pci *pci;
 	struct nvkm_pmu *pmu;
 	struct nvkm_therm *therm;
 	struct nvkm_timer *timer;
@@ -129,7 +128,6 @@ struct nvkm_device_chip {
 #include <core/layout.h>
 #undef NVKM_LAYOUT_INST
 #undef NVKM_LAYOUT_ONCE
-	int (*pci     )(struct nvkm_device *, int idx, struct nvkm_pci **);
 	int (*pmu     )(struct nvkm_device *, int idx, struct nvkm_pmu **);
 	int (*therm   )(struct nvkm_device *, int idx, struct nvkm_therm **);
 	int (*timer   )(struct nvkm_device *, int idx, struct nvkm_timer **);

drivers/gpu/drm/nouveau/include/nvkm/core/layout.h

 /* SPDX-License-Identifier: MIT */
+NVKM_LAYOUT_ONCE(NVKM_SUBDEV_PCI     , struct nvkm_pci     ,      pci)
 NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VBIOS   , struct nvkm_bios    ,     bios)
 NVKM_LAYOUT_ONCE(NVKM_SUBDEV_DEVINIT , struct nvkm_devinit ,  devinit)
 NVKM_LAYOUT_ONCE(NVKM_SUBDEV_IBUS    , struct nvkm_subdev  ,     ibus)

drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h

@@ -39,17 +39,17 @@ void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data);
 u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 value);
 void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
 
-int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int nv40_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int g92_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int gp100_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
+int nv04_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int nv40_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int nv46_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int nv4c_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int g84_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int g92_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int g94_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int gf100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int gf106_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int gk104_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
+int gp100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
 
 /* pcie functions */
 int nvkm_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8 width);

drivers/gpu/drm/nouveau/nvkm/core/subdev.c

@@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
 #include <core/layout.h>
 #undef NVKM_LAYOUT_ONCE
 #undef NVKM_LAYOUT_INST
-	[NVKM_SUBDEV_PCI     ] = "pci",
 	[NVKM_SUBDEV_PMU     ] = "pmu",
 	[NVKM_SUBDEV_THERM   ] = "therm",
 	[NVKM_SUBDEV_TIMER   ] = "tmr",

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -86,7 +86,7 @@ nv4_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv04_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -107,7 +107,7 @@ nv5_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv04_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -129,7 +129,7 @@ nv10_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv04_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -149,7 +149,7 @@ nv11_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv11_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -171,7 +171,7 @@ nv15_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv04_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -193,7 +193,7 @@ nv17_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -215,7 +215,7 @@ nv18_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -237,7 +237,7 @@ nv1a_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv04_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -259,7 +259,7 @@ nv1f_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -281,7 +281,7 @@ nv20_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -303,7 +303,7 @@ nv25_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -325,7 +325,7 @@ nv28_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -347,7 +347,7 @@ nv2a_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -369,7 +369,7 @@ nv30_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -391,7 +391,7 @@ nv31_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -414,7 +414,7 @@ nv34_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -437,7 +437,7 @@ nv35_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -459,7 +459,7 @@ nv36_chipset = {
 	.imem     = { 0x00000001, nv04_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv04_pci_new,
+	.pci      = { 0x00000001, nv04_pci_new },
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
@@ -482,7 +482,7 @@ nv40_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv40_timer_new,
 	.volt = nv40_volt_new,
@@ -508,7 +508,7 @@ nv41_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv41_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -534,7 +534,7 @@ nv42_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv41_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -560,7 +560,7 @@ nv43_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv41_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -586,7 +586,7 @@ nv44_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -612,7 +612,7 @@ nv45_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -638,7 +638,7 @@ nv46_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv46_pci_new,
+	.pci      = { 0x00000001, nv46_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -664,7 +664,7 @@ nv47_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv41_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -690,7 +690,7 @@ nv49_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv41_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -716,7 +716,7 @@ nv4a_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv04_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -742,7 +742,7 @@ nv4b_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv17_mc_new },
 	.mmu      = { 0x00000001, nv41_mmu_new },
-	.pci = nv40_pci_new,
+	.pci      = { 0x00000001, nv40_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -768,7 +768,7 @@ nv4c_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv4c_pci_new,
+	.pci      = { 0x00000001, nv4c_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -794,7 +794,7 @@ nv4e_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv4c_pci_new,
+	.pci      = { 0x00000001, nv4c_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -823,7 +823,7 @@ nv50_chipset = {
 	.mc       = { 0x00000001, nv50_mc_new },
 	.mmu      = { 0x00000001, nv50_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = nv46_pci_new,
+	.pci      = { 0x00000001, nv46_pci_new },
 	.therm = nv50_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -849,7 +849,7 @@ nv63_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv4c_pci_new,
+	.pci      = { 0x00000001, nv4c_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -875,7 +875,7 @@ nv67_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv4c_pci_new,
+	.pci      = { 0x00000001, nv4c_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -901,7 +901,7 @@ nv68_chipset = {
 	.imem     = { 0x00000001, nv40_instmem_new },
 	.mc       = { 0x00000001, nv44_mc_new },
 	.mmu      = { 0x00000001, nv44_mmu_new },
-	.pci = nv4c_pci_new,
+	.pci      = { 0x00000001, nv4c_pci_new },
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -930,7 +930,7 @@ nv84_chipset = {
 	.mc       = { 0x00000001, g84_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g84_pci_new,
+	.pci      = { 0x00000001, g84_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -962,7 +962,7 @@ nv86_chipset = {
 	.mc       = { 0x00000001, g84_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g84_pci_new,
+	.pci      = { 0x00000001, g84_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -994,7 +994,7 @@ nv92_chipset = {
 	.mc       = { 0x00000001, g84_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g92_pci_new,
+	.pci      = { 0x00000001, g92_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1026,7 +1026,7 @@ nv94_chipset = {
 	.mc       = { 0x00000001, g84_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1058,7 +1058,7 @@ nv96_chipset = {
 	.mc       = { 0x00000001, g84_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1090,7 +1090,7 @@ nv98_chipset = {
 	.mc       = { 0x00000001, g98_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1122,7 +1122,7 @@ nva0_chipset = {
 	.mc       = { 0x00000001, g84_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1154,7 +1154,7 @@ nva3_chipset = {
 	.mc       = { 0x00000001, gt215_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.pmu = gt215_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1188,7 +1188,7 @@ nva5_chipset = {
 	.mc       = { 0x00000001, gt215_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.pmu = gt215_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1221,7 +1221,7 @@ nva8_chipset = {
 	.mc       = { 0x00000001, gt215_mc_new },
 	.mmu      = { 0x00000001, g84_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.pmu = gt215_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1254,7 +1254,7 @@ nvaa_chipset = {
 	.mc       = { 0x00000001, g98_mc_new },
 	.mmu      = { 0x00000001, mcp77_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1286,7 +1286,7 @@ nvac_chipset = {
 	.mc       = { 0x00000001, g98_mc_new },
 	.mmu      = { 0x00000001, mcp77_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.therm = g84_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -1318,7 +1318,7 @@ nvaf_chipset = {
 	.mc       = { 0x00000001, gt215_mc_new },
 	.mmu      = { 0x00000001, mcp77_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = g94_pci_new,
+	.pci      = { 0x00000001, g94_pci_new },
 	.pmu = gt215_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1354,7 +1354,7 @@ nvc0_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf100_pci_new,
+	.pci      = { 0x00000001, gf100_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1391,7 +1391,7 @@ nvc1_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf106_pci_new,
+	.pci      = { 0x00000001, gf106_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1427,7 +1427,7 @@ nvc3_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf106_pci_new,
+	.pci      = { 0x00000001, gf106_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1463,7 +1463,7 @@ nvc4_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf100_pci_new,
+	.pci      = { 0x00000001, gf100_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1500,7 +1500,7 @@ nvc8_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf100_pci_new,
+	.pci      = { 0x00000001, gf100_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1537,7 +1537,7 @@ nvce_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf100_pci_new,
+	.pci      = { 0x00000001, gf100_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1574,7 +1574,7 @@ nvcf_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf106_pci_new,
+	.pci      = { 0x00000001, gf106_pci_new },
 	.pmu = gf100_pmu_new,
 	.therm = gt215_therm_new,
 	.timer = nv41_timer_new,
@@ -1610,7 +1610,7 @@ nvd7_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf106_pci_new,
+	.pci      = { 0x00000001, gf106_pci_new },
 	.therm = gf119_therm_new,
 	.timer = nv41_timer_new,
 	.volt = gf117_volt_new,
@@ -1645,7 +1645,7 @@ nvd9_chipset = {
 	.mc       = { 0x00000001, gf100_mc_new },
 	.mmu      = { 0x00000001, gf100_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gf106_pci_new,
+	.pci      = { 0x00000001, gf106_pci_new },
 	.pmu = gf119_pmu_new,
 	.therm = gf119_therm_new,
 	.timer = nv41_timer_new,
@@ -1681,7 +1681,7 @@ nve4_chipset = {
 	.mc       = { 0x00000001, gk104_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk104_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1720,7 +1720,7 @@ nve6_chipset = {
 	.mc       = { 0x00000001, gk104_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk104_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1759,7 +1759,7 @@ nve7_chipset = {
 	.mc       = { 0x00000001, gk104_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk104_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1823,7 +1823,7 @@ nvf0_chipset = {
 	.mc       = { 0x00000001, gk104_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk110_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1861,7 +1861,7 @@ nvf1_chipset = {
 	.mc       = { 0x00000001, gk104_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk110_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1899,7 +1899,7 @@ nv106_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk208_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1937,7 +1937,7 @@ nv108_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gk208_pmu_new,
 	.therm = gk104_therm_new,
 	.timer = nv41_timer_new,
@@ -1975,7 +1975,7 @@ nv117_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gm107_pmu_new,
 	.therm = gm107_therm_new,
 	.timer = gk20a_timer_new,
@@ -2011,7 +2011,7 @@ nv118_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gk104_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gm107_pmu_new,
 	.therm = gm107_therm_new,
 	.timer = gk20a_timer_new,
@@ -2045,7 +2045,7 @@ nv120_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gm200_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gm200_pmu_new,
 	.therm = gm200_therm_new,
 	.timer = gk20a_timer_new,
@@ -2083,7 +2083,7 @@ nv124_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gm200_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gm200_pmu_new,
 	.therm = gm200_therm_new,
 	.timer = gk20a_timer_new,
@@ -2121,7 +2121,7 @@ nv126_chipset = {
 	.mc       = { 0x00000001, gk20a_mc_new },
 	.mmu      = { 0x00000001, gm200_mmu_new },
 	.mxm      = { 0x00000001, nv50_mxm_new },
-	.pci = gk104_pci_new,
+	.pci      = { 0x00000001, gk104_pci_new },
 	.pmu = gm200_pmu_new,
 	.therm = gm200_therm_new,
 	.timer = gk20a_timer_new,
@@ -2183,7 +2183,7 @@ nv130_chipset = {
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gp100_mmu_new },
 	.therm = gp100_therm_new,
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gm200_pmu_new,
 	.timer = gk20a_timer_new,
 	.top = gk104_top_new,
@@ -2223,7 +2223,7 @@ nv132_chipset = {
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gp100_mmu_new },
 	.therm = gp100_therm_new,
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.timer = gk20a_timer_new,
 	.top = gk104_top_new,
@@ -2261,7 +2261,7 @@ nv134_chipset = {
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gp100_mmu_new },
 	.therm = gp100_therm_new,
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.timer = gk20a_timer_new,
 	.top = gk104_top_new,
@@ -2299,7 +2299,7 @@ nv136_chipset = {
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gp100_mmu_new },
 	.therm = gp100_therm_new,
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.timer = gk20a_timer_new,
 	.top = gk104_top_new,
@@ -2336,7 +2336,7 @@ nv137_chipset = {
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gp100_mmu_new },
 	.therm = gp100_therm_new,
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.timer = gk20a_timer_new,
 	.top = gk104_top_new,
@@ -2374,7 +2374,7 @@ nv138_chipset = {
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gp100_mmu_new },
 	.therm = gp100_therm_new,
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.timer = gk20a_timer_new,
 	.top = gk104_top_new,
@@ -2434,7 +2434,7 @@ nv140_chipset = {
 	.ltc      = { 0x00000001, gp102_ltc_new },
 	.mc       = { 0x00000001, gp100_mc_new },
 	.mmu      = { 0x00000001, gv100_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.therm = gp100_therm_new,
 	.timer = gk20a_timer_new,
@@ -2478,7 +2478,7 @@ nv162_chipset = {
 	.ltc      = { 0x00000001, gp102_ltc_new },
 	.mc       = { 0x00000001, tu102_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.therm = gp100_therm_new,
 	.timer = gk20a_timer_new,
@@ -2516,7 +2516,7 @@ nv164_chipset = {
 	.ltc      = { 0x00000001, gp102_ltc_new },
 	.mc       = { 0x00000001, tu102_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.therm = gp100_therm_new,
 	.timer = gk20a_timer_new,
@@ -2555,7 +2555,7 @@ nv166_chipset = {
 	.ltc      = { 0x00000001, gp102_ltc_new },
 	.mc       = { 0x00000001, tu102_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.therm = gp100_therm_new,
 	.timer = gk20a_timer_new,
@@ -2595,7 +2595,7 @@ nv167_chipset = {
 	.ltc      = { 0x00000001, gp102_ltc_new },
 	.mc       = { 0x00000001, tu102_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.therm = gp100_therm_new,
 	.timer = gk20a_timer_new,
@@ -2633,7 +2633,7 @@ nv168_chipset = {
 	.ltc      = { 0x00000001, gp102_ltc_new },
 	.mc       = { 0x00000001, tu102_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.pmu = gp102_pmu_new,
 	.therm = gp100_therm_new,
 	.timer = gk20a_timer_new,
@@ -2665,7 +2665,7 @@ nv170_chipset = {
 	.imem     = { 0x00000001, nv50_instmem_new },
 	.mc       = { 0x00000001, ga100_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.timer = gk20a_timer_new,
 };
 
@@ -2682,7 +2682,7 @@ nv172_chipset = {
 	.imem     = { 0x00000001, nv50_instmem_new },
 	.mc       = { 0x00000001, ga100_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.timer = gk20a_timer_new,
 	.disp = ga102_disp_new,
 	.dma = gv100_dma_new,
@@ -2701,7 +2701,7 @@ nv174_chipset = {
 	.imem     = { 0x00000001, nv50_instmem_new },
 	.mc       = { 0x00000001, ga100_mc_new },
 	.mmu      = { 0x00000001, tu102_mmu_new },
-	.pci = gp100_pci_new,
+	.pci      = { 0x00000001, gp100_pci_new },
 	.timer = gk20a_timer_new,
 	.disp = ga102_disp_new,
 	.dma = gv100_dma_new,
@@ -3248,7 +3248,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
 #include <core/layout.h>
 #undef NVKM_LAYOUT_INST
 #undef NVKM_LAYOUT_ONCE
-		_(NVKM_SUBDEV_PCI     ,      pci);
 		_(NVKM_SUBDEV_PMU     ,      pmu);
 		_(NVKM_SUBDEV_THERM   ,    therm);
 		_(NVKM_SUBDEV_TIMER   ,    timer);

drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c

@@ -183,13 +183,13 @@ nvkm_pci_func = {
 
 int
 nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device,
-	      int index, struct nvkm_pci **ppci)
+	      enum nvkm_subdev_type type, int inst, struct nvkm_pci **ppci)
 {
 	struct nvkm_pci *pci;
 
 	if (!(pci = *ppci = kzalloc(sizeof(**ppci), GFP_KERNEL)))
 		return -ENOMEM;
-	nvkm_subdev_ctor(&nvkm_pci_func, device, index, &pci->subdev);
+	nvkm_subdev_ctor(&nvkm_pci_func, device, type, inst, &pci->subdev);
 	pci->func = func;
 	pci->pdev = device->func->pci(device)->pdev;
 	pci->irq = -1;

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c

@@ -150,7 +150,8 @@ g84_pci_func = {
 };
 
 int
-g84_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+g84_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	    struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&g84_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&g84_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c

@@ -51,7 +51,8 @@ g92_pci_func = {
 };
 
 int
-g92_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+g92_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	    struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&g92_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&g92_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c

@@ -43,7 +43,8 @@ g94_pci_func = {
 };
 
 int
-g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+g94_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	    struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&g94_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&g94_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c

@@ -96,7 +96,8 @@ gf100_pci_func = {
 };
 
 int
-gf100_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+gf100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	      struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&gf100_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&gf100_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c

@@ -43,7 +43,8 @@ gf106_pci_func = {
 };
 
 int
-gf106_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+gf106_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	      struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&gf106_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&gf106_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c

@@ -222,7 +222,8 @@ gk104_pci_func = {
 };
 
 int
-gk104_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+gk104_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	      struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&gk104_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&gk104_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c

@@ -38,7 +38,8 @@ gp100_pci_func = {
 };
 
 int
-gp100_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+gp100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	      struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&gp100_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&gp100_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c

@@ -52,7 +52,8 @@ nv04_pci_func = {
 };
 
 int
-nv04_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+nv04_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	     struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&nv04_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&nv04_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c

@@ -59,7 +59,8 @@ nv40_pci_func = {
 };
 
 int
-nv40_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+nv40_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	     struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&nv40_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&nv40_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c

@@ -45,7 +45,8 @@ nv46_pci_func = {
 };
 
 int
-nv46_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+nv46_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	     struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&nv46_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&nv46_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c

@@ -31,7 +31,8 @@ nv4c_pci_func = {
 };
 
 int
-nv4c_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+nv4c_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	     struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&nv4c_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&nv4c_pci_func, device, type, inst, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h

@@ -4,8 +4,8 @@
 #define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev)
 #include <subdev/pci.h>
 
-int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *,
-		  int index, struct nvkm_pci **);
+int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
+		  struct nvkm_pci **);
 
 struct nvkm_pci_func {
 	void (*init)(struct nvkm_pci *);