Commit 9cb0fbf7 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (47 commits)
  MIPS: Add hibernation support
  MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h
  MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
  MIPS: Kconfig Add SYS_SUPPORTS_HUGETLBFS and enable it for some systems.
  Hugetlbfs: Enable hugetlbfs for more systems in Kconfig.
  MIPS: TLB support for hugetlbfs.
  MIPS: Add hugetlbfs page defines.
  MIPS: Add support files for hugetlbfs.
  MIPS: Remove unused parameters from iPTE_LW.
  Staging: Add octeon-ethernet driver files.
  MIPS: Export erratum function needed by octeon-ethernet driver.
  MIPS: Cavium-Octeon: Add more chip specific feature tests.
  MIPS: Cavium-Octeon: Add more board type constants.
  MIPS: Export cvmx_sysinfo_get needed by octeon-ethernet driver.
  MIPS: Add named alloc functions to OCTEON boot monitor memory allocator.
  MIPS: Alchemy: devboards: Convert to gpio calls.
  MIPS: Alchemy: xxs1500: use linux gpio api.
  MIPS: Alchemy: MTX-1: Use linux gpio api.
  MIPS: Alchemy: Rewrite GPIO support.
  MIPS: Alchemy: Remove unused au1000_gpio.h header
  ...
parents feb72ce8 363c55ca
...@@ -618,6 +618,8 @@ config CAVIUM_OCTEON_REFERENCE_BOARD ...@@ -618,6 +618,8 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
select SYS_HAS_EARLY_PRINTK select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_CAVIUM_OCTEON select SYS_HAS_CPU_CAVIUM_OCTEON
select SWAP_IO_SPACE select SWAP_IO_SPACE
select HW_HAS_PCI
select ARCH_SUPPORTS_MSI
help help
This option supports all of the Octeon reference boards from Cavium This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon Networks. It builds a kernel that dynamically determines the Octeon
...@@ -851,6 +853,11 @@ config SYS_SUPPORTS_BIG_ENDIAN ...@@ -851,6 +853,11 @@ config SYS_SUPPORTS_BIG_ENDIAN
config SYS_SUPPORTS_LITTLE_ENDIAN config SYS_SUPPORTS_LITTLE_ENDIAN
bool bool
config SYS_SUPPORTS_HUGETLBFS
bool
depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
default y
config IRQ_CPU config IRQ_CPU
bool bool
...@@ -1055,6 +1062,7 @@ config CPU_MIPS64_R1 ...@@ -1055,6 +1062,7 @@ config CPU_MIPS64_R1
select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
help help
Choose this option to build a kernel for release 1 or later of the Choose this option to build a kernel for release 1 or later of the
MIPS64 architecture. Many modern embedded systems with a 64-bit MIPS64 architecture. Many modern embedded systems with a 64-bit
...@@ -1074,6 +1082,7 @@ config CPU_MIPS64_R2 ...@@ -1074,6 +1082,7 @@ config CPU_MIPS64_R2
select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
help help
Choose this option to build a kernel for release 2 or later of the Choose this option to build a kernel for release 2 or later of the
MIPS64 architecture. Many modern embedded systems with a 64-bit MIPS64 architecture. Many modern embedded systems with a 64-bit
...@@ -1160,6 +1169,7 @@ config CPU_R5500 ...@@ -1160,6 +1169,7 @@ config CPU_R5500
select CPU_HAS_LLSC select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
help help
NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
instruction set. instruction set.
...@@ -1245,6 +1255,7 @@ config CPU_CAVIUM_OCTEON ...@@ -1245,6 +1255,7 @@ config CPU_CAVIUM_OCTEON
select WEAK_ORDERING select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC select WEAK_REORDERING_BEYOND_LLSC
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
help help
The Cavium Octeon processor is a highly integrated chip containing The Cavium Octeon processor is a highly integrated chip containing
many ethernet hardware widgets for networking tasks. The processor many ethernet hardware widgets for networking tasks. The processor
...@@ -1364,6 +1375,8 @@ config CPU_SUPPORTS_32BIT_KERNEL ...@@ -1364,6 +1375,8 @@ config CPU_SUPPORTS_32BIT_KERNEL
bool bool
config CPU_SUPPORTS_64BIT_KERNEL config CPU_SUPPORTS_64BIT_KERNEL
bool bool
config CPU_SUPPORTS_HUGEPAGES
bool
# #
# Set to y for ptrace access to watch registers. # Set to y for ptrace access to watch registers.
...@@ -2121,6 +2134,10 @@ endmenu ...@@ -2121,6 +2134,10 @@ endmenu
menu "Power management options" menu "Power management options"
config ARCH_HIBERNATION_POSSIBLE
def_bool y
depends on !SMP
config ARCH_SUSPEND_POSSIBLE config ARCH_SUSPEND_POSSIBLE
def_bool y def_bool y
depends on !SMP depends on !SMP
......
...@@ -167,7 +167,6 @@ libs-$(CONFIG_ARC) += arch/mips/fw/arc/ ...@@ -167,7 +167,6 @@ libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
libs-y += arch/mips/fw/lib/ libs-y += arch/mips/fw/lib/
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
# #
# Board-dependent options and extra files # Board-dependent options and extra files
...@@ -184,7 +183,6 @@ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000 ...@@ -184,7 +183,6 @@ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
# Common Alchemy Au1x00 stuff # Common Alchemy Au1x00 stuff
# #
core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/ core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
# #
# AMD Alchemy Pb1000 eval board # AMD Alchemy Pb1000 eval board
...@@ -282,6 +280,10 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 ...@@ -282,6 +280,10 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/ libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/
load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
# must be last for Alchemy systems for GPIO to work properly
cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
# #
# Cobalt Server # Cobalt Server
# #
...@@ -675,6 +677,9 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ ...@@ -675,6 +677,9 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
# suspend and hibernation support
drivers-$(CONFIG_PM) += arch/mips/power/
ifdef CONFIG_LASAT ifdef CONFIG_LASAT
rom.bin rom.sw: vmlinux rom.bin rom.sw: vmlinux
$(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
......
# au1000-style gpio
config ALCHEMY_GPIO_AU1000
bool
# select this in your board config if you don't want to use the gpio
# namespace as documented in the manuals. In this case however you need
# to create the necessary gpio_* functions in your board code/headers!
# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
config ALCHEMY_GPIO_INDIRECT
def_bool n
choice choice
prompt "Machine type" prompt "Machine type"
depends on MACH_ALCHEMY depends on MACH_ALCHEMY
...@@ -108,22 +119,27 @@ endchoice ...@@ -108,22 +119,27 @@ endchoice
config SOC_AU1000 config SOC_AU1000
bool bool
select SOC_AU1X00 select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1100 config SOC_AU1100
bool bool
select SOC_AU1X00 select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1500 config SOC_AU1500
bool bool
select SOC_AU1X00 select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1550 config SOC_AU1550
bool bool
select SOC_AU1X00 select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1200 config SOC_AU1200
bool bool
select SOC_AU1X00 select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1X00 config SOC_AU1X00
bool bool
...@@ -134,4 +150,5 @@ config SOC_AU1X00 ...@@ -134,4 +150,5 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION select SYS_SUPPORTS_APM_EMULATION
select ARCH_REQUIRE_GPIOLIB select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
...@@ -7,7 +7,14 @@ ...@@ -7,7 +7,14 @@
obj-y += prom.o irq.o puts.o time.o reset.o \ obj-y += prom.o irq.o puts.o time.o reset.o \
clocks.o platform.o power.o setup.o \ clocks.o platform.o power.o setup.o \
sleeper.o dma.o dbdma.o gpio.o sleeper.o dma.o dbdma.o
# optional gpiolib support
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
ifeq ($(CONFIG_GPIOLIB),y)
obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o
endif
endif
obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_PCI) += pci.o
......
/* /*
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Architecture specific GPIO support * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -23,8 +23,8 @@ ...@@ -23,8 +23,8 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
* *
* Notes : * Notes :
* au1000 SoC have only one GPIO line : GPIO1 * au1000 SoC have only one GPIO block : GPIO1
* others have a second one : GPIO2 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
...@@ -34,168 +34,97 @@ ...@@ -34,168 +34,97 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <asm/gpio.h> #include <asm/mach-au1x00/gpio.h>
struct au1000_gpio_chip {
struct gpio_chip chip;
void __iomem *regbase;
};
#if !defined(CONFIG_SOC_AU1000) #if !defined(CONFIG_SOC_AU1000)
static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) static int gpio2_get(struct gpio_chip *chip, unsigned offset)
{ {
u32 mask = 1 << offset; return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
} }
static void au1000_gpio2_set(struct gpio_chip *chip, static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
unsigned offset, int value)
{ {
u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
} }
static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{ {
u32 mask = 1 << offset; return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp &= ~mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
local_irq_restore(flags);
return 0;
} }
static int au1000_gpio2_direction_output(struct gpio_chip *chip, static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
unsigned offset, int value) int value)
{ {
u32 mask = 1 << offset; return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); value);
u32 tmp; }
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp |= mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
return 0; static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
{
return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
} }
#endif /* !defined(CONFIG_SOC_AU1000) */ #endif /* !defined(CONFIG_SOC_AU1000) */
static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) static int gpio1_get(struct gpio_chip *chip, unsigned offset)
{ {
u32 mask = 1 << offset; return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
} }
static void au1000_gpio1_set(struct gpio_chip *chip, static void gpio1_set(struct gpio_chip *chip,
unsigned offset, int value) unsigned offset, int value)
{ {
u32 mask = 1 << offset; alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
u32 reg_offset;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
if (value)
reg_offset = AU1000_GPIO1_OUT;
else
reg_offset = AU1000_GPIO1_CLR;
local_irq_save(flags);
writel(mask, gpch->regbase + reg_offset);
local_irq_restore(flags);
} }
static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{ {
u32 mask = 1 << offset; return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_ST);
return 0;
} }
static int au1000_gpio1_direction_output(struct gpio_chip *chip, static int gpio1_direction_output(struct gpio_chip *chip,
unsigned offset, int value) unsigned offset, int value)
{ {
u32 mask = 1 << offset; return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
struct au1000_gpio_chip *gpch; value);
}
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
au1000_gpio1_set(chip, offset, value);
return 0; static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
{
return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
} }
struct au1000_gpio_chip au1000_gpio_chip[] = { struct gpio_chip alchemy_gpio_chip[] = {
[0] = { [0] = {
.regbase = (void __iomem *)SYS_BASE, .label = "alchemy-gpio1",
.chip = { .direction_input = gpio1_direction_input,
.label = "au1000-gpio1", .direction_output = gpio1_direction_output,
.direction_input = au1000_gpio1_direction_input, .get = gpio1_get,
.direction_output = au1000_gpio1_direction_output, .set = gpio1_set,
.get = au1000_gpio1_get, .to_irq = gpio1_to_irq,
.set = au1000_gpio1_set, .base = ALCHEMY_GPIO1_BASE,
.base = 0, .ngpio = ALCHEMY_GPIO1_NUM,
.ngpio = 32,
},
}, },
#if !defined(CONFIG_SOC_AU1000) #if !defined(CONFIG_SOC_AU1000)
[1] = { [1] = {
.regbase = (void __iomem *)GPIO2_BASE, .label = "alchemy-gpio2",
.chip = { .direction_input = gpio2_direction_input,
.label = "au1000-gpio2", .direction_output = gpio2_direction_output,
.direction_input = au1000_gpio2_direction_input, .get = gpio2_get,
.direction_output = au1000_gpio2_direction_output, .set = gpio2_set,
.get = au1000_gpio2_get, .to_irq = gpio2_to_irq,
.set = au1000_gpio2_set, .base = ALCHEMY_GPIO2_BASE,
.base = AU1XXX_GPIO_BASE, .ngpio = ALCHEMY_GPIO2_NUM,
.ngpio = 32,
},
}, },
#endif #endif
}; };
static int __init au1000_gpio_init(void) static int __init alchemy_gpiolib_init(void)
{ {
gpiochip_add(&au1000_gpio_chip[0].chip); gpiochip_add(&alchemy_gpio_chip[0]);
#if !defined(CONFIG_SOC_AU1000) #if !defined(CONFIG_SOC_AU1000)
gpiochip_add(&au1000_gpio_chip[1].chip); gpiochip_add(&alchemy_gpio_chip[1]);
#endif #endif
return 0; return 0;
} }
arch_initcall(au1000_gpio_init); arch_initcall(alchemy_gpiolib_init);
...@@ -27,8 +27,9 @@ ...@@ -27,8 +27,9 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <asm/cacheflush.h> #include <linux/gpio.h>
#include <asm/cacheflush.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
void au1000_restart(char *command) void au1000_restart(char *command)
...@@ -161,7 +162,7 @@ void au1000_halt(void) ...@@ -161,7 +162,7 @@ void au1000_halt(void)
#else #else
printk(KERN_NOTICE "\n** You can safely turn off the power\n"); printk(KERN_NOTICE "\n** You can safely turn off the power\n");
#ifdef CONFIG_MIPS_MIRAGE #ifdef CONFIG_MIPS_MIRAGE
au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); gpio_direction_output(210, 1);
#endif #endif
#ifdef CONFIG_MIPS_DB1200 #ifdef CONFIG_MIPS_DB1200
au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
......
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
...@@ -94,12 +95,12 @@ void __init board_setup(void) ...@@ -94,12 +95,12 @@ void __init board_setup(void)
#endif #endif
bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */
#ifdef CONFIG_MIPS_MIRAGE
/* Enable GPIO[31:0] inputs */ /* Enable GPIO[31:0] inputs */
au_writel(0, SYS_PININPUTEN); alchemy_gpio1_input_enable();
/* GPIO[20] is output, tristate the other input primary GPIOs */ #ifdef CONFIG_MIPS_MIRAGE
au_writel(~(1 << 20), SYS_TRIOUTCLR); /* GPIO[20] is output */
alchemy_gpio_direction_output(20, 0);
/* Set GPIO[210:208] instead of SSI_0 */ /* Set GPIO[210:208] instead of SSI_0 */
pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
...@@ -118,8 +119,7 @@ void __init board_setup(void) ...@@ -118,8 +119,7 @@ void __init board_setup(void)
* Enable speaker amplifier. This should * Enable speaker amplifier. This should
* be part of the audio driver. * be part of the audio driver.
*/ */
au_writel(au_readl(GPIO2_DIR) | 0x200, GPIO2_DIR); alchemy_gpio_direction_output(209, 1);
au_writel(0x02000200, GPIO2_OUTPUT);
#endif #endif
au_sync(); au_sync();
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
*/ */
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
...@@ -130,8 +131,11 @@ void __init board_setup(void) ...@@ -130,8 +131,11 @@ void __init board_setup(void)
pin_func |= SYS_PF_USB; pin_func |= SYS_PF_USB;
au_writel(pin_func, SYS_PINFUNC); au_writel(pin_func, SYS_PINFUNC);
au_writel(0x2800, SYS_TRIOUTCLR);
au_writel(0x0030, SYS_OUTPUTCLR); alchemy_gpio_direction_input(11);
alchemy_gpio_direction_input(13);
alchemy_gpio_direction_output(4, 0);
alchemy_gpio_direction_output(5, 0);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
/* Make GPIO 15 an input (for interrupt line) */ /* Make GPIO 15 an input (for interrupt line) */
...@@ -140,7 +144,7 @@ void __init board_setup(void) ...@@ -140,7 +144,7 @@ void __init board_setup(void)
pin_func |= SYS_PF_I2S; pin_func |= SYS_PF_I2S;
au_writel(pin_func, SYS_PINFUNC); au_writel(pin_func, SYS_PINFUNC);
au_writel(0x8000, SYS_TRIOUTCLR); alchemy_gpio_direction_input(15);
static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00; static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
au_writel(static_cfg0, MEM_STCFG0); au_writel(static_cfg0, MEM_STCFG0);
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -88,7 +89,7 @@ void __init board_setup(void) ...@@ -88,7 +89,7 @@ void __init board_setup(void)
/* Set AUX clock to 12 MHz * 8 = 96 MHz */ /* Set AUX clock to 12 MHz * 8 = 96 MHz */
au_writel(8, SYS_AUXPLL); au_writel(8, SYS_AUXPLL);
au_writel(0, SYS_PININPUTEN); alchemy_gpio1_input_enable();
udelay(100); udelay(100);
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
......
...@@ -23,8 +23,9 @@ ...@@ -23,8 +23,9 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/init.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
...@@ -90,11 +91,12 @@ void __init board_setup(void) ...@@ -90,11 +91,12 @@ void __init board_setup(void)
au_writel(0, SYS_PINSTATERD); au_writel(0, SYS_PINSTATERD);
udelay(100); udelay(100);
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* GPIO201 is input for PCMCIA card detect */ /* GPIO201 is input for PCMCIA card detect */
/* GPIO203 is input for PCMCIA interrupt request */ /* GPIO203 is input for PCMCIA interrupt request */
au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR); alchemy_gpio_direction_input(201);
alchemy_gpio_direction_input(203);
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* Zero and disable FREQ2 */ /* Zero and disable FREQ2 */
sys_freqctrl = au_readl(SYS_FREQCTRL0); sys_freqctrl = au_readl(SYS_FREQCTRL0);
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <linux/suspend.h> #include <linux/suspend.h>
#include <linux/sysfs.h> #include <linux/sysfs.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio.h>
/* /*
* Generic suspend userspace interface for Alchemy development boards. * Generic suspend userspace interface for Alchemy development boards.
...@@ -26,7 +27,7 @@ static unsigned long db1x_pm_last_wakesrc; ...@@ -26,7 +27,7 @@ static unsigned long db1x_pm_last_wakesrc;
static int db1x_pm_enter(suspend_state_t state) static int db1x_pm_enter(suspend_state_t state)
{ {
/* enable GPIO based wakeup */ /* enable GPIO based wakeup */
au_writel(1, SYS_PININPUTEN); alchemy_gpio1_input_enable();
/* clear and setup wake cause and source */ /* clear and setup wake cause and source */
au_writel(0, SYS_WAKEMSK); au_writel(0, SYS_WAKEMSK);
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
...@@ -55,10 +56,11 @@ void __init board_setup(void) ...@@ -55,10 +56,11 @@ void __init board_setup(void)
} }
#endif #endif
alchemy_gpio2_enable();
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* Enable USB power switch */ /* Enable USB power switch */
au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); alchemy_gpio_direction_output(204, 0);
au_writel(0x100000, GPIO2_OUTPUT);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
...@@ -74,14 +76,14 @@ void __init board_setup(void) ...@@ -74,14 +76,14 @@ void __init board_setup(void)
/* Initialize GPIO */ /* Initialize GPIO */
au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */ alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */ alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */ alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
/* Enable LED and set it to green */ /* Enable LED and set it to green */
au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR); alchemy_gpio_direction_output(211, 1); /* green on */
au_writel(0x18000800, GPIO2_OUTPUT); alchemy_gpio_direction_output(212, 0); /* red off */
board_pci_idsel = mtx1_pci_idsel; board_pci_idsel = mtx1_pci_idsel;
...@@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert) ...@@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
if (assert && devsel != 0) if (assert && devsel != 0)
/* Suppress signal to Cardbus */ /* Suppress signal to Cardbus */
au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ gpio_set_value(1, 0); /* set EXT_IO3 OFF */
else else
au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ gpio_set_value(1, 1); /* set EXT_IO3 ON */
au_sync_udelay(1); au_sync_udelay(1);
return 1; return 1;
} }
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/delay.h> #include <linux/delay.h>
...@@ -50,6 +51,9 @@ void __init board_setup(void) ...@@ -50,6 +51,9 @@ void __init board_setup(void)
} }
#endif #endif
alchemy_gpio1_input_enable();
alchemy_gpio2_enable();
/* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
pin_func |= SYS_PF_UR3; pin_func |= SYS_PF_UR3;
...@@ -65,20 +69,19 @@ void __init board_setup(void) ...@@ -65,20 +69,19 @@ void __init board_setup(void)
au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */ au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
#ifdef CONFIG_PCMCIA_XXS1500 #ifdef CONFIG_PCMCIA_XXS1500
/* Setup PCMCIA signals */
au_writel(0, SYS_PININPUTEN);
/* GPIO 0, 1, and 4 are inputs */ /* GPIO 0, 1, and 4 are inputs */
au_writel(1 | (1 << 1) | (1 << 4), SYS_TRIOUTCLR); alchemy_gpio_direction_input(0);
alchemy_gpio_direction_input(1);
alchemy_gpio_direction_input(4);
/* Enable GPIO2 if not already enabled */
au_writel(1, GPIO2_ENABLE);
/* GPIO2 208/9/10/11 are inputs */ /* GPIO2 208/9/10/11 are inputs */
au_writel((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11), GPIO2_DIR); alchemy_gpio_direction_input(208);
alchemy_gpio_direction_input(209);
alchemy_gpio_direction_input(210);
alchemy_gpio_direction_input(211);
/* Turn off power */ /* Turn off power */
au_writel((au_readl(GPIO2_PINSTATE) & ~(1 << 14)) | (1 << 30), alchemy_gpio_direction_output(214, 0);
GPIO2_OUTPUT);
#endif #endif
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
......
...@@ -14,5 +14,9 @@ obj-y += dma-octeon.o flash_setup.o ...@@ -14,5 +14,9 @@ obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o obj-y += octeon-memcpy.o
obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_PCI) += pci-common.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_PCI_MSI) += msi.o
EXTRA_CFLAGS += -Werror EXTRA_CFLAGS += -Werror
This diff is collapsed.
...@@ -11,3 +11,4 @@ ...@@ -11,3 +11,4 @@
obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/module.h>
#include <asm/octeon/cvmx.h> #include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-spinlock.h> #include <asm/octeon/cvmx-spinlock.h>
...@@ -97,6 +98,33 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment) ...@@ -97,6 +98,33 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
return cvmx_bootmem_alloc_range(size, alignment, 0, 0); return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
} }
void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
uint64_t max_addr, uint64_t align,
char *name)
{
int64_t addr;
addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
align, name, 0);
if (addr >= 0)
return cvmx_phys_to_ptr(addr);
else
return NULL;
}
void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
char *name)
{
return cvmx_bootmem_alloc_named_range(size, address, address + size,
0, name);
}
void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
{
return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name);
}
EXPORT_SYMBOL(cvmx_bootmem_alloc_named);
int cvmx_bootmem_free_named(char *name) int cvmx_bootmem_free_named(char *name)
{ {
return cvmx_bootmem_phy_named_block_free(name, 0); return cvmx_bootmem_phy_named_block_free(name, 0);
...@@ -106,6 +134,7 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name) ...@@ -106,6 +134,7 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name)
{ {
return cvmx_bootmem_phy_named_block_find(name, 0); return cvmx_bootmem_phy_named_block_find(name, 0);
} }
EXPORT_SYMBOL(cvmx_bootmem_find_named_block);
void cvmx_bootmem_lock(void) void cvmx_bootmem_lock(void)
{ {
...@@ -584,3 +613,78 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags) ...@@ -584,3 +613,78 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
cvmx_bootmem_unlock(); cvmx_bootmem_unlock();
return named_block_ptr != NULL; /* 0 on failure, 1 on success */ return named_block_ptr != NULL; /* 0 on failure, 1 on success */
} }
int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
uint64_t max_addr,
uint64_t alignment,
char *name,
uint32_t flags)
{
int64_t addr_allocated;
struct cvmx_bootmem_named_block_desc *named_block_desc_ptr;
#ifdef DEBUG
cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: "
"0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
(unsigned long long)size,
(unsigned long long)min_addr,
(unsigned long long)max_addr,
(unsigned long long)alignment,
name);
#endif
if (cvmx_bootmem_desc->major_version != 3) {
cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
"%d.%d at addr: %p\n",
(int)cvmx_bootmem_desc->major_version,
(int)cvmx_bootmem_desc->minor_version,
cvmx_bootmem_desc);
return -1;
}
/*
* Take lock here, as name lookup/block alloc/name add need to
* be atomic.
*/
if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
/* Get pointer to first available named block descriptor */
named_block_desc_ptr =
cvmx_bootmem_phy_named_block_find(NULL,
flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
/*
* Check to see if name already in use, return error if name
* not available or no more room for blocks.
*/
if (cvmx_bootmem_phy_named_block_find(name,
flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr) {
if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
return -1;
}
/*
* Round size up to mult of minimum alignment bytes We need
* the actual size allocated to allow for blocks to be
* coallesced when they are freed. The alloc routine does the
* same rounding up on all allocations.
*/
size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1));
addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr,
alignment,
flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
if (addr_allocated >= 0) {
named_block_desc_ptr->base_addr = addr_allocated;
named_block_desc_ptr->size = size;
strncpy(named_block_desc_ptr->name, name,
cvmx_bootmem_desc->named_block_name_len);
named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
}
if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
return addr_allocated;
}
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
*
* Fixes and workaround for Octeon chip errata. This file
* contains functions called by cvmx-helper to workaround known
* chip errata. For the most part, code doesn't need to call
* these functions directly.
*
*/
#include <linux/module.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-helper-jtag.h>
/**
* Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
* 1 doesn't work properly. The following code disables 2nd order
* CDR for the specified QLM.
*
* @qlm: QLM to disable 2nd order CDR for.
*/
void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
{
int lane;
cvmx_helper_qlm_jtag_init();
/* We need to load all four lanes of the QLM, a total of 1072 bits */
for (lane = 0; lane < 4; lane++) {
/*
* Each lane has 268 bits. We need to set
* cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
* 1. All other bits are zero. Bits go in LSB first,
* so start off with the zeros for bits <63:0>.
*/
cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
/* cfg_cdr_incx<67:64>=3 */
cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
/* Zeros for bits <76:68> */
cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
/* cfg_cdr_secord<77>=1 */
cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
/* Zeros for bits <267:78> */
cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
}
cvmx_helper_qlm_jtag_update(qlm);
}
EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
*
* Helper utilities for qlm_jtag.
*
*/
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-helper-jtag.h>
/**
* Initialize the internal QLM JTAG logic to allow programming
* of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
* These functions should only be used at the direction of Cavium
* Networks. Programming incorrect values into the JTAG chain
* can cause chip damage.
*/
void cvmx_helper_qlm_jtag_init(void)
{
union cvmx_ciu_qlm_jtgc jtgc;
uint32_t clock_div = 0;
uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
divisor = (divisor - 1) >> 2;
/* Convert the divisor into a power of 2 shift */
while (divisor) {
clock_div++;
divisor = divisor >> 1;
}
/*
* Clock divider for QLM JTAG operations. eclk is divided by
* 2^(CLK_DIV + 2)
*/
jtgc.u64 = 0;
jtgc.s.clk_div = clock_div;
jtgc.s.mux_sel = 0;
if (OCTEON_IS_MODEL(OCTEON_CN52XX))
jtgc.s.bypass = 0x3;
else
jtgc.s.bypass = 0xf;
cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
cvmx_read_csr(CVMX_CIU_QLM_JTGC);
}
/**
* Write up to 32bits into the QLM jtag chain. Bits are shifted
* into the MSB and out the LSB, so you should shift in the low
* order bits followed by the high order bits. The JTAG chain is
* 4 * 268 bits long, or 1072.
*
* @qlm: QLM to shift value into
* @bits: Number of bits to shift in (1-32).
* @data: Data to shift in. Bit 0 enters the chain first, followed by
* bit 1, etc.
*
* Returns The low order bits of the JTAG chain that shifted out of the
* circle.
*/
uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
{
union cvmx_ciu_qlm_jtgd jtgd;
jtgd.u64 = 0;
jtgd.s.shift = 1;
jtgd.s.shft_cnt = bits - 1;
jtgd.s.shft_reg = data;
if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
jtgd.s.select = 1 << qlm;
cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
do {
jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
} while (jtgd.s.shift);
return jtgd.s.shft_reg >> (32 - bits);
}
/**
* Shift long sequences of zeros into the QLM JTAG chain. It is
* common to need to shift more than 32 bits of zeros into the
* chain. This function is a convience wrapper around
* cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
* zeros at a time.
*
* @qlm: QLM to shift zeros into
* @bits:
*/
void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
{
while (bits > 0) {
int n = bits;
if (n > 32)
n = 32;
cvmx_helper_qlm_jtag_shift(qlm, n, 0);
bits -= n;
}
}
/**
* Program the QLM JTAG chain into all lanes of the QLM. You must
* have already shifted in 268*4, or 1072 bits into the JTAG
* chain. Updating invalid values can possibly cause chip damage.
*
* @qlm: QLM to program
*/
void cvmx_helper_qlm_jtag_update(int qlm)
{
union cvmx_ciu_qlm_jtgd jtgd;
/* Update the new data */
jtgd.u64 = 0;
jtgd.s.update = 1;
if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
jtgd.s.select = 1 << qlm;
cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
do {
jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
} while (jtgd.s.update);
}
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
* This module provides system/board/application information obtained * This module provides system/board/application information obtained
* by the bootloader. * by the bootloader.
*/ */
#include <linux/module.h>
#include <asm/octeon/cvmx.h> #include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-spinlock.h> #include <asm/octeon/cvmx-spinlock.h>
...@@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void) ...@@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void)
{ {
return &(state.sysinfo); return &(state.sysinfo);
} }
EXPORT_SYMBOL(cvmx_sysinfo_get);
/** /**
* This function is used in non-simple executive environments (such as * This function is used in non-simple executive environments (such as
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h>
#include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include "pci-common.h"
/*
* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
* in use.
*/
static uint64_t msi_free_irq_bitmask;
/*
* Each bit in msi_multiple_irq_bitmask tells that the device using
* this bit in msi_free_irq_bitmask is also using the next bit. This
* is used so we can disable all of the MSI interrupts when a device
* uses multiple.
*/
static uint64_t msi_multiple_irq_bitmask;
/*
* This lock controls updates to msi_free_irq_bitmask and
* msi_multiple_irq_bitmask.
*/
static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
/**
* Called when a driver request MSI interrupts instead of the
* legacy INT A-D. This routine will allocate multiple interrupts
* for MSI devices that support them. A device can override this by
* programming the MSI control bits [6:4] before calling
* pci_enable_msi().
*
* @param dev Device requesting MSI interrupts
* @param desc MSI descriptor
*
* Returns 0 on success.
*/
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
{
struct msi_msg msg;
uint16_t control;
int configured_private_bits;
int request_private_bits;
int irq;
int irq_step;
uint64_t search_mask;
/*
* Read the MSI config to figure out how many IRQs this device
* wants. Most devices only want 1, which will give
* configured_private_bits and request_private_bits equal 0.
*/
pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
&control);
/*
* If the number of private bits has been configured then use
* that value instead of the requested number. This gives the
* driver the chance to override the number of interrupts
* before calling pci_enable_msi().
*/
configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
if (configured_private_bits == 0) {
/* Nothing is configured, so use the hardware requested size */
request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
} else {
/*
* Use the number of configured bits, assuming the
* driver wanted to override the hardware request
* value.
*/
request_private_bits = configured_private_bits;
}
/*
* The PCI 2.3 spec mandates that there are at most 32
* interrupts. If this device asks for more, only give it one.
*/
if (request_private_bits > 5)
request_private_bits = 0;
try_only_one:
/*
* The IRQs have to be aligned on a power of two based on the
* number being requested.
*/
irq_step = 1 << request_private_bits;
/* Mask with one bit for each IRQ */
search_mask = (1 << irq_step) - 1;
/*
* We're going to search msi_free_irq_bitmask_lock for zero
* bits. This represents an MSI interrupt number that isn't in
* use.
*/
spin_lock(&msi_free_irq_bitmask_lock);
for (irq = 0; irq < 64; irq += irq_step) {
if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
msi_free_irq_bitmask |= search_mask << irq;
msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
break;
}
}
spin_unlock(&msi_free_irq_bitmask_lock);
/* Make sure the search for available interrupts didn't fail */
if (irq >= 64) {
if (request_private_bits) {
pr_err("arch_setup_msi_irq: Unable to find %d free "
"interrupts, trying just one",
1 << request_private_bits);
request_private_bits = 0;
goto try_only_one;
} else
panic("arch_setup_msi_irq: Unable to find a free MSI "
"interrupt");
}
/* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
irq += OCTEON_IRQ_MSI_BIT0;
switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_SMALL:
/* When not using big bar, Bar 0 is based at 128MB */
msg.address_lo =
((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
case OCTEON_DMA_BAR_TYPE_BIG:
/* When using big bar, Bar 0 is based at 0 */
msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
break;
case OCTEON_DMA_BAR_TYPE_PCIE:
/* When using PCIe, Bar 0 is based at 0 */
/* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
break;
default:
panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
}
msg.data = irq - OCTEON_IRQ_MSI_BIT0;
/* Update the number of IRQs the device has available to it */
control &= ~PCI_MSI_FLAGS_QSIZE;
control |= request_private_bits << 4;
pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
control);
set_irq_msi(irq, desc);
write_msi_msg(irq, &msg);
return 0;
}
/**
* Called when a device no longer needs its MSI interrupts. All
* MSI interrupts for the device are freed.
*
* @irq: The devices first irq number. There may be multple in sequence.
*/
void arch_teardown_msi_irq(unsigned int irq)
{
int number_irqs;
uint64_t bitmask;
if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
panic("arch_teardown_msi_irq: Attempted to teardown illegal "
"MSI interrupt (%d)", irq);
irq -= OCTEON_IRQ_MSI_BIT0;
/*
* Count the number of IRQs we need to free by looking at the
* msi_multiple_irq_bitmask. Each bit set means that the next
* IRQ is also owned by this device.
*/
number_irqs = 0;
while ((irq+number_irqs < 64) &&
(msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
number_irqs++;
number_irqs++;
/* Mask with one bit for each IRQ */
bitmask = (1 << number_irqs) - 1;
/* Shift the mask to the correct bit location */
bitmask <<= irq;
if ((msi_free_irq_bitmask & bitmask) != bitmask)
panic("arch_teardown_msi_irq: Attempted to teardown MSI "
"interrupt (%d) not in use", irq);
/* Checks are done, update the in use bitmask */
spin_lock(&msi_free_irq_bitmask_lock);
msi_free_irq_bitmask &= ~bitmask;
msi_multiple_irq_bitmask &= ~bitmask;
spin_unlock(&msi_free_irq_bitmask_lock);
}
/**
* Called by the interrupt handling code when an MSI interrupt
* occurs.
*
* @param cpl
* @param dev_id
*
* @return
*/
static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
{
uint64_t msi_bits;
int irq;
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
else
msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
irq = fls64(msi_bits);
if (irq) {
irq += OCTEON_IRQ_MSI_BIT0 - 1;
if (irq_desc[irq].action) {
do_IRQ(irq);
return IRQ_HANDLED;
} else {
pr_err("Spurious MSI interrupt %d\n", irq);
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
/* These chips have PCIe */
cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
1ull << (irq -
OCTEON_IRQ_MSI_BIT0));
} else {
/* These chips have PCI */
cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
1ull << (irq -
OCTEON_IRQ_MSI_BIT0));
}
}
}
return IRQ_NONE;
}
/**
* Initializes the MSI interrupt handling code
*
* @return
*/
int octeon_msi_initialize(void)
{
int r;
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[0:63]", octeon_msi_interrupt);
} else if (octeon_is_pci_host()) {
r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[0:15]", octeon_msi_interrupt);
r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[16:31]", octeon_msi_interrupt);
r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[32:47]", octeon_msi_interrupt);
r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[48:63]", octeon_msi_interrupt);
}
return 0;
}
subsys_initcall(octeon_msi_initialize);
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#include <linux/hardirq.h> #include <linux/hardirq.h>
#include <asm/octeon/octeon.h> #include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include <asm/octeon/cvmx-npi-defs.h>
DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
#include "pci-common.h"
typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
/**
* Map a PCI device to the appropriate interrupt line
*
* @param dev The Linux PCI device structure for the device to map
* @param slot The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @param pin The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* @return Interrupt number for the device
*/
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (octeon_pcibios_map_irq)
return octeon_pcibios_map_irq(dev, slot, pin);
else
panic("octeon_pcibios_map_irq doesn't point to a "
"pcibios_map_irq() function");
}
/**
* Called to perform platform specific PCI setup
*
* @param dev
* @return
*/
int pcibios_plat_dev_init(struct pci_dev *dev)
{
uint16_t config;
uint32_t dconfig;
int pos;
/*
* Force the Cache line setting to 64 bytes. The standard
* Linux bus scan doesn't seem to set it. Octeon really has
* 128 byte lines, but Intel bridges get really upset if you
* try and set values above 64 bytes. Value is specified in
* 32bit words.
*/
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
/* Set latency timers for all devices */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
/* Enable reporting System errors and parity errors on all devices */
/* Enable parity checking and error reporting */
pci_read_config_word(dev, PCI_COMMAND, &config);
config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
pci_write_config_word(dev, PCI_COMMAND, config);
if (dev->subordinate) {
/* Set latency timers on sub bridges */
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
/* More bridge error detection */
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
}
/* Enable the PCIe normal error reporting */
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (pos) {
/* Update Device Control */
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
/* Correctable Error Reporting */
config |= PCI_EXP_DEVCTL_CERE;
/* Non-Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_NFERE;
/* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_FERE;
/* Unsupported Request */
config |= PCI_EXP_DEVCTL_URRE;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
}
/* Find the Advanced Error Reporting capability */
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
if (pos) {
/* Clear Uncorrectable Error Status */
pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
&dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
dconfig);
/* Enable reporting of all uncorrectable errors */
/* Uncorrectable Error Mask - turned on bits disable errors */
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
/*
* Leave severity at HW default. This only controls if
* errors are reported as uncorrectable or
* correctable, not if the error is reported.
*/
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
/* Clear Correctable Error Status */
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
/* Enable reporting of all correctable errors */
/* Correctable Error Mask - turned on bits disable errors */
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
/* Advanced Error Capabilities */
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
/* ECRC Generation Enable */
if (config & PCI_ERR_CAP_ECRC_GENC)
config |= PCI_ERR_CAP_ECRC_GENE;
/* ECRC Check Enable */
if (config & PCI_ERR_CAP_ECRC_CHKC)
config |= PCI_ERR_CAP_ECRC_CHKE;
pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
/* Report all errors to the root complex */
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
PCI_ERR_ROOT_CMD_COR_EN |
PCI_ERR_ROOT_CMD_NONFATAL_EN |
PCI_ERR_ROOT_CMD_FATAL_EN);
/* Clear the Root status register */
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
}
return 0;
}
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
*/
#ifndef __OCTEON_PCI_COMMON_H__
#define __OCTEON_PCI_COMMON_H__
#include <linux/pci.h>
/* Some PCI cards require delays when accessing config space. */
#define PCI_CONFIG_SPACE_DELAY 10000
/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
Octeon specific version pointed to by this variable. This function needs to
change for PCI or PCIe based hosts */
extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
/* The following defines are only used when octeon_dma_bar_type =
OCTEON_DMA_BAR_TYPE_BIG */
#define OCTEON_PCI_BAR1_HOLE_BITS 5
#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
enum octeon_dma_bar_type {
OCTEON_DMA_BAR_TYPE_INVALID,
OCTEON_DMA_BAR_TYPE_SMALL,
OCTEON_DMA_BAR_TYPE_BIG,
OCTEON_DMA_BAR_TYPE_PCIE
};
/**
* This is a variable to tell the DMA mapping system in dma-octeon.c
* how to map PCI DMA addresses.
*/
extern enum octeon_dma_bar_type octeon_dma_bar_type;
#endif
This diff is collapsed.
This diff is collapsed.
...@@ -147,6 +147,10 @@ ...@@ -147,6 +147,10 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2) cpu_has_mips64r1 | cpu_has_mips64r2)
#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
#endif
/* /*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
...@@ -230,4 +234,8 @@ ...@@ -230,4 +234,8 @@
#define cpu_scache_line_size() cpu_data[0].scache.linesz #define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif #endif
#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits 0
#endif
#endif /* __ASM_CPU_FEATURES_H */ #endif /* __ASM_CPU_FEATURES_H */
...@@ -15,7 +15,7 @@ extern void __delay(unsigned int loops); ...@@ -15,7 +15,7 @@ extern void __delay(unsigned int loops);
extern void __ndelay(unsigned int ns); extern void __ndelay(unsigned int ns);
extern void __udelay(unsigned int us); extern void __udelay(unsigned int us);
#define ndelay(ns) __udelay(ns) #define ndelay(ns) __ndelay(ns)
#define udelay(us) __udelay(us) #define udelay(us) __udelay(us)
/* make sure "usecs *= ..." in udelay do not overflow. */ /* make sure "usecs *= ..." in udelay do not overflow. */
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008, 2009 Cavium Networks, Inc.
*/
#ifndef __ASM_HUGETLB_H
#define __ASM_HUGETLB_H
#include <asm/page.h>
static inline int is_hugepage_only_range(struct mm_struct *mm,
unsigned long addr,
unsigned long len)
{
return 0;
}
static inline int prepare_hugepage_range(struct file *file,
unsigned long addr,
unsigned long len)
{
unsigned long task_size = STACK_TOP;
struct hstate *h = hstate_file(file);
if (len & ~huge_page_mask(h))
return -EINVAL;
if (addr & ~huge_page_mask(h))
return -EINVAL;
if (len > task_size)
return -ENOMEM;
if (task_size - len < addr)
return -EINVAL;
return 0;
}
static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
{
}
static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
unsigned long addr,
unsigned long end,
unsigned long floor,
unsigned long ceiling)
{
free_pgd_range(tlb, addr, end, floor, ceiling);
}
static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
set_pte_at(mm, addr, ptep, pte);
}
static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
pte_t clear;
pte_t pte = *ptep;
pte_val(clear) = (unsigned long)invalid_pte_table;
set_pte_at(mm, addr, ptep, clear);
return pte;
}
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
}
static inline int huge_pte_none(pte_t pte)
{
unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
return !val || (val == (unsigned long)invalid_pte_table);
}
static inline pte_t huge_pte_wrprotect(pte_t pte)
{
return pte_wrprotect(pte);
}
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
ptep_set_wrprotect(mm, addr, ptep);
}
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr,
pte_t *ptep, pte_t pte,
int dirty)
{
return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
}
static inline pte_t huge_ptep_get(pte_t *ptep)
{
return *ptep;
}
static inline int arch_prepare_hugepage(struct page *page)
{
return 0;
}
static inline void arch_release_hugepage(struct page *page)
{
}
#endif /* __ASM_HUGETLB_H */
...@@ -3,40 +3,16 @@ ...@@ -3,40 +3,16 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) 1995, 96, 99, 2001 Ralf Baechle * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) 2009 Wind River Systems
* Written by Ralf Baechle <ralf@linux-mips.org>
*/ */
#ifndef _ASM_IOCTL_H #ifndef __ASM_IOCTL_H
#define _ASM_IOCTL_H #define __ASM_IOCTL_H
/*
* The original linux ioctl numbering scheme was just a general
* "anything goes" setup, where more or less random numbers were
* assigned. Sorry, I was clueless when I started out on this.
*
* On the alpha, we'll try to clean it up a bit, using a more sane
* ioctl numbering, and also trying to be compatible with OSF/1 in
* the process. I'd like to clean it up for the i386 as well, but
* it's so painful recognizing both the new and the old numbers..
*
* The same applies for for the MIPS ABI; in fact even the macros
* from Linux/Alpha fit almost perfectly.
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 13 #define _IOC_SIZEBITS 13
#define _IOC_DIRBITS 3 #define _IOC_DIRBITS 3
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
/* /*
* Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
* And this turns out useful to catch old ioctl numbers in header * And this turns out useful to catch old ioctl numbers in header
...@@ -46,53 +22,6 @@ ...@@ -46,53 +22,6 @@
#define _IOC_READ 2U #define _IOC_READ 2U
#define _IOC_WRITE 4U #define _IOC_WRITE 4U
/* #include <asm-generic/ioctl.h>
* The following are included for compatibility
*/
#define _IOC_VOID 0x20000000
#define _IOC_OUT 0x40000000
#define _IOC_IN 0x80000000
#define _IOC_INOUT (IOC_IN|IOC_OUT)
#define _IOC(dir, type, nr, size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
#ifdef __KERNEL__
/* provoke compile error for invalid uses of size argument */
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) \
((sizeof(t) == sizeof(t[1]) && \
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
sizeof(t) : __invalid_size_argument_for_IOC)
#else
#define _IOC_TYPECHECK(t) (sizeof(t))
#endif
/* used to create numbers */
#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
/* used to decode them.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
/* ...and for the drivers/sound files... */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#endif /* _ASM_IOCTL_H */ #endif /* __ASM_IOCTL_H */
/*
* FILE NAME au1000_gpio.h
*
* BRIEF MODULE DESCRIPTION
* API to Alchemy Au1xx0 GPIO device.
*
* Author: MontaVista Software, Inc. <source@mvista.com>
* Steve Longerbeam
*
* Copyright 2001, 2008 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __AU1000_GPIO_H
#define __AU1000_GPIO_H
#include <linux/ioctl.h>
#define AU1000GPIO_IOC_MAGIC 'A'
#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
#ifdef __KERNEL__
extern u32 get_au1000_avail_gpio_mask(void);
extern int au1000gpio_tristate(u32 data);
extern int au1000gpio_in(u32 *data);
extern int au1000gpio_set(u32 data);
extern int au1000gpio_clear(u32 data);
extern int au1000gpio_out(u32 data);
#endif
#endif
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#ifndef _AU1XXX_GPIO_H_ #ifndef _ALCHEMY_GPIO_H_
#define _AU1XXX_GPIO_H_ #define _ALCHEMY_GPIO_H_
#include <linux/types.h> #if defined(CONFIG_ALCHEMY_GPIO_AU1000)
#define AU1XXX_GPIO_BASE 200 #include <asm/mach-au1x00/gpio-au1000.h>
/* GPIO bank 1 offsets */ #endif
#define AU1000_GPIO1_TRI_OUT 0x0100
#define AU1000_GPIO1_OUT 0x0108
#define AU1000_GPIO1_ST 0x0110
#define AU1000_GPIO1_CLR 0x010C
/* GPIO bank 2 offsets */ #endif /* _ALCHEMY_GPIO_H_ */
#define AU1000_GPIO2_DIR 0x00
#define AU1000_GPIO2_RSVD 0x04
#define AU1000_GPIO2_OUT 0x08
#define AU1000_GPIO2_ST 0x0C
#define AU1000_GPIO2_INT 0x10
#define AU1000_GPIO2_EN 0x14
#define GPIO2_OUT_EN_MASK 0x00010000
#define gpio_to_irq(gpio) NULL
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#include <asm-generic/gpio.h>
#endif /* _AU1XXX_GPIO_H_ */
...@@ -37,6 +37,9 @@ static inline int gpio_direction_input(unsigned gpio) ...@@ -37,6 +37,9 @@ static inline int gpio_direction_input(unsigned gpio)
static inline int gpio_direction_output(unsigned gpio, int value) static inline int gpio_direction_output(unsigned gpio, int value)
{ {
/* first set the gpio out value */
ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
/* then set the gpio mode */
ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio); ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
return 0; return 0;
} }
......
...@@ -47,11 +47,13 @@ ...@@ -47,11 +47,13 @@
#define cpu_has_mips32r2 0 #define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0 #define cpu_has_mips64r1 0
#define cpu_has_mips64r2 1 #define cpu_has_mips64r2 1
#define cpu_has_mips_r2_exec_hazard 0
#define cpu_has_dsp 0 #define cpu_has_dsp 0
#define cpu_has_mipsmt 0 #define cpu_has_mipsmt 0
#define cpu_has_userlocal 0 #define cpu_has_userlocal 0
#define cpu_has_vint 0 #define cpu_has_vint 0
#define cpu_has_veic 0 #define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
#define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1
......
...@@ -30,12 +30,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, ...@@ -30,12 +30,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
} }
static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{ {
return dma_addr; return dma_addr;
} }
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{ {
octeon_unmap_dma_mem(dev, dma_addr); octeon_unmap_dma_mem(dev, dma_addr);
} }
......
...@@ -23,12 +23,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, ...@@ -23,12 +23,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
return page_to_phys(page); return page_to_phys(page);
} }
static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{ {
return dma_addr; return dma_addr;
} }
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{ {
} }
......
...@@ -33,12 +33,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ...@@ -33,12 +33,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
return pa; return pa;
} }
static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) static unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{ {
return dma_addr & ~(0xffUL << 56); return dma_addr & ~(0xffUL << 56);
} }
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{ {
} }
......
...@@ -50,7 +50,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ...@@ -50,7 +50,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
} }
/* This is almost certainly wrong but it's what dma-ip32.c used to use */ /* This is almost certainly wrong but it's what dma-ip32.c used to use */
static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) static unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{ {
unsigned long addr = dma_addr & RAM_OFFSET_MASK; unsigned long addr = dma_addr & RAM_OFFSET_MASK;
...@@ -60,7 +61,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) ...@@ -60,7 +61,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
return addr; return addr;
} }
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{ {
} }
......
...@@ -22,12 +22,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ...@@ -22,12 +22,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
return vdma_alloc(page_to_phys(page), PAGE_SIZE); return vdma_alloc(page_to_phys(page), PAGE_SIZE);
} }
static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) static unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{ {
return vdma_log2phys(dma_addr); return vdma_log2phys(dma_addr);
} }
static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{ {
vdma_free(dma_addr); vdma_free(dma_addr);
} }
......
...@@ -25,12 +25,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, ...@@ -25,12 +25,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
return page_to_phys(page) | 0x80000000; return page_to_phys(page) | 0x80000000;
} }
static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{ {
return dma_addr & 0x7fffffff; return dma_addr & 0x7fffffff;
} }
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{ {
} }
......
...@@ -53,11 +53,6 @@ ...@@ -53,11 +53,6 @@
#define cpu_has_smartmips 0 #define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0 #define cpu_has_vtag_icache 0
/* #define cpu_has_dc_aliases ? */
/* #define cpu_has_ic_fills_f_dc ? */
/* #define cpu_has_pindexed_dcache ? */
/* #define cpu_icache_snoops_remote_store ? */
#define cpu_has_mips32r1 1 #define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0 #define cpu_has_mips32r2 0
......
...@@ -220,6 +220,22 @@ ...@@ -220,6 +220,22 @@
#error Bad page size configuration! #error Bad page size configuration!
#endif #endif
/*
* Default huge tlb size for a given kernel configuration
*/
#ifdef CONFIG_PAGE_SIZE_4KB
#define PM_HUGE_MASK PM_1M
#elif defined(CONFIG_PAGE_SIZE_8KB)
#define PM_HUGE_MASK PM_4M
#elif defined(CONFIG_PAGE_SIZE_16KB)
#define PM_HUGE_MASK PM_16M
#elif defined(CONFIG_PAGE_SIZE_32KB)
#define PM_HUGE_MASK PM_64M
#elif defined(CONFIG_PAGE_SIZE_64KB)
#define PM_HUGE_MASK PM_256M
#elif defined(CONFIG_HUGETLB_PAGE)
#error Bad page size configuration for hugetlbfs!
#endif
/* /*
* Values used for computation of new tlb entries * Values used for computation of new tlb entries
......
...@@ -157,6 +157,13 @@ enum cvmx_board_types_enum { ...@@ -157,6 +157,13 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_NIC_XLE_4G = 21, CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
CVMX_BOARD_TYPE_EBT5600 = 22, CVMX_BOARD_TYPE_EBT5600 = 22,
CVMX_BOARD_TYPE_EBH5201 = 23, CVMX_BOARD_TYPE_EBH5201 = 23,
CVMX_BOARD_TYPE_EBT5200 = 24,
CVMX_BOARD_TYPE_CB5600 = 25,
CVMX_BOARD_TYPE_CB5601 = 26,
CVMX_BOARD_TYPE_CB5200 = 27,
/* Special 'generic' board type, supports many boards */
CVMX_BOARD_TYPE_GENERIC = 28,
CVMX_BOARD_TYPE_EBH5610 = 29,
CVMX_BOARD_TYPE_MAX, CVMX_BOARD_TYPE_MAX,
/* /*
...@@ -228,6 +235,12 @@ static inline const char *cvmx_board_type_to_string(enum ...@@ -228,6 +235,12 @@ static inline const char *cvmx_board_type_to_string(enum
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
/* Customer boards listed here */ /* Customer boards listed here */
......
...@@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, ...@@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
* Returns 0 on failure, * Returns 0 on failure,
* !0 on success * !0 on success
*/ */
/**
* Allocate a block of memory from the free list that was passed
* to the application by the bootloader, and assign it a name in the
* global named block table. (part of the cvmx_bootmem_descriptor_t structure)
* Named blocks can later be freed.
*
* @size: Size in bytes of block to allocate
* @alignment: Alignment required - must be power of 2
* @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
*
* Returns a pointer to block of memory, NULL on error
*/
extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
char *name);
/**
* Allocate a block of memory from the free list that was passed
* to the application by the bootloader, and assign it a name in the
* global named block table. (part of the cvmx_bootmem_descriptor_t structure)
* Named blocks can later be freed.
*
* @size: Size in bytes of block to allocate
* @address: Physical address to allocate memory at. If this
* memory is not available, the allocation fails.
* @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN
* bytes
*
* Returns a pointer to block of memory, NULL on error
*/
extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
char *name);
/**
* Allocate a block of memory from a specific range of the free list
* that was passed to the application by the bootloader, and assign it
* a name in the global named block table. (part of the
* cvmx_bootmem_descriptor_t structure) Named blocks can later be
* freed. If request cannot be satisfied within the address range
* specified, NULL is returned
*
* @size: Size in bytes of block to allocate
* @min_addr: minimum address of range
* @max_addr: maximum address of range
* @align: Alignment of memory to be allocated. (must be a power of 2)
* @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
*
* Returns a pointer to block of memory, NULL on error
*/
extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
uint64_t max_addr, uint64_t align,
char *name);
extern int cvmx_bootmem_free_named(char *name); extern int cvmx_bootmem_free_named(char *name);
/** /**
...@@ -223,6 +281,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, ...@@ -223,6 +281,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
uint64_t address_max, uint64_t alignment, uint64_t address_max, uint64_t alignment,
uint32_t flags); uint32_t flags);
/**
* Allocates a named block of physical memory from the free list, at
* (optional) requested address and alignment.
*
* @param size size of region to allocate. All requests are rounded
* up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
* bytes size
* @param min_addr Minimum address that block can occupy.
* @param max_addr Specifies the maximum address_min (inclusive) that
* the allocation can use.
* @param alignment Requested alignment of the block. If this
* alignment cannot be met, the allocation fails.
* This must be a power of 2. (Note: Alignment of
* CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
* internally enforced. Requested alignments of less
* than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
* CVMX_BOOTMEM_ALIGNMENT_SIZE.)
* @param name name to assign to named block
* @param flags Flags to control options for the allocation.
*
* @return physical address of block allocated, or -1 on failure
*/
int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
uint64_t max_addr,
uint64_t alignment,
char *name, uint32_t flags);
/** /**
* Finds a named memory block by name. * Finds a named memory block by name.
* Also used for finding an unused entry in the named block table. * Also used for finding an unused entry in the named block table.
......
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_HELPER_ERRATA_H__
#define __CVMX_HELPER_ERRATA_H__
extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
#endif
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...@@ -375,6 +375,18 @@ static inline uint64_t cvmx_get_cycle(void) ...@@ -375,6 +375,18 @@ static inline uint64_t cvmx_get_cycle(void)
return cycle; return cycle;
} }
/**
* Wait for the specified number of cycle
*
*/
static inline void cvmx_wait(uint64_t cycles)
{
uint64_t done = cvmx_get_cycle() + cycles;
while (cvmx_get_cycle() < done)
; /* Spin */
}
/** /**
* Reads a chip global cycle counter. This counts CPU cycles since * Reads a chip global cycle counter. This counts CPU cycles since
* chip reset. The counter is 64 bit. * chip reset. The counter is 64 bit.
......
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obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o
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lib-y = setup.o
lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
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