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Commit 9da51974 authored by John Youn's avatar John Youn Committed by Felipe Balbi
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usb: dwc2: Cleanup some checkpatch issues 

This commmit is the result of running checkpatch --fix.

The results were verified for correctness. Some of the fixes result in
line over 80 char which we will fix manually later.

The following is a summary of what was done by checkpatch:
* Remove externs on function prototypes.
* Replace symbolic permissions with octal.
* Align code to open parens.
* Replace 'unsigned' with 'unsigned int'.
* Remove unneccessary blank lines.
* Add blank lines after declarations.
* Add spaces around operators.
* Remove unnecessary spaces after casts.
* Replace 'x == NULL' with '!x'.
* Replace kzalloc() with kcalloc().
* Concatenate multi-line strings.
* Use the BIT() macro.
Signed-off-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 33e4c1a9
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Inline Side-by-side
Showing with 521 additions and 527 deletions
drivers/usb/dwc2/core.c
View file @ 9da51974
...@@ -104,7 +104,7 @@ static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) ...@@ -104,7 +104,7 @@ static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
gr = &hsotg->gr_backup; gr = &hsotg->gr_backup;
if (!gr->valid) { if (!gr->valid) {
dev_err(hsotg->dev, "%s: no global registers to restore\n", dev_err(hsotg->dev, "%s: no global registers to restore\n",
__func__); __func__);
return -EINVAL; return -EINVAL;
} }
gr->valid = false; gr->valid = false;
...@@ -155,21 +155,21 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) ...@@ -155,21 +155,21 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
ret = dwc2_restore_global_registers(hsotg); ret = dwc2_restore_global_registers(hsotg);
if (ret) { if (ret) {
dev_err(hsotg->dev, "%s: failed to restore registers\n", dev_err(hsotg->dev, "%s: failed to restore registers\n",
__func__); __func__);
return ret; return ret;
} }
if (dwc2_is_host_mode(hsotg)) { if (dwc2_is_host_mode(hsotg)) {
ret = dwc2_restore_host_registers(hsotg); ret = dwc2_restore_host_registers(hsotg);
if (ret) { if (ret) {
dev_err(hsotg->dev, "%s: failed to restore host registers\n", dev_err(hsotg->dev, "%s: failed to restore host registers\n",
__func__); __func__);
return ret; return ret;
} }
} else { } else {
ret = dwc2_restore_device_registers(hsotg); ret = dwc2_restore_device_registers(hsotg);
if (ret) { if (ret) {
dev_err(hsotg->dev, "%s: failed to restore device registers\n", dev_err(hsotg->dev, "%s: failed to restore device registers\n",
__func__); __func__);
return ret; return ret;
} }
} }
...@@ -195,7 +195,7 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) ...@@ -195,7 +195,7 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
ret = dwc2_backup_global_registers(hsotg); ret = dwc2_backup_global_registers(hsotg);
if (ret) { if (ret) {
dev_err(hsotg->dev, "%s: failed to backup global registers\n", dev_err(hsotg->dev, "%s: failed to backup global registers\n",
__func__); __func__);
return ret; return ret;
} }
...@@ -203,14 +203,14 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) ...@@ -203,14 +203,14 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
ret = dwc2_backup_host_registers(hsotg); ret = dwc2_backup_host_registers(hsotg);
if (ret) { if (ret) {
dev_err(hsotg->dev, "%s: failed to backup host registers\n", dev_err(hsotg->dev, "%s: failed to backup host registers\n",
__func__); __func__);
return ret; return ret;
} }
} else { } else {
ret = dwc2_backup_device_registers(hsotg); ret = dwc2_backup_device_registers(hsotg);
if (ret) { if (ret) {
dev_err(hsotg->dev, "%s: failed to backup device registers\n", dev_err(hsotg->dev, "%s: failed to backup device registers\n",
__func__); __func__);
return ret; return ret;
} }
} }
...@@ -793,7 +793,7 @@ void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) ...@@ -793,7 +793,7 @@ void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
} }
/* Returns the controller's GHWCFG2.OTG_MODE. */ /* Returns the controller's GHWCFG2.OTG_MODE. */
unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
{ {
u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
...@@ -804,7 +804,7 @@ unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) ...@@ -804,7 +804,7 @@ unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
/* Returns true if the controller is capable of DRD. */ /* Returns true if the controller is capable of DRD. */
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
{ {
unsigned op_mode = dwc2_op_mode(hsotg); unsigned int op_mode = dwc2_op_mode(hsotg);
return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
...@@ -814,7 +814,7 @@ bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) ...@@ -814,7 +814,7 @@ bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
/* Returns true if the controller is host-only. */ /* Returns true if the controller is host-only. */
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
{ {
unsigned op_mode = dwc2_op_mode(hsotg); unsigned int op_mode = dwc2_op_mode(hsotg);
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
...@@ -823,7 +823,7 @@ bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) ...@@ -823,7 +823,7 @@ bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
/* Returns true if the controller is device-only. */ /* Returns true if the controller is device-only. */
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
{ {
unsigned op_mode = dwc2_op_mode(hsotg); unsigned int op_mode = dwc2_op_mode(hsotg);
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
......
drivers/usb/dwc2/core.h
View file @ 9da51974
...@@ -1101,37 +1101,37 @@ static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) ...@@ -1101,37 +1101,37 @@ static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
* The following functions support initialization of the core driver component * The following functions support initialization of the core driver component
* and the DWC_otg controller * and the DWC_otg controller
*/ */
extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); int dwc2_core_reset(struct dwc2_hsotg *hsotg);
extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
/* /*
* Common core Functions. * Common core Functions.
* The following functions support managing the DWC_otg controller in either * The following functions support managing the DWC_otg controller in either
* device or host mode. * device or host mode.
*/ */
extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
/* This function should be called on every hardware interrupt. */ /* This function should be called on every hardware interrupt. */
extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
/* The device ID match table */ /* The device ID match table */
extern const struct of_device_id dwc2_of_match_table[]; extern const struct of_device_id dwc2_of_match_table[];
extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
/* Parameters */ /* Parameters */
int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
...@@ -1145,7 +1145,7 @@ int dwc2_init_params(struct dwc2_hsotg *hsotg); ...@@ -1145,7 +1145,7 @@ int dwc2_init_params(struct dwc2_hsotg *hsotg);
* are read in and cached so they always read directly from the * are read in and cached so they always read directly from the
* GHWCFG2 register. * GHWCFG2 register.
*/ */
unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
...@@ -1157,6 +1157,7 @@ static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) ...@@ -1157,6 +1157,7 @@ static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
{ {
return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
} }
static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
{ {
return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
...@@ -1165,26 +1166,26 @@ static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) ...@@ -1165,26 +1166,26 @@ static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
/* /*
* Dump core registers and SPRAM * Dump core registers and SPRAM
*/ */
extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
/* /*
* Return OTG version - either 1.3 or 2.0 * Return OTG version - either 1.3 or 2.0
*/ */
extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
/* Gadget defines */ /* Gadget defines */
#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
bool reset); bool reset);
extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
#define dwc2_is_device_connected(hsotg) (hsotg->connected) #define dwc2_is_device_connected(hsotg) (hsotg->connected)
int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
...@@ -1198,11 +1199,11 @@ static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) ...@@ -1198,11 +1199,11 @@ static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{ return 0; } { return 0; }
static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
bool reset) {} bool reset) {}
static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
int testmode) int testmode)
{ return 0; } { return 0; }
#define dwc2_is_device_connected(hsotg) (0) #define dwc2_is_device_connected(hsotg) (0)
static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
...@@ -1212,11 +1213,11 @@ static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) ...@@ -1212,11 +1213,11 @@ static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
#endif #endif
#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
#else #else
......
drivers/usb/dwc2/core_intr.c
View file @ 9da51974
...@@ -317,7 +317,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) ...@@ -317,7 +317,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
hsotg->lx_state); hsotg->lx_state);
if (dwc2_is_device_mode(hsotg)) { if (dwc2_is_device_mode(hsotg)) {
if (hsotg->lx_state == DWC2_L2) { if (hsotg->lx_state == DWC2_L2) {
...@@ -437,7 +437,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) ...@@ -437,7 +437,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
/* Ignore suspend request before enumeration */ /* Ignore suspend request before enumeration */
if (!dwc2_is_device_connected(hsotg)) { if (!dwc2_is_device_connected(hsotg)) {
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"ignore suspend request before enumeration\n"); "ignore suspend request before enumeration\n");
return; return;
} }
...@@ -445,7 +445,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) ...@@ -445,7 +445,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
if (ret) { if (ret) {
if (ret != -ENOTSUPP) if (ret != -ENOTSUPP)
dev_err(hsotg->dev, dev_err(hsotg->dev,
"enter hibernation failed\n"); "enter hibernation failed\n");
goto skip_power_saving; goto skip_power_saving;
} }
......
drivers/usb/dwc2/debug.h
View file @ 9da51974
...@@ -17,8 +17,8 @@ ...@@ -17,8 +17,8 @@
#include "core.h" #include "core.h"
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
extern int dwc2_debugfs_init(struct dwc2_hsotg *); int dwc2_debugfs_init(struct dwc2_hsotg *);
extern void dwc2_debugfs_exit(struct dwc2_hsotg *); void dwc2_debugfs_exit(struct dwc2_hsotg *);
#else #else
static inline int dwc2_debugfs_init(struct dwc2_hsotg *hsotg) static inline int dwc2_debugfs_init(struct dwc2_hsotg *hsotg)
{ return 0; } { return 0; }
......
drivers/usb/dwc2/debugfs.c
View file @ 9da51974
...@@ -137,7 +137,7 @@ static int state_show(struct seq_file *seq, void *v) ...@@ -137,7 +137,7 @@ static int state_show(struct seq_file *seq, void *v)
int idx; int idx;
seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
dwc2_readl(regs + DCFG), dwc2_readl(regs + DCFG),
dwc2_readl(regs + DCTL), dwc2_readl(regs + DCTL),
dwc2_readl(regs + DSTS)); dwc2_readl(regs + DSTS));
...@@ -338,23 +338,23 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg) ...@@ -338,23 +338,23 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
{ {
struct dentry *root; struct dentry *root;
struct dentry *file; struct dentry *file;
unsigned epidx; unsigned int epidx;
root = hsotg->debug_root; root = hsotg->debug_root;
/* create general state file */ /* create general state file */
file = debugfs_create_file("state", S_IRUGO, root, hsotg, &state_fops); file = debugfs_create_file("state", 0444, root, hsotg, &state_fops);
if (IS_ERR(file)) if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create state\n", __func__); dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
file = debugfs_create_file("testmode", S_IRUGO | S_IWUSR, root, hsotg, file = debugfs_create_file("testmode", 0644, root, hsotg,
&testmode_fops); &testmode_fops);
if (IS_ERR(file)) if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create testmode\n", dev_err(hsotg->dev, "%s: failed to create testmode\n",
__func__); __func__);
file = debugfs_create_file("fifo", S_IRUGO, root, hsotg, &fifo_fops); file = debugfs_create_file("fifo", 0444, root, hsotg, &fifo_fops);
if (IS_ERR(file)) if (IS_ERR(file))
dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
...@@ -364,8 +364,8 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg) ...@@ -364,8 +364,8 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
ep = hsotg->eps_out[epidx]; ep = hsotg->eps_out[epidx];
if (ep) { if (ep) {
file = debugfs_create_file(ep->name, S_IRUGO, file = debugfs_create_file(ep->name, 0444,
root, ep, &ep_fops); root, ep, &ep_fops);
if (IS_ERR(file)) if (IS_ERR(file))
dev_err(hsotg->dev, "failed to create %s debug file\n", dev_err(hsotg->dev, "failed to create %s debug file\n",
ep->name); ep->name);
...@@ -377,8 +377,8 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg) ...@@ -377,8 +377,8 @@ static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg)
ep = hsotg->eps_in[epidx]; ep = hsotg->eps_in[epidx];
if (ep) { if (ep) {
file = debugfs_create_file(ep->name, S_IRUGO, file = debugfs_create_file(ep->name, 0444,
root, ep, &ep_fops); root, ep, &ep_fops);
if (IS_ERR(file)) if (IS_ERR(file))
dev_err(hsotg->dev, "failed to create %s debug file\n", dev_err(hsotg->dev, "failed to create %s debug file\n",
ep->name); ep->name);
...@@ -750,8 +750,8 @@ int dwc2_debugfs_init(struct dwc2_hsotg *hsotg) ...@@ -750,8 +750,8 @@ int dwc2_debugfs_init(struct dwc2_hsotg *hsotg)
hsotg->regset->nregs = ARRAY_SIZE(dwc2_regs); hsotg->regset->nregs = ARRAY_SIZE(dwc2_regs);
hsotg->regset->base = hsotg->regs; hsotg->regset->base = hsotg->regs;
file = debugfs_create_regset32("regdump", S_IRUGO, hsotg->debug_root, file = debugfs_create_regset32("regdump", 0444, hsotg->debug_root,
hsotg->regset); hsotg->regset);
if (!file) { if (!file) {
ret = -ENOMEM; ret = -ENOMEM;
goto err1; goto err1;
......
drivers/usb/dwc2/gadget.c
View file @ 9da51974
...@@ -171,7 +171,7 @@ static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) ...@@ -171,7 +171,7 @@ static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
* request. * request.
*/ */
static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
unsigned int ep, unsigned int dir_in, unsigned int ep, unsigned int dir_in,
unsigned int en) unsigned int en)
{ {
unsigned long flags; unsigned long flags;
...@@ -277,7 +277,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) ...@@ -277,7 +277,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
* Allocate a new USB request structure appropriate for the specified endpoint * Allocate a new USB request structure appropriate for the specified endpoint
*/ */
static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
gfp_t flags) gfp_t flags)
{ {
struct dwc2_hsotg_req *req; struct dwc2_hsotg_req *req;
...@@ -312,10 +312,11 @@ static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) ...@@ -312,10 +312,11 @@ static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
* of a request to ensure the buffer is ready for access by the caller. * of a request to ensure the buffer is ready for access by the caller.
*/ */
static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_ep *hs_ep,
struct dwc2_hsotg_req *hs_req) struct dwc2_hsotg_req *hs_req)
{ {
struct usb_request *req = &hs_req->req; struct usb_request *req = &hs_req->req;
usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
} }
...@@ -384,7 +385,7 @@ static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) ...@@ -384,7 +385,7 @@ static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
* This routine is only needed for PIO * This routine is only needed for PIO
*/ */
static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_ep *hs_ep,
struct dwc2_hsotg_req *hs_req) struct dwc2_hsotg_req *hs_req)
{ {
bool periodic = is_ep_periodic(hs_ep); bool periodic = is_ep_periodic(hs_ep);
...@@ -466,7 +467,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -466,7 +467,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
__func__, gnptxsts, can_write, to_write, max_transfer); __func__, gnptxsts, can_write, to_write, max_transfer);
/* /*
* limit to 512 bytes of data, it seems at least on the non-periodic * limit to 512 bytes of data, it seems at least on the non-periodic
...@@ -487,7 +488,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -487,7 +488,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
/* it's needed only when we do not use dedicated fifos */ /* it's needed only when we do not use dedicated fifos */
if (!hsotg->dedicated_fifos) if (!hsotg->dedicated_fifos)
dwc2_hsotg_en_gsint(hsotg, dwc2_hsotg_en_gsint(hsotg,
periodic ? GINTSTS_PTXFEMP : periodic ? GINTSTS_PTXFEMP :
GINTSTS_NPTXFEMP); GINTSTS_NPTXFEMP);
} }
...@@ -516,12 +517,12 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -516,12 +517,12 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
/* it's needed only when we do not use dedicated fifos */ /* it's needed only when we do not use dedicated fifos */
if (!hsotg->dedicated_fifos) if (!hsotg->dedicated_fifos)
dwc2_hsotg_en_gsint(hsotg, dwc2_hsotg_en_gsint(hsotg,
periodic ? GINTSTS_PTXFEMP : periodic ? GINTSTS_PTXFEMP :
GINTSTS_NPTXFEMP); GINTSTS_NPTXFEMP);
} }
dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
to_write, hs_req->req.length, can_write, buf_pos); to_write, hs_req->req.length, can_write, buf_pos);
if (to_write <= 0) if (to_write <= 0)
return -ENOSPC; return -ENOSPC;
...@@ -547,17 +548,17 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, ...@@ -547,17 +548,17 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
* Return the maximum data that can be queued in one go on a given endpoint * Return the maximum data that can be queued in one go on a given endpoint
* so that transfers that are too long can be split. * so that transfers that are too long can be split.
*/ */
static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
{ {
int index = hs_ep->index; int index = hs_ep->index;
unsigned maxsize; unsigned int maxsize;
unsigned maxpkt; unsigned int maxpkt;
if (index != 0) { if (index != 0) {
maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
} else { } else {
maxsize = 64+64; maxsize = 64 + 64;
if (hs_ep->dir_in) if (hs_ep->dir_in)
maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
else else
...@@ -874,7 +875,7 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) ...@@ -874,7 +875,7 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
* appropriately, and writing any data to the FIFOs. * appropriately, and writing any data to the FIFOs.
*/ */
static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_ep *hs_ep,
struct dwc2_hsotg_req *hs_req, struct dwc2_hsotg_req *hs_req,
bool continuing) bool continuing)
{ {
...@@ -885,9 +886,9 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -885,9 +886,9 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
u32 epsize_reg; u32 epsize_reg;
u32 epsize; u32 epsize;
u32 ctrl; u32 ctrl;
unsigned length; unsigned int length;
unsigned packets; unsigned int packets;
unsigned maxreq; unsigned int maxreq;
unsigned int dma_reg; unsigned int dma_reg;
if (index != 0) { if (index != 0) {
...@@ -966,7 +967,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -966,7 +967,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
if (dir_in && ureq->zero && !continuing) { if (dir_in && ureq->zero && !continuing) {
/* Test if zlp is actually required. */ /* Test if zlp is actually required. */
if ((ureq->length >= hs_ep->ep.maxpacket) && if ((ureq->length >= hs_ep->ep.maxpacket) &&
!(ureq->length % hs_ep->ep.maxpacket)) !(ureq->length % hs_ep->ep.maxpacket))
hs_ep->send_zlp = 1; hs_ep->send_zlp = 1;
} }
...@@ -1070,7 +1071,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -1070,7 +1071,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
/* check ep is enabled */ /* check ep is enabled */
if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
index, dwc2_readl(hsotg->regs + epctrl_reg)); index, dwc2_readl(hsotg->regs + epctrl_reg));
dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
...@@ -1093,7 +1094,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ...@@ -1093,7 +1094,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
* cleanup on completion. * cleanup on completion.
*/ */
static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_ep *hs_ep,
struct usb_request *req) struct usb_request *req)
{ {
int ret; int ret;
...@@ -1112,7 +1113,7 @@ static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, ...@@ -1112,7 +1113,7 @@ static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
} }
static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
{ {
void *req_buf = hs_req->req.buf; void *req_buf = hs_req->req.buf;
...@@ -1123,7 +1124,7 @@ static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, ...@@ -1123,7 +1124,7 @@ static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
WARN_ON(hs_req->saved_req_buf); WARN_ON(hs_req->saved_req_buf);
dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
hs_ep->ep.name, req_buf, hs_req->req.length); hs_ep->ep.name, req_buf, hs_req->req.length);
hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
if (!hs_req->req.buf) { if (!hs_req->req.buf) {
...@@ -1143,7 +1144,7 @@ static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, ...@@ -1143,7 +1144,7 @@ static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
} }
static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
{ {
/* If dma is not being used or buffer was aligned */ /* If dma is not being used or buffer was aligned */
if (!using_dma(hsotg) || !hs_req->saved_req_buf) if (!using_dma(hsotg) || !hs_req->saved_req_buf)
...@@ -1155,7 +1156,7 @@ static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, ...@@ -1155,7 +1156,7 @@ static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
/* Copy data from bounce buffer on successful out transfer */ /* Copy data from bounce buffer on successful out transfer */
if (!hs_ep->dir_in && !hs_req->req.status) if (!hs_ep->dir_in && !hs_req->req.status)
memcpy(hs_req->saved_req_buf, hs_req->req.buf, memcpy(hs_req->saved_req_buf, hs_req->req.buf,
hs_req->req.actual); hs_req->req.actual);
/* Free bounce buffer */ /* Free bounce buffer */
kfree(hs_req->req.buf); kfree(hs_req->req.buf);
...@@ -1224,7 +1225,7 @@ static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, ...@@ -1224,7 +1225,7 @@ static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
} }
static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
gfp_t gfp_flags) gfp_t gfp_flags)
{ {
struct dwc2_hsotg_req *hs_req = our_req(req); struct dwc2_hsotg_req *hs_req = our_req(req);
struct dwc2_hsotg_ep *hs_ep = our_ep(ep); struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
...@@ -1239,7 +1240,7 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, ...@@ -1239,7 +1240,7 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
/* Prevent new request submission when controller is suspended */ /* Prevent new request submission when controller is suspended */
if (hs->lx_state == DWC2_L2) { if (hs->lx_state == DWC2_L2) {
dev_dbg(hs->dev, "%s: don't submit request while suspended\n", dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
__func__); __func__);
return -EAGAIN; return -EAGAIN;
} }
...@@ -1300,7 +1301,7 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, ...@@ -1300,7 +1301,7 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
} }
static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
gfp_t gfp_flags) gfp_t gfp_flags)
{ {
struct dwc2_hsotg_ep *hs_ep = our_ep(ep); struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
struct dwc2_hsotg *hs = hs_ep->parent; struct dwc2_hsotg *hs = hs_ep->parent;
...@@ -1315,7 +1316,7 @@ static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, ...@@ -1315,7 +1316,7 @@ static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
} }
static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
struct usb_request *req) struct usb_request *req)
{ {
struct dwc2_hsotg_req *hs_req = our_req(req); struct dwc2_hsotg_req *hs_req = our_req(req);
...@@ -1331,7 +1332,7 @@ static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, ...@@ -1331,7 +1332,7 @@ static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
* submitted that need cleaning up. * submitted that need cleaning up.
*/ */
static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
struct usb_request *req) struct usb_request *req)
{ {
struct dwc2_hsotg_ep *hs_ep = our_ep(ep); struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
struct dwc2_hsotg *hsotg = hs_ep->parent; struct dwc2_hsotg *hsotg = hs_ep->parent;
...@@ -1350,7 +1351,7 @@ static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, ...@@ -1350,7 +1351,7 @@ static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
* structure, or return NULL if it is not a valid endpoint. * structure, or return NULL if it is not a valid endpoint.
*/ */
static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
u32 windex) u32 windex)
{ {
struct dwc2_hsotg_ep *ep; struct dwc2_hsotg_ep *ep;
int dir = (windex & USB_DIR_IN) ? 1 : 0; int dir = (windex & USB_DIR_IN) ? 1 : 0;
...@@ -1407,7 +1408,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) ...@@ -1407,7 +1408,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
* an internal method of sending replies to certain control requests, etc. * an internal method of sending replies to certain control requests, etc.
*/ */
static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_ep *ep,
void *buff, void *buff,
int length) int length)
{ {
...@@ -1450,7 +1451,7 @@ static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, ...@@ -1450,7 +1451,7 @@ static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
* @ctrl: USB control request * @ctrl: USB control request
*/ */
static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
struct usb_ctrlrequest *ctrl) struct usb_ctrlrequest *ctrl)
{ {
struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
struct dwc2_hsotg_ep *ep; struct dwc2_hsotg_ep *ep;
...@@ -1555,7 +1556,7 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) ...@@ -1555,7 +1556,7 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
* @ctrl: USB control request * @ctrl: USB control request
*/ */
static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
struct usb_ctrlrequest *ctrl) struct usb_ctrlrequest *ctrl)
{ {
struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
struct dwc2_hsotg_req *hs_req; struct dwc2_hsotg_req *hs_req;
...@@ -1705,7 +1706,7 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) ...@@ -1705,7 +1706,7 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
* gadget driver). * gadget driver).
*/ */
static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
struct usb_ctrlrequest *ctrl) struct usb_ctrlrequest *ctrl)
{ {
struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
int ret = 0; int ret = 0;
...@@ -1781,7 +1782,7 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, ...@@ -1781,7 +1782,7 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
* EP0 setup packets * EP0 setup packets
*/ */
static void dwc2_hsotg_complete_setup(struct usb_ep *ep, static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
struct usb_request *req) struct usb_request *req)
{ {
struct dwc2_hsotg_ep *hs_ep = our_ep(ep); struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
struct dwc2_hsotg *hsotg = hs_ep->parent; struct dwc2_hsotg *hsotg = hs_ep->parent;
...@@ -1839,7 +1840,7 @@ static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) ...@@ -1839,7 +1840,7 @@ static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
} }
static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep) struct dwc2_hsotg_ep *hs_ep)
{ {
u32 ctrl; u32 ctrl;
u8 index = hs_ep->index; u8 index = hs_ep->index;
...@@ -1885,11 +1886,10 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, ...@@ -1885,11 +1886,10 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
* Note, expects the ep to already be locked as appropriate. * Note, expects the ep to already be locked as appropriate.
*/ */
static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_ep *hs_ep,
struct dwc2_hsotg_req *hs_req, struct dwc2_hsotg_req *hs_req,
int result) int result)
{ {
if (!hs_req) { if (!hs_req) {
dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
return; return;
...@@ -2068,13 +2068,12 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) ...@@ -2068,13 +2068,12 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
int max_req; int max_req;
int read_ptr; int read_ptr;
if (!hs_req) { if (!hs_req) {
u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
int ptr; int ptr;
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
__func__, size, ep_idx, epctl); __func__, size, ep_idx, epctl);
/* dump the data from the FIFO, we've nothing we can do */ /* dump the data from the FIFO, we've nothing we can do */
...@@ -2134,7 +2133,7 @@ static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) ...@@ -2134,7 +2133,7 @@ static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
} }
static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
u32 epctl_reg) u32 epctl_reg)
{ {
u32 ctrl; u32 ctrl;
...@@ -2191,7 +2190,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) ...@@ -2191,7 +2190,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
struct dwc2_hsotg_req *hs_req = hs_ep->req; struct dwc2_hsotg_req *hs_req = hs_ep->req;
struct usb_request *req = &hs_req->req; struct usb_request *req = &hs_req->req;
unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
int result = 0; int result = 0;
if (!hs_req) { if (!hs_req) {
...@@ -2210,7 +2209,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) ...@@ -2210,7 +2209,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
if (using_dma(hsotg)) { if (using_dma(hsotg)) {
unsigned size_done; unsigned int size_done;
/* /*
* Calculate the size of the transfer by checking how much * Calculate the size of the transfer by checking how much
...@@ -2295,7 +2294,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) ...@@ -2295,7 +2294,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
size >>= GRXSTS_BYTECNT_SHIFT; size >>= GRXSTS_BYTECNT_SHIFT;
dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
__func__, grxstsr, size, epnum); __func__, grxstsr, size, epnum);
switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
case GRXSTS_PKTSTS_GLOBALOUTNAK: case GRXSTS_PKTSTS_GLOBALOUTNAK:
...@@ -2470,7 +2469,7 @@ static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) ...@@ -2470,7 +2469,7 @@ static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
* make an attempt to write data into the FIFO. * make an attempt to write data into the FIFO.
*/ */
static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep) struct dwc2_hsotg_ep *hs_ep)
{ {
struct dwc2_hsotg_req *hs_req = hs_ep->req; struct dwc2_hsotg_req *hs_req = hs_ep->req;
...@@ -2481,7 +2480,7 @@ static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, ...@@ -2481,7 +2480,7 @@ static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
*/ */
if (hs_ep->index != 0) if (hs_ep->index != 0)
dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
hs_ep->dir_in, 0); hs_ep->dir_in, 0);
return 0; return 0;
} }
...@@ -2503,7 +2502,7 @@ static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, ...@@ -2503,7 +2502,7 @@ static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
* call the relevant completion routines. * call the relevant completion routines.
*/ */
static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep) struct dwc2_hsotg_ep *hs_ep)
{ {
struct dwc2_hsotg_req *hs_req = hs_ep->req; struct dwc2_hsotg_req *hs_req = hs_ep->req;
u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
...@@ -2531,7 +2530,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, ...@@ -2531,7 +2530,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
if (ret < 0) { if (ret < 0) {
dev_dbg(hsotg->dev, "Invalid Test #%d\n", dev_dbg(hsotg->dev, "Invalid Test #%d\n",
hsotg->test_mode); hsotg->test_mode);
dwc2_hsotg_stall_ep0(hsotg); dwc2_hsotg_stall_ep0(hsotg);
return; return;
} }
...@@ -2807,7 +2806,7 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) ...@@ -2807,7 +2806,7 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
* Process and clear any interrupt pending for an individual endpoint * Process and clear any interrupt pending for an individual endpoint
*/ */
static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
int dir_in) int dir_in)
{ {
struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
...@@ -2824,7 +2823,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, ...@@ -2824,7 +2823,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
if (!hs_ep) { if (!hs_ep) {
dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
__func__, idx, dir_in ? "in" : "out"); __func__, idx, dir_in ? "in" : "out");
return; return;
} }
...@@ -3059,13 +3058,13 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg, ...@@ -3059,13 +3058,13 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
int result) int result)
{ {
struct dwc2_hsotg_req *req, *treq; struct dwc2_hsotg_req *req, *treq;
unsigned size; unsigned int size;
ep->req = NULL; ep->req = NULL;
list_for_each_entry_safe(req, treq, &ep->queue, queue) list_for_each_entry_safe(req, treq, &ep->queue, queue)
dwc2_hsotg_complete_request(hsotg, ep, req, dwc2_hsotg_complete_request(hsotg, ep, req,
result); result);
if (!hsotg->dedicated_fifos) if (!hsotg->dedicated_fifos)
return; return;
...@@ -3084,7 +3083,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg, ...@@ -3084,7 +3083,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
*/ */
void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
{ {
unsigned ep; unsigned int ep;
if (!hsotg->connected) if (!hsotg->connected)
return; return;
...@@ -3095,10 +3094,10 @@ void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) ...@@ -3095,10 +3094,10 @@ void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
for (ep = 0; ep < hsotg->num_of_eps; ep++) { for (ep = 0; ep < hsotg->num_of_eps; ep++) {
if (hsotg->eps_in[ep]) if (hsotg->eps_in[ep])
kill_all_requests(hsotg, hsotg->eps_in[ep], kill_all_requests(hsotg, hsotg->eps_in[ep],
-ESHUTDOWN); -ESHUTDOWN);
if (hsotg->eps_out[ep]) if (hsotg->eps_out[ep])
kill_all_requests(hsotg, hsotg->eps_out[ep], kill_all_requests(hsotg, hsotg->eps_out[ep],
-ESHUTDOWN); -ESHUTDOWN);
} }
call_gadget(hsotg, disconnect); call_gadget(hsotg, disconnect);
...@@ -3147,7 +3146,7 @@ static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) ...@@ -3147,7 +3146,7 @@ static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
* Issue a soft reset to the core, and await the core finishing it. * Issue a soft reset to the core, and await the core finishing it.
*/ */
void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
bool is_usb_reset) bool is_usb_reset)
{ {
u32 intmsk; u32 intmsk;
u32 val; u32 val;
...@@ -3462,7 +3461,6 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) ...@@ -3462,7 +3461,6 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
} }
if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
u32 connected = hsotg->connected; u32 connected = hsotg->connected;
...@@ -3705,7 +3703,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, ...@@ -3705,7 +3703,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
* This is called from the USB gadget code's usb_ep_enable(). * This is called from the USB gadget code's usb_ep_enable().
*/ */
static int dwc2_hsotg_ep_enable(struct usb_ep *ep, static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
const struct usb_endpoint_descriptor *desc) const struct usb_endpoint_descriptor *desc)
{ {
struct dwc2_hsotg_ep *hs_ep = our_ep(ep); struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
struct dwc2_hsotg *hsotg = hs_ep->parent; struct dwc2_hsotg *hsotg = hs_ep->parent;
...@@ -3827,12 +3825,13 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, ...@@ -3827,12 +3825,13 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
if (dir_in && hsotg->dedicated_fifos) { if (dir_in && hsotg->dedicated_fifos) {
u32 fifo_index = 0; u32 fifo_index = 0;
u32 fifo_size = UINT_MAX; u32 fifo_size = UINT_MAX;
size = hs_ep->ep.maxpacket*hs_ep->mc;
size = hs_ep->ep.maxpacket * hs_ep->mc;
for (i = 1; i < hsotg->num_of_eps; ++i) { for (i = 1; i < hsotg->num_of_eps; ++i) {
if (hsotg->fifo_map & (1<<i)) if (hsotg->fifo_map & (1 << i))
continue; continue;
val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
if (val < size) if (val < size)
continue; continue;
/* Search for smallest acceptable fifo */ /* Search for smallest acceptable fifo */
...@@ -4041,12 +4040,11 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) ...@@ -4041,12 +4040,11 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
epctl &= ~DXEPCTL_STALL; epctl &= ~DXEPCTL_STALL;
xfertype = epctl & DXEPCTL_EPTYPE_MASK; xfertype = epctl & DXEPCTL_EPTYPE_MASK;
if (xfertype == DXEPCTL_EPTYPE_BULK || if (xfertype == DXEPCTL_EPTYPE_BULK ||
xfertype == DXEPCTL_EPTYPE_INTERRUPT) xfertype == DXEPCTL_EPTYPE_INTERRUPT)
epctl |= DXEPCTL_SETD0PID; epctl |= DXEPCTL_SETD0PID;
} }
dwc2_writel(epctl, hs->regs + epreg); dwc2_writel(epctl, hs->regs + epreg);
} else { } else {
epreg = DOEPCTL(index); epreg = DOEPCTL(index);
epctl = dwc2_readl(hs->regs + epreg); epctl = dwc2_readl(hs->regs + epreg);
...@@ -4056,7 +4054,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) ...@@ -4056,7 +4054,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
epctl &= ~DXEPCTL_STALL; epctl &= ~DXEPCTL_STALL;
xfertype = epctl & DXEPCTL_EPTYPE_MASK; xfertype = epctl & DXEPCTL_EPTYPE_MASK;
if (xfertype == DXEPCTL_EPTYPE_BULK || if (xfertype == DXEPCTL_EPTYPE_BULK ||
xfertype == DXEPCTL_EPTYPE_INTERRUPT) xfertype == DXEPCTL_EPTYPE_INTERRUPT)
epctl |= DXEPCTL_SETD0PID; epctl |= DXEPCTL_SETD0PID;
} }
dwc2_writel(epctl, hs->regs + epreg); dwc2_writel(epctl, hs->regs + epreg);
...@@ -4098,7 +4096,7 @@ static struct usb_ep_ops dwc2_hsotg_ep_ops = { ...@@ -4098,7 +4096,7 @@ static struct usb_ep_ops dwc2_hsotg_ep_ops = {
}; };
/** /**
* dwc2_hsotg_init - initalize the usb core * dwc2_hsotg_init - initialize the usb core
* @hsotg: The driver state * @hsotg: The driver state
*/ */
static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
...@@ -4152,7 +4150,7 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) ...@@ -4152,7 +4150,7 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
* to work. * to work.
*/ */
static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
struct usb_gadget_driver *driver) struct usb_gadget_driver *driver)
{ {
struct dwc2_hsotg *hsotg = to_hsotg(gadget); struct dwc2_hsotg *hsotg = to_hsotg(gadget);
unsigned long flags; unsigned long flags;
...@@ -4275,7 +4273,7 @@ static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) ...@@ -4275,7 +4273,7 @@ static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
unsigned long flags = 0; unsigned long flags = 0;
dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
hsotg->op_state); hsotg->op_state);
/* Don't modify pullup state while in host mode */ /* Don't modify pullup state while in host mode */
if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
...@@ -4337,7 +4335,7 @@ static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) ...@@ -4337,7 +4335,7 @@ static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
* *
* Report how much power the device may consume to the phy. * Report how much power the device may consume to the phy.
*/ */
static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
{ {
struct dwc2_hsotg *hsotg = to_hsotg(gadget); struct dwc2_hsotg *hsotg = to_hsotg(gadget);
...@@ -4366,7 +4364,7 @@ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { ...@@ -4366,7 +4364,7 @@ static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
* direction information and other state that may be required. * direction information and other state that may be required.
*/ */
static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_ep *hs_ep,
int epnum, int epnum,
bool dir_in) bool dir_in)
{ {
...@@ -4423,6 +4421,7 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, ...@@ -4423,6 +4421,7 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
if (using_dma(hsotg)) { if (using_dma(hsotg)) {
u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
if (dir_in) if (dir_in)
dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
else else
...@@ -4529,7 +4528,6 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) ...@@ -4529,7 +4528,6 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
idx, dwc2_readl(regs + DOEPCTL(idx)), idx, dwc2_readl(regs + DOEPCTL(idx)),
dwc2_readl(regs + DOEPTSIZ(idx)), dwc2_readl(regs + DOEPTSIZ(idx)),
dwc2_readl(regs + DOEPDMA(idx))); dwc2_readl(regs + DOEPDMA(idx)));
} }
dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
...@@ -4584,7 +4582,7 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) ...@@ -4584,7 +4582,7 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
} }
ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
dev_name(hsotg->dev), hsotg); dev_name(hsotg->dev), hsotg);
if (ret < 0) { if (ret < 0) {
dev_err(dev, "cannot claim IRQ for gadget\n"); dev_err(dev, "cannot claim IRQ for gadget\n");
return ret; return ret;
...@@ -4615,10 +4613,10 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) ...@@ -4615,10 +4613,10 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
if (hsotg->eps_in[epnum]) if (hsotg->eps_in[epnum])
dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
epnum, 1); epnum, 1);
if (hsotg->eps_out[epnum]) if (hsotg->eps_out[epnum])
dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
epnum, 0); epnum, 0);
} }
ret = usb_add_gadget_udc(dev, &hsotg->gadget); ret = usb_add_gadget_udc(dev, &hsotg->gadget);
......
drivers/usb/dwc2/hcd.c
View file @ 9da51974
...@@ -2577,7 +2577,7 @@ static void dwc2_free_dma_aligned_buffer(struct urb *urb) ...@@ -2577,7 +2577,7 @@ static void dwc2_free_dma_aligned_buffer(struct urb *urb)
return; return;
temp = container_of(urb->transfer_buffer, temp = container_of(urb->transfer_buffer,
struct dma_aligned_buffer, data); struct dma_aligned_buffer, data);
if (usb_urb_dir_in(urb)) if (usb_urb_dir_in(urb))
memcpy(temp->old_xfer_buffer, temp->data, memcpy(temp->old_xfer_buffer, temp->data,
...@@ -2621,7 +2621,7 @@ static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) ...@@ -2621,7 +2621,7 @@ static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
} }
static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
gfp_t mem_flags) gfp_t mem_flags)
{ {
int ret; int ret;
...@@ -2718,7 +2718,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) ...@@ -2718,7 +2718,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
chan->multi_count = 1; chan->multi_count = 1;
if (urb->actual_length > urb->length && if (urb->actual_length > urb->length &&
!dwc2_hcd_is_pipe_in(&urb->pipe_info)) !dwc2_hcd_is_pipe_in(&urb->pipe_info))
urb->actual_length = urb->length; urb->actual_length = urb->length;
if (hsotg->params.host_dma > 0) if (hsotg->params.host_dma > 0)
...@@ -2989,7 +2989,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) ...@@ -2989,7 +2989,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
* the middle of multiple high-bandwidth packets getting queued. * the middle of multiple high-bandwidth packets getting queued.
*/ */
if (hsotg->params.host_dma <= 0 && if (hsotg->params.host_dma <= 0 &&
qh->channel->multi_count > 1) qh->channel->multi_count > 1)
hsotg->queuing_high_bandwidth = 1; hsotg->queuing_high_bandwidth = 1;
fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
...@@ -4047,7 +4047,7 @@ static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) ...@@ -4047,7 +4047,7 @@ static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
{ {
struct wrapper_priv_data *p; struct wrapper_priv_data *p;
p = (struct wrapper_priv_data *) &hcd->hcd_priv; p = (struct wrapper_priv_data *)&hcd->hcd_priv;
return p->hsotg; return p->hsotg;
} }
...@@ -4082,7 +4082,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, ...@@ -4082,7 +4082,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
*ttport = urb->dev->ttport; *ttport = urb->dev->ttport;
dwc_tt = urb->dev->tt->hcpriv; dwc_tt = urb->dev->tt->hcpriv;
if (dwc_tt == NULL) { if (!dwc_tt) {
size_t bitmap_size; size_t bitmap_size;
/* /*
...@@ -4096,7 +4096,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, ...@@ -4096,7 +4096,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
mem_flags); mem_flags);
if (dwc_tt == NULL) if (!dwc_tt)
return NULL; return NULL;
dwc_tt->usb_tt = urb->dev->tt; dwc_tt->usb_tt = urb->dev->tt;
...@@ -4123,7 +4123,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, ...@@ -4123,7 +4123,7 @@ struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
{ {
/* Model kfree and make put of NULL a no-op */ /* Model kfree and make put of NULL a no-op */
if (dwc_tt == NULL) if (!dwc_tt)
return; return;
WARN_ON(dwc_tt->refcount < 1); WARN_ON(dwc_tt->refcount < 1);
...@@ -4206,7 +4206,6 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, ...@@ -4206,7 +4206,6 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
usb_pipein(urb->pipe) ? "IN" : "OUT", status, usb_pipein(urb->pipe) ? "IN" : "OUT", status,
urb->actual_length); urb->actual_length);
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
for (i = 0; i < urb->number_of_packets; ++i) { for (i = 0; i < urb->number_of_packets; ++i) {
...@@ -4237,7 +4236,7 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, ...@@ -4237,7 +4236,7 @@ void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
if (ep) if (ep)
dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
dwc2_hcd_get_ep_bandwidth(hsotg, ep), dwc2_hcd_get_ep_bandwidth(hsotg, ep),
urb); urb);
} }
...@@ -4584,7 +4583,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, ...@@ -4584,7 +4583,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
} }
if (ep == NULL) if (!ep)
return -EINVAL; return -EINVAL;
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
...@@ -4654,7 +4653,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, ...@@ -4654,7 +4653,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
urb->iso_frame_desc[i].length); urb->iso_frame_desc[i].length);
urb->hcpriv = dwc2_urb; urb->hcpriv = dwc2_urb;
qh = (struct dwc2_qh *) ep->hcpriv; qh = (struct dwc2_qh *)ep->hcpriv;
/* Create QH for the endpoint if it doesn't exist */ /* Create QH for the endpoint if it doesn't exist */
if (!qh) { if (!qh) {
qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
...@@ -4683,7 +4682,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, ...@@ -4683,7 +4682,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
if (alloc_bandwidth) { if (alloc_bandwidth) {
dwc2_allocate_bus_bandwidth(hcd, dwc2_allocate_bus_bandwidth(hcd,
dwc2_hcd_get_ep_bandwidth(hsotg, ep), dwc2_hcd_get_ep_bandwidth(hsotg, ep),
urb); urb);
} }
...@@ -4709,7 +4708,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, ...@@ -4709,7 +4708,7 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
dwc2_hcd_qh_unlink(hsotg, qh); dwc2_hcd_qh_unlink(hsotg, qh);
/* Free each QTD in the QH's QTD list */ /* Free each QTD in the QH's QTD list */
list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
qtd_list_entry) qtd_list_entry)
dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
dwc2_hcd_qh_free(hsotg, qh); dwc2_hcd_qh_free(hsotg, qh);
} }
...@@ -4908,7 +4907,7 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) ...@@ -4908,7 +4907,7 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
for (i = 0; i < MAX_EPS_CHANNELS; i++) { for (i = 0; i < MAX_EPS_CHANNELS; i++) {
struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
if (chan != NULL) { if (chan) {
dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
i, chan); i, chan);
hsotg->hc_ptr_array[i] = NULL; hsotg->hc_ptr_array[i] = NULL;
...@@ -4997,7 +4996,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) ...@@ -4997,7 +4996,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
/* Check if the bus driver or platform code has setup a dma_mask */ /* Check if the bus driver or platform code has setup a dma_mask */
if (hsotg->params.host_dma > 0 && if (hsotg->params.host_dma > 0 &&
hsotg->dev->dma_mask == NULL) { !hsotg->dev->dma_mask) {
dev_warn(hsotg->dev, dev_warn(hsotg->dev,
"dma_mask not set, disabling DMA\n"); "dma_mask not set, disabling DMA\n");
hsotg->params.host_dma = false; hsotg->params.host_dma = false;
...@@ -5021,7 +5020,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) ...@@ -5021,7 +5020,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
hcd->has_tt = 1; hcd->has_tt = 1;
((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
hsotg->priv = hcd; hsotg->priv = hcd;
/* /*
...@@ -5069,7 +5068,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) ...@@ -5069,7 +5068,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
for (i = 0; i < num_channels; i++) { for (i = 0; i < num_channels; i++) {
channel = kzalloc(sizeof(*channel), GFP_KERNEL); channel = kzalloc(sizeof(*channel), GFP_KERNEL);
if (channel == NULL) if (!channel)
goto error3; goto error3;
channel->hc_num = i; channel->hc_num = i;
INIT_LIST_HEAD(&channel->split_order_list_entry); INIT_LIST_HEAD(&channel->split_order_list_entry);
......
drivers/usb/dwc2/hcd.h
View file @ 9da51974
...@@ -521,29 +521,29 @@ static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) ...@@ -521,29 +521,29 @@ static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
return !dwc2_hcd_is_pipe_in(pipe); return !dwc2_hcd_is_pipe_in(pipe);
} }
extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq); int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq);
extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
/* Transaction Execution Functions */ /* Transaction Execution Functions */
extern enum dwc2_transaction_type dwc2_hcd_select_transactions( enum dwc2_transaction_type dwc2_hcd_select_transactions(
struct dwc2_hsotg *hsotg); struct dwc2_hsotg *hsotg);
extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
enum dwc2_transaction_type tr_type); enum dwc2_transaction_type tr_type);
/* Schedule Queue Functions */ /* Schedule Queue Functions */
/* Implemented in hcd_queue.c */ /* Implemented in hcd_queue.c */
extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
struct dwc2_hcd_urb *urb, struct dwc2_hcd_urb *urb,
gfp_t mem_flags); gfp_t mem_flags);
extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
int sched_csplit); int sched_csplit);
extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
struct dwc2_qh *qh); struct dwc2_qh *qh);
/* Unlinks and frees a QTD */ /* Unlinks and frees a QTD */
static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
...@@ -556,15 +556,15 @@ static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, ...@@ -556,15 +556,15 @@ static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
} }
/* Descriptor DMA support functions */ /* Descriptor DMA support functions */
extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
struct dwc2_qh *qh); struct dwc2_qh *qh);
extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
struct dwc2_host_chan *chan, int chnum, struct dwc2_host_chan *chan, int chnum,
enum dwc2_halt_status halt_status); enum dwc2_halt_status halt_status);
extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
gfp_t mem_flags); gfp_t mem_flags);
extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
/* Check if QH is non-periodic */ /* Check if QH is non-periodic */
#define dwc2_qh_is_non_per(_qh_ptr_) \ #define dwc2_qh_is_non_per(_qh_ptr_) \
...@@ -732,8 +732,8 @@ static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, ...@@ -732,8 +732,8 @@ static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
return qh->host_us; return qh->host_us;
} }
extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
struct dwc2_host_chan *chan, int chnum, struct dwc2_host_chan *chan, int chnum,
struct dwc2_qtd *qtd); struct dwc2_qtd *qtd);
/* HCD Core API */ /* HCD Core API */
...@@ -746,14 +746,14 @@ extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, ...@@ -746,14 +746,14 @@ extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
* Returns IRQ_HANDLED if interrupt is handled * Returns IRQ_HANDLED if interrupt is handled
* Return IRQ_NONE if interrupt is not handled * Return IRQ_NONE if interrupt is not handled
*/ */
extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
/** /**
* dwc2_hcd_stop() - Halts the DWC_otg host mode operation * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
* *
* @hsotg: The DWC2 HCD * @hsotg: The DWC2 HCD
*/ */
extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
/** /**
* dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
...@@ -761,7 +761,7 @@ extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); ...@@ -761,7 +761,7 @@ extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
* *
* @hsotg: The DWC2 HCD * @hsotg: The DWC2 HCD
*/ */
extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
/** /**
* dwc2_hcd_dump_state() - Dumps hsotg state * dwc2_hcd_dump_state() - Dumps hsotg state
...@@ -771,7 +771,7 @@ extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); ...@@ -771,7 +771,7 @@ extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
* NOTE: This function will be removed once the peripheral controller code * NOTE: This function will be removed once the peripheral controller code
* is integrated and the driver is stable * is integrated and the driver is stable
*/ */
extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
/** /**
* dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
...@@ -784,7 +784,7 @@ extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); ...@@ -784,7 +784,7 @@ extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
* NOTE: This function will be removed once the peripheral controller code * NOTE: This function will be removed once the peripheral controller code
* is integrated and the driver is stable * is integrated and the driver is stable
*/ */
extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
/* URB interface */ /* URB interface */
...@@ -793,15 +793,15 @@ extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); ...@@ -793,15 +793,15 @@ extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
#define URB_SEND_ZERO_PACKET 0x2 #define URB_SEND_ZERO_PACKET 0x2
/* Host driver callbacks */ /* Host driver callbacks */
extern struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
void *context, gfp_t mem_flags, void *context, gfp_t mem_flags,
int *ttport); int *ttport);
extern void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
struct dwc2_tt *dwc_tt); struct dwc2_tt *dwc_tt);
extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
int status); int status);
#ifdef DEBUG #ifdef DEBUG
/* /*
......
drivers/usb/dwc2/hcd_ddma.c
View file @ 9da51974
...@@ -106,7 +106,7 @@ static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, ...@@ -106,7 +106,7 @@ static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
qh->desc_list_sz, qh->desc_list_sz,
DMA_TO_DEVICE); DMA_TO_DEVICE);
qh->n_bytes = kzalloc(sizeof(u32) * dwc2_max_desc_num(qh), flags); qh->n_bytes = kcalloc(dwc2_max_desc_num(qh), sizeof(u32), flags);
if (!qh->n_bytes) { if (!qh->n_bytes) {
dma_unmap_single(hsotg->dev, qh->desc_list_dma, dma_unmap_single(hsotg->dev, qh->desc_list_dma,
qh->desc_list_sz, qh->desc_list_sz,
...@@ -175,7 +175,6 @@ static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg) ...@@ -175,7 +175,6 @@ static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
hsotg->frame_list = NULL; hsotg->frame_list = NULL;
spin_unlock_irqrestore(&hsotg->lock, flags); spin_unlock_irqrestore(&hsotg->lock, flags);
} }
static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en) static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
...@@ -570,7 +569,7 @@ static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg, ...@@ -570,7 +569,7 @@ static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
#endif #endif
dma_sync_single_for_device(hsotg->dev, dma_sync_single_for_device(hsotg->dev,
qh->desc_list_dma + qh->desc_list_dma +
(idx * sizeof(struct dwc2_dma_desc)), (idx * sizeof(struct dwc2_dma_desc)),
sizeof(struct dwc2_dma_desc), sizeof(struct dwc2_dma_desc),
DMA_TO_DEVICE); DMA_TO_DEVICE);
...@@ -776,7 +775,7 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg, ...@@ -776,7 +775,7 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
n_desc - 1, n_desc - 1,
&qh->desc_list[n_desc - 1]); &qh->desc_list[n_desc - 1]);
dma_sync_single_for_device(hsotg->dev, dma_sync_single_for_device(hsotg->dev,
qh->desc_list_dma + qh->desc_list_dma +
((n_desc - 1) * ((n_desc - 1) *
sizeof(struct dwc2_dma_desc)), sizeof(struct dwc2_dma_desc)),
sizeof(struct dwc2_dma_desc), sizeof(struct dwc2_dma_desc),
...@@ -816,7 +815,7 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg, ...@@ -816,7 +815,7 @@ static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n", dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n",
&qh->desc_list[0]); &qh->desc_list[0]);
dma_sync_single_for_device(hsotg->dev, dma_sync_single_for_device(hsotg->dev,
qh->desc_list_dma, qh->desc_list_dma,
sizeof(struct dwc2_dma_desc), sizeof(struct dwc2_dma_desc),
DMA_TO_DEVICE); DMA_TO_DEVICE);
} }
...@@ -1064,7 +1063,7 @@ static void dwc2_complete_isoc_xfer_ddma(struct dwc2_hsotg *hsotg, ...@@ -1064,7 +1063,7 @@ static void dwc2_complete_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
} }
static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg, static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg,
struct dwc2_host_chan *chan, struct dwc2_host_chan *chan,
struct dwc2_qtd *qtd, struct dwc2_qtd *qtd,
struct dwc2_dma_desc *dma_desc, struct dwc2_dma_desc *dma_desc,
enum dwc2_halt_status halt_status, enum dwc2_halt_status halt_status,
......
drivers/usb/dwc2/hcd_intr.c
View file @ 9da51974
...@@ -60,7 +60,7 @@ static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) ...@@ -60,7 +60,7 @@ static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
if (expected != curr_frame_number) if (expected != curr_frame_number)
dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n", dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
expected, curr_frame_number); expected, curr_frame_number);
#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
...@@ -163,7 +163,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) ...@@ -163,7 +163,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
* (micro)frame * (micro)frame
*/ */
list_move_tail(&qh->qh_list_entry, list_move_tail(&qh->qh_list_entry,
&hsotg->periodic_sched_ready); &hsotg->periodic_sched_ready);
} }
} }
tr_type = dwc2_hcd_select_transactions(hsotg); tr_type = dwc2_hcd_select_transactions(hsotg);
...@@ -442,7 +442,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, ...@@ -442,7 +442,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
count = (hctsiz & TSIZ_XFERSIZE_MASK) >> count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
TSIZ_XFERSIZE_SHIFT; TSIZ_XFERSIZE_SHIFT;
length = chan->xfer_len - count; length = chan->xfer_len - count;
if (short_read != NULL) if (short_read)
*short_read = (count != 0); *short_read = (count != 0);
} else if (chan->qh->do_split) { } else if (chan->qh->do_split) {
length = qtd->ssplit_out_xfer_count; length = qtd->ssplit_out_xfer_count;
...@@ -823,7 +823,7 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, ...@@ -823,7 +823,7 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
* processed. * processed.
*/ */
list_move_tail(&chan->qh->qh_list_entry, list_move_tail(&chan->qh->qh_list_entry,
&hsotg->periodic_sched_assigned); &hsotg->periodic_sched_assigned);
/* /*
* Make sure the Periodic Tx FIFO Empty interrupt is * Make sure the Periodic Tx FIFO Empty interrupt is
...@@ -1078,7 +1078,7 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, ...@@ -1078,7 +1078,7 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL) if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
halt_status = dwc2_update_isoc_urb_state(hsotg, chan, halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
chnum, qtd, DWC2_HC_XFER_COMPLETE); chnum, qtd, DWC2_HC_XFER_COMPLETE);
dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
halt_status); halt_status);
break; break;
...@@ -1369,7 +1369,7 @@ static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, ...@@ -1369,7 +1369,7 @@ static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
DWC2_HC_XFER_URB_COMPLETE); DWC2_HC_XFER_URB_COMPLETE);
} else { } else {
dwc2_release_channel(hsotg, chan, qtd, dwc2_release_channel(hsotg, chan, qtd,
DWC2_HC_XFER_NO_HALT_STATUS); DWC2_HC_XFER_NO_HALT_STATUS);
} }
goto handle_nyet_done; goto handle_nyet_done;
} }
...@@ -1485,7 +1485,7 @@ static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, ...@@ -1485,7 +1485,7 @@ static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
enum dwc2_halt_status halt_status; enum dwc2_halt_status halt_status;
halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
qtd, DWC2_HC_XFER_BABBLE_ERR); qtd, DWC2_HC_XFER_BABBLE_ERR);
dwc2_halt_channel(hsotg, chan, qtd, halt_status); dwc2_halt_channel(hsotg, chan, qtd, halt_status);
} }
...@@ -1620,7 +1620,6 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, ...@@ -1620,7 +1620,6 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
case USB_ENDPOINT_XFER_BULK: case USB_ENDPOINT_XFER_BULK:
qtd->error_count++; qtd->error_count++;
if (!chan->qh->ping_state) { if (!chan->qh->ping_state) {
dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
qtd, DWC2_HC_XFER_XACT_ERR); qtd, DWC2_HC_XFER_XACT_ERR);
dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
...@@ -1645,7 +1644,7 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, ...@@ -1645,7 +1644,7 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
enum dwc2_halt_status halt_status; enum dwc2_halt_status halt_status;
halt_status = dwc2_update_isoc_urb_state(hsotg, chan, halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
chnum, qtd, DWC2_HC_XFER_XACT_ERR); chnum, qtd, DWC2_HC_XFER_XACT_ERR);
dwc2_halt_channel(hsotg, chan, qtd, halt_status); dwc2_halt_channel(hsotg, chan, qtd, halt_status);
} }
break; break;
...@@ -1680,7 +1679,7 @@ static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, ...@@ -1680,7 +1679,7 @@ static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
break; break;
case USB_ENDPOINT_XFER_ISOC: case USB_ENDPOINT_XFER_ISOC:
halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
qtd, DWC2_HC_XFER_FRAME_OVERRUN); qtd, DWC2_HC_XFER_FRAME_OVERRUN);
dwc2_halt_channel(hsotg, chan, qtd, halt_status); dwc2_halt_channel(hsotg, chan, qtd, halt_status);
break; break;
} }
...@@ -1906,7 +1905,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, ...@@ -1906,7 +1905,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
"%s: Halt channel %d (assume incomplete periodic transfer)\n", "%s: Halt channel %d (assume incomplete periodic transfer)\n",
__func__, chnum); __func__, chnum);
dwc2_halt_channel(hsotg, chan, qtd, dwc2_halt_channel(hsotg, chan, qtd,
DWC2_HC_XFER_PERIODIC_INCOMPLETE); DWC2_HC_XFER_PERIODIC_INCOMPLETE);
} else { } else {
dev_err(hsotg->dev, dev_err(hsotg->dev,
"%s: Channel %d - ChHltd set, but reason is unknown\n", "%s: Channel %d - ChHltd set, but reason is unknown\n",
...@@ -1970,7 +1969,7 @@ static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh) ...@@ -1970,7 +1969,7 @@ static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
{ {
struct dwc2_qtd *cur_head; struct dwc2_qtd *cur_head;
if (qh == NULL) if (!qh)
return false; return false;
cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd, cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
......
drivers/usb/dwc2/hcd_queue.c
View file @ 9da51974
...@@ -82,8 +82,8 @@ static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) ...@@ -82,8 +82,8 @@ static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
status = 0; status = 0;
} else { } else {
dev_dbg(hsotg->dev, dev_dbg(hsotg->dev,
"%s: Total channels: %d, Periodic: %d, " "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
"Non-periodic: %d\n", __func__, num_channels, __func__, num_channels,
hsotg->periodic_channels, hsotg->non_periodic_channels); hsotg->periodic_channels, hsotg->non_periodic_channels);
status = -ENOSPC; status = -ENOSPC;
} }
...@@ -485,7 +485,6 @@ static void pmap_print(unsigned long *map, int bits_per_period, ...@@ -485,7 +485,6 @@ static void pmap_print(unsigned long *map, int bits_per_period,
} }
} }
struct dwc2_qh_print_data { struct dwc2_qh_print_data {
struct dwc2_hsotg *hsotg; struct dwc2_hsotg *hsotg;
struct dwc2_qh *qh; struct dwc2_qh *qh;
...@@ -587,7 +586,7 @@ static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, ...@@ -587,7 +586,7 @@ static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
unsigned long *map = dwc2_get_ls_map(hsotg, qh); unsigned long *map = dwc2_get_ls_map(hsotg, qh);
int slice; int slice;
if (map == NULL) if (!map)
return -EINVAL; return -EINVAL;
/* /*
...@@ -626,7 +625,7 @@ static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg, ...@@ -626,7 +625,7 @@ static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
unsigned long *map = dwc2_get_ls_map(hsotg, qh); unsigned long *map = dwc2_get_ls_map(hsotg, qh);
/* Schedule should have failed, so no worries about no error code */ /* Schedule should have failed, so no worries about no error code */
if (map == NULL) if (!map)
return; return;
pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
...@@ -1182,7 +1181,7 @@ static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) ...@@ -1182,7 +1181,7 @@ static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
qh->start_active_frame = next_active_frame; qh->start_active_frame = next_active_frame;
dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n", dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
qh, frame_number, qh->next_active_frame); qh, frame_number, qh->next_active_frame);
} }
/** /**
...@@ -1501,7 +1500,6 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, ...@@ -1501,7 +1500,6 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
device_ns += dwc_tt->usb_tt->think_time; device_ns += dwc_tt->usb_tt->think_time;
qh->device_us = NS_TO_US(device_ns); qh->device_us = NS_TO_US(device_ns);
qh->device_interval = urb->interval; qh->device_interval = urb->interval;
qh->host_interval = urb->interval * (do_split ? 8 : 1); qh->host_interval = urb->interval * (do_split ? 8 : 1);
...@@ -1587,7 +1585,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, ...@@ -1587,7 +1585,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
* Return: Pointer to the newly allocated QH, or NULL on error * Return: Pointer to the newly allocated QH, or NULL on error
*/ */
struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
struct dwc2_hcd_urb *urb, struct dwc2_hcd_urb *urb,
gfp_t mem_flags) gfp_t mem_flags)
{ {
struct dwc2_qh *qh; struct dwc2_qh *qh;
...@@ -1741,7 +1739,7 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) ...@@ -1741,7 +1739,7 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
* Return: number missed by (or 0 if we didn't miss). * Return: number missed by (or 0 if we didn't miss).
*/ */
static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg, static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
struct dwc2_qh *qh, u16 frame_number) struct dwc2_qh *qh, u16 frame_number)
{ {
u16 old_frame = qh->next_active_frame; u16 old_frame = qh->next_active_frame;
u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
...@@ -1804,7 +1802,7 @@ static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg, ...@@ -1804,7 +1802,7 @@ static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
* Return: number missed by (or 0 if we didn't miss). * Return: number missed by (or 0 if we didn't miss).
*/ */
static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg, static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
struct dwc2_qh *qh, u16 frame_number) struct dwc2_qh *qh, u16 frame_number)
{ {
int missed = 0; int missed = 0;
u16 interval = qh->host_interval; u16 interval = qh->host_interval;
...@@ -1926,7 +1924,7 @@ void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, ...@@ -1926,7 +1924,7 @@ void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
missed = dwc2_next_periodic_start(hsotg, qh, frame_number); missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
dwc2_sch_vdbg(hsotg, dwc2_sch_vdbg(hsotg,
"QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n", "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
qh, sched_next_periodic_split, frame_number, old_frame, qh, sched_next_periodic_split, frame_number, old_frame,
qh->next_active_frame, qh->next_active_frame,
dwc2_frame_num_dec(qh->next_active_frame, old_frame), dwc2_frame_num_dec(qh->next_active_frame, old_frame),
......
drivers/usb/dwc2/hw.h
View file @ 9da51974
...@@ -40,37 +40,37 @@ ...@@ -40,37 +40,37 @@
#define HSOTG_REG(x) (x) #define HSOTG_REG(x) (x)
#define GOTGCTL HSOTG_REG(0x000) #define GOTGCTL HSOTG_REG(0x000)
#define GOTGCTL_CHIRPEN (1 << 27) #define GOTGCTL_CHIRPEN BIT(27)
#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
#define GOTGCTL_MULT_VALID_BC_SHIFT 22 #define GOTGCTL_MULT_VALID_BC_SHIFT 22
#define GOTGCTL_OTGVER (1 << 20) #define GOTGCTL_OTGVER BIT(20)
#define GOTGCTL_BSESVLD (1 << 19) #define GOTGCTL_BSESVLD BIT(19)
#define GOTGCTL_ASESVLD (1 << 18) #define GOTGCTL_ASESVLD BIT(18)
#define GOTGCTL_DBNC_SHORT (1 << 17) #define GOTGCTL_DBNC_SHORT BIT(17)
#define GOTGCTL_CONID_B (1 << 16) #define GOTGCTL_CONID_B BIT(16)
#define GOTGCTL_DBNCE_FLTR_BYPASS (1 << 15) #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
#define GOTGCTL_DEVHNPEN (1 << 11) #define GOTGCTL_DEVHNPEN BIT(11)
#define GOTGCTL_HSTSETHNPEN (1 << 10) #define GOTGCTL_HSTSETHNPEN BIT(10)
#define GOTGCTL_HNPREQ (1 << 9) #define GOTGCTL_HNPREQ BIT(9)
#define GOTGCTL_HSTNEGSCS (1 << 8) #define GOTGCTL_HSTNEGSCS BIT(8)
#define GOTGCTL_SESREQ (1 << 1) #define GOTGCTL_SESREQ BIT(1)
#define GOTGCTL_SESREQSCS (1 << 0) #define GOTGCTL_SESREQSCS BIT(0)
#define GOTGINT HSOTG_REG(0x004) #define GOTGINT HSOTG_REG(0x004)
#define GOTGINT_DBNCE_DONE (1 << 19) #define GOTGINT_DBNCE_DONE BIT(19)
#define GOTGINT_A_DEV_TOUT_CHG (1 << 18) #define GOTGINT_A_DEV_TOUT_CHG BIT(18)
#define GOTGINT_HST_NEG_DET (1 << 17) #define GOTGINT_HST_NEG_DET BIT(17)
#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9) #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8) #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
#define GOTGINT_SES_END_DET (1 << 2) #define GOTGINT_SES_END_DET BIT(2)
#define GAHBCFG HSOTG_REG(0x008) #define GAHBCFG HSOTG_REG(0x008)
#define GAHBCFG_AHB_SINGLE (1 << 23) #define GAHBCFG_AHB_SINGLE BIT(23)
#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22) #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
#define GAHBCFG_REM_MEM_SUPP (1 << 21) #define GAHBCFG_REM_MEM_SUPP BIT(21)
#define GAHBCFG_P_TXF_EMP_LVL (1 << 8) #define GAHBCFG_P_TXF_EMP_LVL BIT(8)
#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) #define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
#define GAHBCFG_DMA_EN (1 << 5) #define GAHBCFG_DMA_EN BIT(5)
#define GAHBCFG_HBSTLEN_MASK (0xf << 1) #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
#define GAHBCFG_HBSTLEN_SHIFT 1 #define GAHBCFG_HBSTLEN_SHIFT 1
#define GAHBCFG_HBSTLEN_SINGLE 0 #define GAHBCFG_HBSTLEN_SINGLE 0
...@@ -78,38 +78,38 @@ ...@@ -78,38 +78,38 @@
#define GAHBCFG_HBSTLEN_INCR4 3 #define GAHBCFG_HBSTLEN_INCR4 3
#define GAHBCFG_HBSTLEN_INCR8 5 #define GAHBCFG_HBSTLEN_INCR8 5
#define GAHBCFG_HBSTLEN_INCR16 7 #define GAHBCFG_HBSTLEN_INCR16 7
#define GAHBCFG_GLBL_INTR_EN (1 << 0) #define GAHBCFG_GLBL_INTR_EN BIT(0)
#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
GAHBCFG_NP_TXF_EMP_LVL | \ GAHBCFG_NP_TXF_EMP_LVL | \
GAHBCFG_DMA_EN | \ GAHBCFG_DMA_EN | \
GAHBCFG_GLBL_INTR_EN) GAHBCFG_GLBL_INTR_EN)
#define GUSBCFG HSOTG_REG(0x00C) #define GUSBCFG HSOTG_REG(0x00C)
#define GUSBCFG_FORCEDEVMODE (1 << 30) #define GUSBCFG_FORCEDEVMODE BIT(30)
#define GUSBCFG_FORCEHOSTMODE (1 << 29) #define GUSBCFG_FORCEHOSTMODE BIT(29)
#define GUSBCFG_TXENDDELAY (1 << 28) #define GUSBCFG_TXENDDELAY BIT(28)
#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27) #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
#define GUSBCFG_ICUSBCAP (1 << 26) #define GUSBCFG_ICUSBCAP BIT(26)
#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25) #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24) #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23) #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
#define GUSBCFG_TERMSELDLPULSE (1 << 22) #define GUSBCFG_TERMSELDLPULSE BIT(22)
#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21) #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19) #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
#define GUSBCFG_ULPI_AUTO_RES (1 << 18) #define GUSBCFG_ULPI_AUTO_RES BIT(18)
#define GUSBCFG_ULPI_FS_LS (1 << 17) #define GUSBCFG_ULPI_FS_LS BIT(17)
#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16) #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15) #define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
#define GUSBCFG_USBTRDTIM_SHIFT 10 #define GUSBCFG_USBTRDTIM_SHIFT 10
#define GUSBCFG_HNPCAP (1 << 9) #define GUSBCFG_HNPCAP BIT(9)
#define GUSBCFG_SRPCAP (1 << 8) #define GUSBCFG_SRPCAP BIT(8)
#define GUSBCFG_DDRSEL (1 << 7) #define GUSBCFG_DDRSEL BIT(7)
#define GUSBCFG_PHYSEL (1 << 6) #define GUSBCFG_PHYSEL BIT(6)
#define GUSBCFG_FSINTF (1 << 5) #define GUSBCFG_FSINTF BIT(5)
#define GUSBCFG_ULPI_UTMI_SEL (1 << 4) #define GUSBCFG_ULPI_UTMI_SEL BIT(4)
#define GUSBCFG_PHYIF16 (1 << 3) #define GUSBCFG_PHYIF16 BIT(3)
#define GUSBCFG_PHYIF8 (0 << 3) #define GUSBCFG_PHYIF8 (0 << 3)
#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
#define GUSBCFG_TOUTCAL_SHIFT 0 #define GUSBCFG_TOUTCAL_SHIFT 0
...@@ -117,54 +117,54 @@ ...@@ -117,54 +117,54 @@
#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) #define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
#define GRSTCTL HSOTG_REG(0x010) #define GRSTCTL HSOTG_REG(0x010)
#define GRSTCTL_AHBIDLE (1 << 31) #define GRSTCTL_AHBIDLE BIT(31)
#define GRSTCTL_DMAREQ (1 << 30) #define GRSTCTL_DMAREQ BIT(30)
#define GRSTCTL_TXFNUM_MASK (0x1f << 6) #define GRSTCTL_TXFNUM_MASK (0x1f << 6)
#define GRSTCTL_TXFNUM_SHIFT 6 #define GRSTCTL_TXFNUM_SHIFT 6
#define GRSTCTL_TXFNUM_LIMIT 0x1f #define GRSTCTL_TXFNUM_LIMIT 0x1f
#define GRSTCTL_TXFNUM(_x) ((_x) << 6) #define GRSTCTL_TXFNUM(_x) ((_x) << 6)
#define GRSTCTL_TXFFLSH (1 << 5) #define GRSTCTL_TXFFLSH BIT(5)
#define GRSTCTL_RXFFLSH (1 << 4) #define GRSTCTL_RXFFLSH BIT(4)
#define GRSTCTL_IN_TKNQ_FLSH (1 << 3) #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
#define GRSTCTL_FRMCNTRRST (1 << 2) #define GRSTCTL_FRMCNTRRST BIT(2)
#define GRSTCTL_HSFTRST (1 << 1) #define GRSTCTL_HSFTRST BIT(1)
#define GRSTCTL_CSFTRST (1 << 0) #define GRSTCTL_CSFTRST BIT(0)
#define GINTSTS HSOTG_REG(0x014) #define GINTSTS HSOTG_REG(0x014)
#define GINTMSK HSOTG_REG(0x018) #define GINTMSK HSOTG_REG(0x018)
#define GINTSTS_WKUPINT (1 << 31) #define GINTSTS_WKUPINT BIT(31)
#define GINTSTS_SESSREQINT (1 << 30) #define GINTSTS_SESSREQINT BIT(30)
#define GINTSTS_DISCONNINT (1 << 29) #define GINTSTS_DISCONNINT BIT(29)
#define GINTSTS_CONIDSTSCHNG (1 << 28) #define GINTSTS_CONIDSTSCHNG BIT(28)
#define GINTSTS_LPMTRANRCVD (1 << 27) #define GINTSTS_LPMTRANRCVD BIT(27)
#define GINTSTS_PTXFEMP (1 << 26) #define GINTSTS_PTXFEMP BIT(26)
#define GINTSTS_HCHINT (1 << 25) #define GINTSTS_HCHINT BIT(25)
#define GINTSTS_PRTINT (1 << 24) #define GINTSTS_PRTINT BIT(24)
#define GINTSTS_RESETDET (1 << 23) #define GINTSTS_RESETDET BIT(23)
#define GINTSTS_FET_SUSP (1 << 22) #define GINTSTS_FET_SUSP BIT(22)
#define GINTSTS_INCOMPL_IP (1 << 21) #define GINTSTS_INCOMPL_IP BIT(21)
#define GINTSTS_INCOMPL_SOOUT (1 << 21) #define GINTSTS_INCOMPL_SOOUT BIT(21)
#define GINTSTS_INCOMPL_SOIN (1 << 20) #define GINTSTS_INCOMPL_SOIN BIT(20)
#define GINTSTS_OEPINT (1 << 19) #define GINTSTS_OEPINT BIT(19)
#define GINTSTS_IEPINT (1 << 18) #define GINTSTS_IEPINT BIT(18)
#define GINTSTS_EPMIS (1 << 17) #define GINTSTS_EPMIS BIT(17)
#define GINTSTS_RESTOREDONE (1 << 16) #define GINTSTS_RESTOREDONE BIT(16)
#define GINTSTS_EOPF (1 << 15) #define GINTSTS_EOPF BIT(15)
#define GINTSTS_ISOUTDROP (1 << 14) #define GINTSTS_ISOUTDROP BIT(14)
#define GINTSTS_ENUMDONE (1 << 13) #define GINTSTS_ENUMDONE BIT(13)
#define GINTSTS_USBRST (1 << 12) #define GINTSTS_USBRST BIT(12)
#define GINTSTS_USBSUSP (1 << 11) #define GINTSTS_USBSUSP BIT(11)
#define GINTSTS_ERLYSUSP (1 << 10) #define GINTSTS_ERLYSUSP BIT(10)
#define GINTSTS_I2CINT (1 << 9) #define GINTSTS_I2CINT BIT(9)
#define GINTSTS_ULPI_CK_INT (1 << 8) #define GINTSTS_ULPI_CK_INT BIT(8)
#define GINTSTS_GOUTNAKEFF (1 << 7) #define GINTSTS_GOUTNAKEFF BIT(7)
#define GINTSTS_GINNAKEFF (1 << 6) #define GINTSTS_GINNAKEFF BIT(6)
#define GINTSTS_NPTXFEMP (1 << 5) #define GINTSTS_NPTXFEMP BIT(5)
#define GINTSTS_RXFLVL (1 << 4) #define GINTSTS_RXFLVL BIT(4)
#define GINTSTS_SOF (1 << 3) #define GINTSTS_SOF BIT(3)
#define GINTSTS_OTGINT (1 << 2) #define GINTSTS_OTGINT BIT(2)
#define GINTSTS_MODEMIS (1 << 1) #define GINTSTS_MODEMIS BIT(1)
#define GINTSTS_CURMODE_HOST (1 << 0) #define GINTSTS_CURMODE_HOST BIT(0)
#define GRXSTSR HSOTG_REG(0x01C) #define GRXSTSR HSOTG_REG(0x01C)
#define GRXSTSP HSOTG_REG(0x020) #define GRXSTSP HSOTG_REG(0x020)
...@@ -208,14 +208,14 @@ ...@@ -208,14 +208,14 @@
#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
#define GI2CCTL HSOTG_REG(0x0030) #define GI2CCTL HSOTG_REG(0x0030)
#define GI2CCTL_BSYDNE (1 << 31) #define GI2CCTL_BSYDNE BIT(31)
#define GI2CCTL_RW (1 << 30) #define GI2CCTL_RW BIT(30)
#define GI2CCTL_I2CDATSE0 (1 << 28) #define GI2CCTL_I2CDATSE0 BIT(28)
#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
#define GI2CCTL_I2CDEVADDR_SHIFT 26 #define GI2CCTL_I2CDEVADDR_SHIFT 26
#define GI2CCTL_I2CSUSPCTL (1 << 25) #define GI2CCTL_I2CSUSPCTL BIT(25)
#define GI2CCTL_ACK (1 << 24) #define GI2CCTL_ACK BIT(24)
#define GI2CCTL_I2CEN (1 << 23) #define GI2CCTL_I2CEN BIT(23)
#define GI2CCTL_ADDR_MASK (0x7f << 16) #define GI2CCTL_ADDR_MASK (0x7f << 16)
#define GI2CCTL_ADDR_SHIFT 16 #define GI2CCTL_ADDR_SHIFT 16
#define GI2CCTL_REGADDR_MASK (0xff << 8) #define GI2CCTL_REGADDR_MASK (0xff << 8)
...@@ -230,16 +230,16 @@ ...@@ -230,16 +230,16 @@
#define GHWCFG1 HSOTG_REG(0x0044) #define GHWCFG1 HSOTG_REG(0x0044)
#define GHWCFG2 HSOTG_REG(0x0048) #define GHWCFG2 HSOTG_REG(0x0048)
#define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31) #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
#define GHWCFG2_MULTI_PROC_INT (1 << 20) #define GHWCFG2_MULTI_PROC_INT BIT(20)
#define GHWCFG2_DYNAMIC_FIFO (1 << 19) #define GHWCFG2_DYNAMIC_FIFO BIT(19)
#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18) #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
...@@ -256,7 +256,7 @@ ...@@ -256,7 +256,7 @@
#define GHWCFG2_HS_PHY_TYPE_UTMI 1 #define GHWCFG2_HS_PHY_TYPE_UTMI 1
#define GHWCFG2_HS_PHY_TYPE_ULPI 2 #define GHWCFG2_HS_PHY_TYPE_ULPI 2
#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
#define GHWCFG2_POINT2POINT (1 << 5) #define GHWCFG2_POINT2POINT BIT(5)
#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
#define GHWCFG2_ARCHITECTURE_SHIFT 3 #define GHWCFG2_ARCHITECTURE_SHIFT 3
#define GHWCFG2_SLAVE_ONLY_ARCH 0 #define GHWCFG2_SLAVE_ONLY_ARCH 0
...@@ -276,32 +276,32 @@ ...@@ -276,32 +276,32 @@
#define GHWCFG3 HSOTG_REG(0x004c) #define GHWCFG3 HSOTG_REG(0x004c)
#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 #define GHWCFG3_DFIFO_DEPTH_SHIFT 16
#define GHWCFG3_OTG_LPM_EN (1 << 15) #define GHWCFG3_OTG_LPM_EN BIT(15)
#define GHWCFG3_BC_SUPPORT (1 << 14) #define GHWCFG3_BC_SUPPORT BIT(14)
#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13) #define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
#define GHWCFG3_ADP_SUPP (1 << 12) #define GHWCFG3_ADP_SUPP BIT(12)
#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11) #define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
#define GHWCFG3_OPTIONAL_FEATURES (1 << 10) #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
#define GHWCFG3_VENDOR_CTRL_IF (1 << 9) #define GHWCFG3_VENDOR_CTRL_IF BIT(9)
#define GHWCFG3_I2C (1 << 8) #define GHWCFG3_I2C BIT(8)
#define GHWCFG3_OTG_FUNC (1 << 7) #define GHWCFG3_OTG_FUNC BIT(7)
#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
#define GHWCFG4 HSOTG_REG(0x0050) #define GHWCFG4 HSOTG_REG(0x0050)
#define GHWCFG4_DESC_DMA_DYN (1 << 31) #define GHWCFG4_DESC_DMA_DYN BIT(31)
#define GHWCFG4_DESC_DMA (1 << 30) #define GHWCFG4_DESC_DMA BIT(30)
#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
#define GHWCFG4_NUM_IN_EPS_SHIFT 26 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
#define GHWCFG4_DED_FIFO_EN (1 << 25) #define GHWCFG4_DED_FIFO_EN BIT(25)
#define GHWCFG4_DED_FIFO_SHIFT 25 #define GHWCFG4_DED_FIFO_SHIFT 25
#define GHWCFG4_SESSION_END_FILT_EN (1 << 24) #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
#define GHWCFG4_B_VALID_FILT_EN (1 << 23) #define GHWCFG4_B_VALID_FILT_EN BIT(23)
#define GHWCFG4_A_VALID_FILT_EN (1 << 22) #define GHWCFG4_A_VALID_FILT_EN BIT(22)
#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21) #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
#define GHWCFG4_IDDIG_FILT_EN (1 << 20) #define GHWCFG4_IDDIG_FILT_EN BIT(20)
#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
...@@ -309,64 +309,64 @@ ...@@ -309,64 +309,64 @@
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
#define GHWCFG4_XHIBER (1 << 7) #define GHWCFG4_XHIBER BIT(7)
#define GHWCFG4_HIBER (1 << 6) #define GHWCFG4_HIBER BIT(6)
#define GHWCFG4_MIN_AHB_FREQ (1 << 5) #define GHWCFG4_MIN_AHB_FREQ BIT(5)
#define GHWCFG4_POWER_OPTIMIZ (1 << 4) #define GHWCFG4_POWER_OPTIMIZ BIT(4)
#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
#define GLPMCFG HSOTG_REG(0x0054) #define GLPMCFG HSOTG_REG(0x0054)
#define GLPMCFG_INV_SEL_HSIC (1 << 31) #define GLPMCFG_INV_SEL_HSIC BIT(31)
#define GLPMCFG_HSIC_CONNECT (1 << 30) #define GLPMCFG_HSIC_CONNECT BIT(30)
#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25) #define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25)
#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25 #define GLPMCFG_RETRY_COUNT_STS_SHIFT 25
#define GLPMCFG_SEND_LPM (1 << 24) #define GLPMCFG_SEND_LPM BIT(24)
#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21) #define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21)
#define GLPMCFG_RETRY_COUNT_SHIFT 21 #define GLPMCFG_RETRY_COUNT_SHIFT 21
#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17) #define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17)
#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17 #define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17
#define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16) #define GLPMCFG_SLEEP_STATE_RESUMEOK BIT(16)
#define GLPMCFG_PRT_SLEEP_STS (1 << 15) #define GLPMCFG_PRT_SLEEP_STS BIT(15)
#define GLPMCFG_LPM_RESP_MASK (0x3 << 13) #define GLPMCFG_LPM_RESP_MASK (0x3 << 13)
#define GLPMCFG_LPM_RESP_SHIFT 13 #define GLPMCFG_LPM_RESP_SHIFT 13
#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
#define GLPMCFG_HIRD_THRES_SHIFT 8 #define GLPMCFG_HIRD_THRES_SHIFT 8
#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) #define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
#define GLPMCFG_EN_UTMI_SLEEP (1 << 7) #define GLPMCFG_EN_UTMI_SLEEP BIT(7)
#define GLPMCFG_REM_WKUP_EN (1 << 6) #define GLPMCFG_REM_WKUP_EN BIT(6)
#define GLPMCFG_HIRD_MASK (0xf << 2) #define GLPMCFG_HIRD_MASK (0xf << 2)
#define GLPMCFG_HIRD_SHIFT 2 #define GLPMCFG_HIRD_SHIFT 2
#define GLPMCFG_APPL_RESP (1 << 1) #define GLPMCFG_APPL_RESP BIT(1)
#define GLPMCFG_LPM_CAP_EN (1 << 0) #define GLPMCFG_LPM_CAP_EN BIT(0)
#define GPWRDN HSOTG_REG(0x0058) #define GPWRDN HSOTG_REG(0x0058)
#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
#define GPWRDN_ADP_INT (1 << 23) #define GPWRDN_ADP_INT BIT(23)
#define GPWRDN_BSESSVLD (1 << 22) #define GPWRDN_BSESSVLD BIT(22)
#define GPWRDN_IDSTS (1 << 21) #define GPWRDN_IDSTS BIT(21)
#define GPWRDN_LINESTATE_MASK (0x3 << 19) #define GPWRDN_LINESTATE_MASK (0x3 << 19)
#define GPWRDN_LINESTATE_SHIFT 19 #define GPWRDN_LINESTATE_SHIFT 19
#define GPWRDN_STS_CHGINT_MSK (1 << 18) #define GPWRDN_STS_CHGINT_MSK BIT(18)
#define GPWRDN_STS_CHGINT (1 << 17) #define GPWRDN_STS_CHGINT BIT(17)
#define GPWRDN_SRP_DET_MSK (1 << 16) #define GPWRDN_SRP_DET_MSK BIT(16)
#define GPWRDN_SRP_DET (1 << 15) #define GPWRDN_SRP_DET BIT(15)
#define GPWRDN_CONNECT_DET_MSK (1 << 14) #define GPWRDN_CONNECT_DET_MSK BIT(14)
#define GPWRDN_CONNECT_DET (1 << 13) #define GPWRDN_CONNECT_DET BIT(13)
#define GPWRDN_DISCONN_DET_MSK (1 << 12) #define GPWRDN_DISCONN_DET_MSK BIT(12)
#define GPWRDN_DISCONN_DET (1 << 11) #define GPWRDN_DISCONN_DET BIT(11)
#define GPWRDN_RST_DET_MSK (1 << 10) #define GPWRDN_RST_DET_MSK BIT(10)
#define GPWRDN_RST_DET (1 << 9) #define GPWRDN_RST_DET BIT(9)
#define GPWRDN_LNSTSCHG_MSK (1 << 8) #define GPWRDN_LNSTSCHG_MSK BIT(8)
#define GPWRDN_LNSTSCHG (1 << 7) #define GPWRDN_LNSTSCHG BIT(7)
#define GPWRDN_DIS_VBUS (1 << 6) #define GPWRDN_DIS_VBUS BIT(6)
#define GPWRDN_PWRDNSWTCH (1 << 5) #define GPWRDN_PWRDNSWTCH BIT(5)
#define GPWRDN_PWRDNRSTN (1 << 4) #define GPWRDN_PWRDNRSTN BIT(4)
#define GPWRDN_PWRDNCLMP (1 << 3) #define GPWRDN_PWRDNCLMP BIT(3)
#define GPWRDN_RESTORE (1 << 2) #define GPWRDN_RESTORE BIT(2)
#define GPWRDN_PMUACTV (1 << 1) #define GPWRDN_PMUACTV BIT(1)
#define GPWRDN_PMUINTSEL (1 << 0) #define GPWRDN_PMUINTSEL BIT(0)
#define GDFIFOCFG HSOTG_REG(0x005c) #define GDFIFOCFG HSOTG_REG(0x005c)
#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
...@@ -377,16 +377,16 @@ ...@@ -377,16 +377,16 @@
#define ADPCTL HSOTG_REG(0x0060) #define ADPCTL HSOTG_REG(0x0060)
#define ADPCTL_AR_MASK (0x3 << 27) #define ADPCTL_AR_MASK (0x3 << 27)
#define ADPCTL_AR_SHIFT 27 #define ADPCTL_AR_SHIFT 27
#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26) #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
#define ADPCTL_ADP_SNS_INT_MSK (1 << 25) #define ADPCTL_ADP_SNS_INT_MSK BIT(25)
#define ADPCTL_ADP_PRB_INT_MSK (1 << 24) #define ADPCTL_ADP_PRB_INT_MSK BIT(24)
#define ADPCTL_ADP_TMOUT_INT (1 << 23) #define ADPCTL_ADP_TMOUT_INT BIT(23)
#define ADPCTL_ADP_SNS_INT (1 << 22) #define ADPCTL_ADP_SNS_INT BIT(22)
#define ADPCTL_ADP_PRB_INT (1 << 21) #define ADPCTL_ADP_PRB_INT BIT(21)
#define ADPCTL_ADPENA (1 << 20) #define ADPCTL_ADPENA BIT(20)
#define ADPCTL_ADPRES (1 << 19) #define ADPCTL_ADPRES BIT(19)
#define ADPCTL_ENASNS (1 << 18) #define ADPCTL_ENASNS BIT(18)
#define ADPCTL_ENAPRB (1 << 17) #define ADPCTL_ENAPRB BIT(17)
#define ADPCTL_RTIM_MASK (0x7ff << 6) #define ADPCTL_RTIM_MASK (0x7ff << 6)
#define ADPCTL_RTIM_SHIFT 6 #define ADPCTL_RTIM_SHIFT 6
#define ADPCTL_PRB_PER_MASK (0x3 << 4) #define ADPCTL_PRB_PER_MASK (0x3 << 4)
...@@ -412,7 +412,7 @@ ...@@ -412,7 +412,7 @@
/* Device mode registers */ /* Device mode registers */
#define DCFG HSOTG_REG(0x800) #define DCFG HSOTG_REG(0x800)
#define DCFG_DESCDMA_EN (1 << 23) #define DCFG_DESCDMA_EN BIT(23)
#define DCFG_EPMISCNT_MASK (0x1f << 18) #define DCFG_EPMISCNT_MASK (0x1f << 18)
#define DCFG_EPMISCNT_SHIFT 18 #define DCFG_EPMISCNT_SHIFT 18
#define DCFG_EPMISCNT_LIMIT 0x1f #define DCFG_EPMISCNT_LIMIT 0x1f
...@@ -425,7 +425,7 @@ ...@@ -425,7 +425,7 @@
#define DCFG_DEVADDR_SHIFT 4 #define DCFG_DEVADDR_SHIFT 4
#define DCFG_DEVADDR_LIMIT 0x7f #define DCFG_DEVADDR_LIMIT 0x7f
#define DCFG_DEVADDR(_x) ((_x) << 4) #define DCFG_DEVADDR(_x) ((_x) << 4)
#define DCFG_NZ_STS_OUT_HSHK (1 << 2) #define DCFG_NZ_STS_OUT_HSHK BIT(2)
#define DCFG_DEVSPD_MASK (0x3 << 0) #define DCFG_DEVSPD_MASK (0x3 << 0)
#define DCFG_DEVSPD_SHIFT 0 #define DCFG_DEVSPD_SHIFT 0
#define DCFG_DEVSPD_HS 0 #define DCFG_DEVSPD_HS 0
...@@ -434,54 +434,54 @@ ...@@ -434,54 +434,54 @@
#define DCFG_DEVSPD_FS48 3 #define DCFG_DEVSPD_FS48 3
#define DCTL HSOTG_REG(0x804) #define DCTL HSOTG_REG(0x804)
#define DCTL_PWRONPRGDONE (1 << 11) #define DCTL_PWRONPRGDONE BIT(11)
#define DCTL_CGOUTNAK (1 << 10) #define DCTL_CGOUTNAK BIT(10)
#define DCTL_SGOUTNAK (1 << 9) #define DCTL_SGOUTNAK BIT(9)
#define DCTL_CGNPINNAK (1 << 8) #define DCTL_CGNPINNAK BIT(8)
#define DCTL_SGNPINNAK (1 << 7) #define DCTL_SGNPINNAK BIT(7)
#define DCTL_TSTCTL_MASK (0x7 << 4) #define DCTL_TSTCTL_MASK (0x7 << 4)
#define DCTL_TSTCTL_SHIFT 4 #define DCTL_TSTCTL_SHIFT 4
#define DCTL_GOUTNAKSTS (1 << 3) #define DCTL_GOUTNAKSTS BIT(3)
#define DCTL_GNPINNAKSTS (1 << 2) #define DCTL_GNPINNAKSTS BIT(2)
#define DCTL_SFTDISCON (1 << 1) #define DCTL_SFTDISCON BIT(1)
#define DCTL_RMTWKUPSIG (1 << 0) #define DCTL_RMTWKUPSIG BIT(0)
#define DSTS HSOTG_REG(0x808) #define DSTS HSOTG_REG(0x808)
#define DSTS_SOFFN_MASK (0x3fff << 8) #define DSTS_SOFFN_MASK (0x3fff << 8)
#define DSTS_SOFFN_SHIFT 8 #define DSTS_SOFFN_SHIFT 8
#define DSTS_SOFFN_LIMIT 0x3fff #define DSTS_SOFFN_LIMIT 0x3fff
#define DSTS_SOFFN(_x) ((_x) << 8) #define DSTS_SOFFN(_x) ((_x) << 8)
#define DSTS_ERRATICERR (1 << 3) #define DSTS_ERRATICERR BIT(3)
#define DSTS_ENUMSPD_MASK (0x3 << 1) #define DSTS_ENUMSPD_MASK (0x3 << 1)
#define DSTS_ENUMSPD_SHIFT 1 #define DSTS_ENUMSPD_SHIFT 1
#define DSTS_ENUMSPD_HS 0 #define DSTS_ENUMSPD_HS 0
#define DSTS_ENUMSPD_FS 1 #define DSTS_ENUMSPD_FS 1
#define DSTS_ENUMSPD_LS 2 #define DSTS_ENUMSPD_LS 2
#define DSTS_ENUMSPD_FS48 3 #define DSTS_ENUMSPD_FS48 3
#define DSTS_SUSPSTS (1 << 0) #define DSTS_SUSPSTS BIT(0)
#define DIEPMSK HSOTG_REG(0x810) #define DIEPMSK HSOTG_REG(0x810)
#define DIEPMSK_NAKMSK (1 << 13) #define DIEPMSK_NAKMSK BIT(13)
#define DIEPMSK_BNAININTRMSK (1 << 9) #define DIEPMSK_BNAININTRMSK BIT(9)
#define DIEPMSK_TXFIFOUNDRNMSK (1 << 8) #define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
#define DIEPMSK_TXFIFOEMPTY (1 << 7) #define DIEPMSK_TXFIFOEMPTY BIT(7)
#define DIEPMSK_INEPNAKEFFMSK (1 << 6) #define DIEPMSK_INEPNAKEFFMSK BIT(6)
#define DIEPMSK_INTKNEPMISMSK (1 << 5) #define DIEPMSK_INTKNEPMISMSK BIT(5)
#define DIEPMSK_INTKNTXFEMPMSK (1 << 4) #define DIEPMSK_INTKNTXFEMPMSK BIT(4)
#define DIEPMSK_TIMEOUTMSK (1 << 3) #define DIEPMSK_TIMEOUTMSK BIT(3)
#define DIEPMSK_AHBERRMSK (1 << 2) #define DIEPMSK_AHBERRMSK BIT(2)
#define DIEPMSK_EPDISBLDMSK (1 << 1) #define DIEPMSK_EPDISBLDMSK BIT(1)
#define DIEPMSK_XFERCOMPLMSK (1 << 0) #define DIEPMSK_XFERCOMPLMSK BIT(0)
#define DOEPMSK HSOTG_REG(0x814) #define DOEPMSK HSOTG_REG(0x814)
#define DOEPMSK_BNAMSK (1 << 9) #define DOEPMSK_BNAMSK BIT(9)
#define DOEPMSK_BACK2BACKSETUP (1 << 6) #define DOEPMSK_BACK2BACKSETUP BIT(6)
#define DOEPMSK_STSPHSERCVDMSK (1 << 5) #define DOEPMSK_STSPHSERCVDMSK BIT(5)
#define DOEPMSK_OUTTKNEPDISMSK (1 << 4) #define DOEPMSK_OUTTKNEPDISMSK BIT(4)
#define DOEPMSK_SETUPMSK (1 << 3) #define DOEPMSK_SETUPMSK BIT(3)
#define DOEPMSK_AHBERRMSK (1 << 2) #define DOEPMSK_AHBERRMSK BIT(2)
#define DOEPMSK_EPDISBLDMSK (1 << 1) #define DOEPMSK_EPDISBLDMSK BIT(1)
#define DOEPMSK_XFERCOMPLMSK (1 << 0) #define DOEPMSK_XFERCOMPLMSK BIT(0)
#define DAINT HSOTG_REG(0x818) #define DAINT HSOTG_REG(0x818)
#define DAINTMSK HSOTG_REG(0x81C) #define DAINTMSK HSOTG_REG(0x81C)
...@@ -516,30 +516,30 @@ ...@@ -516,30 +516,30 @@
#define D0EPCTL_MPS_16 2 #define D0EPCTL_MPS_16 2
#define D0EPCTL_MPS_8 3 #define D0EPCTL_MPS_8 3
#define DXEPCTL_EPENA (1 << 31) #define DXEPCTL_EPENA BIT(31)
#define DXEPCTL_EPDIS (1 << 30) #define DXEPCTL_EPDIS BIT(30)
#define DXEPCTL_SETD1PID (1 << 29) #define DXEPCTL_SETD1PID BIT(29)
#define DXEPCTL_SETODDFR (1 << 29) #define DXEPCTL_SETODDFR BIT(29)
#define DXEPCTL_SETD0PID (1 << 28) #define DXEPCTL_SETD0PID BIT(28)
#define DXEPCTL_SETEVENFR (1 << 28) #define DXEPCTL_SETEVENFR BIT(28)
#define DXEPCTL_SNAK (1 << 27) #define DXEPCTL_SNAK BIT(27)
#define DXEPCTL_CNAK (1 << 26) #define DXEPCTL_CNAK BIT(26)
#define DXEPCTL_TXFNUM_MASK (0xf << 22) #define DXEPCTL_TXFNUM_MASK (0xf << 22)
#define DXEPCTL_TXFNUM_SHIFT 22 #define DXEPCTL_TXFNUM_SHIFT 22
#define DXEPCTL_TXFNUM_LIMIT 0xf #define DXEPCTL_TXFNUM_LIMIT 0xf
#define DXEPCTL_TXFNUM(_x) ((_x) << 22) #define DXEPCTL_TXFNUM(_x) ((_x) << 22)
#define DXEPCTL_STALL (1 << 21) #define DXEPCTL_STALL BIT(21)
#define DXEPCTL_SNP (1 << 20) #define DXEPCTL_SNP BIT(20)
#define DXEPCTL_EPTYPE_MASK (0x3 << 18) #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
#define DXEPCTL_EPTYPE_ISO (0x1 << 18) #define DXEPCTL_EPTYPE_ISO (0x1 << 18)
#define DXEPCTL_EPTYPE_BULK (0x2 << 18) #define DXEPCTL_EPTYPE_BULK (0x2 << 18)
#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
#define DXEPCTL_NAKSTS (1 << 17) #define DXEPCTL_NAKSTS BIT(17)
#define DXEPCTL_DPID (1 << 16) #define DXEPCTL_DPID BIT(16)
#define DXEPCTL_EOFRNUM (1 << 16) #define DXEPCTL_EOFRNUM BIT(16)
#define DXEPCTL_USBACTEP (1 << 15) #define DXEPCTL_USBACTEP BIT(15)
#define DXEPCTL_NEXTEP_MASK (0xf << 11) #define DXEPCTL_NEXTEP_MASK (0xf << 11)
#define DXEPCTL_NEXTEP_SHIFT 11 #define DXEPCTL_NEXTEP_SHIFT 11
#define DXEPCTL_NEXTEP_LIMIT 0xf #define DXEPCTL_NEXTEP_LIMIT 0xf
...@@ -551,26 +551,26 @@ ...@@ -551,26 +551,26 @@
#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
#define DXEPINT_SETUP_RCVD (1 << 15) #define DXEPINT_SETUP_RCVD BIT(15)
#define DXEPINT_NYETINTRPT (1 << 14) #define DXEPINT_NYETINTRPT BIT(14)
#define DXEPINT_NAKINTRPT (1 << 13) #define DXEPINT_NAKINTRPT BIT(13)
#define DXEPINT_BBLEERRINTRPT (1 << 12) #define DXEPINT_BBLEERRINTRPT BIT(12)
#define DXEPINT_PKTDRPSTS (1 << 11) #define DXEPINT_PKTDRPSTS BIT(11)
#define DXEPINT_BNAINTR (1 << 9) #define DXEPINT_BNAINTR BIT(9)
#define DXEPINT_TXFIFOUNDRN (1 << 8) #define DXEPINT_TXFIFOUNDRN BIT(8)
#define DXEPINT_OUTPKTERR (1 << 8) #define DXEPINT_OUTPKTERR BIT(8)
#define DXEPINT_TXFEMP (1 << 7) #define DXEPINT_TXFEMP BIT(7)
#define DXEPINT_INEPNAKEFF (1 << 6) #define DXEPINT_INEPNAKEFF BIT(6)
#define DXEPINT_BACK2BACKSETUP (1 << 6) #define DXEPINT_BACK2BACKSETUP BIT(6)
#define DXEPINT_INTKNEPMIS (1 << 5) #define DXEPINT_INTKNEPMIS BIT(5)
#define DXEPINT_STSPHSERCVD (1 << 5) #define DXEPINT_STSPHSERCVD BIT(5)
#define DXEPINT_INTKNTXFEMP (1 << 4) #define DXEPINT_INTKNTXFEMP BIT(4)
#define DXEPINT_OUTTKNEPDIS (1 << 4) #define DXEPINT_OUTTKNEPDIS BIT(4)
#define DXEPINT_TIMEOUT (1 << 3) #define DXEPINT_TIMEOUT BIT(3)
#define DXEPINT_SETUP (1 << 3) #define DXEPINT_SETUP BIT(3)
#define DXEPINT_AHBERR (1 << 2) #define DXEPINT_AHBERR BIT(2)
#define DXEPINT_EPDISBLD (1 << 1) #define DXEPINT_EPDISBLD BIT(1)
#define DXEPINT_XFERCOMPL (1 << 0) #define DXEPINT_XFERCOMPL BIT(0)
#define DIEPTSIZ0 HSOTG_REG(0x910) #define DIEPTSIZ0 HSOTG_REG(0x910)
#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
...@@ -587,7 +587,7 @@ ...@@ -587,7 +587,7 @@
#define DOEPTSIZ0_SUPCNT_SHIFT 29 #define DOEPTSIZ0_SUPCNT_SHIFT 29
#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
#define DOEPTSIZ0_PKTCNT (1 << 19) #define DOEPTSIZ0_PKTCNT BIT(19)
#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
#define DOEPTSIZ0_XFERSIZE_SHIFT 0 #define DOEPTSIZ0_XFERSIZE_SHIFT 0
...@@ -614,55 +614,55 @@ ...@@ -614,55 +614,55 @@
#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
#define PCGCTL HSOTG_REG(0x0e00) #define PCGCTL HSOTG_REG(0x0e00)
#define PCGCTL_IF_DEV_MODE (1 << 31) #define PCGCTL_IF_DEV_MODE BIT(31)
#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 #define PCGCTL_MAC_DEV_ADDR_SHIFT 20
#define PCGCTL_MAX_TERMSEL (1 << 19) #define PCGCTL_MAX_TERMSEL BIT(19)
#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 #define PCGCTL_MAX_XCVRSELECT_SHIFT 17
#define PCGCTL_PORT_POWER (1 << 16) #define PCGCTL_PORT_POWER BIT(16)
#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
#define PCGCTL_PRT_CLK_SEL_SHIFT 14 #define PCGCTL_PRT_CLK_SEL_SHIFT 14
#define PCGCTL_ESS_REG_RESTORED (1 << 13) #define PCGCTL_ESS_REG_RESTORED BIT(13)
#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12) #define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11) #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
#define PCGCTL_ENBL_EXTND_HIBER (1 << 10) #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
#define PCGCTL_RESTOREMODE (1 << 9) #define PCGCTL_RESTOREMODE BIT(9)
#define PCGCTL_RESETAFTSUSP (1 << 8) #define PCGCTL_RESETAFTSUSP BIT(8)
#define PCGCTL_DEEP_SLEEP (1 << 7) #define PCGCTL_DEEP_SLEEP BIT(7)
#define PCGCTL_PHY_IN_SLEEP (1 << 6) #define PCGCTL_PHY_IN_SLEEP BIT(6)
#define PCGCTL_ENBL_SLEEP_GATING (1 << 5) #define PCGCTL_ENBL_SLEEP_GATING BIT(5)
#define PCGCTL_RSTPDWNMODULE (1 << 3) #define PCGCTL_RSTPDWNMODULE BIT(3)
#define PCGCTL_PWRCLMP (1 << 2) #define PCGCTL_PWRCLMP BIT(2)
#define PCGCTL_GATEHCLK (1 << 1) #define PCGCTL_GATEHCLK BIT(1)
#define PCGCTL_STOPPCLK (1 << 0) #define PCGCTL_STOPPCLK BIT(0)
#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
/* Host Mode Registers */ /* Host Mode Registers */
#define HCFG HSOTG_REG(0x0400) #define HCFG HSOTG_REG(0x0400)
#define HCFG_MODECHTIMEN (1 << 31) #define HCFG_MODECHTIMEN BIT(31)
#define HCFG_PERSCHEDENA (1 << 26) #define HCFG_PERSCHEDENA BIT(26)
#define HCFG_FRLISTEN_MASK (0x3 << 24) #define HCFG_FRLISTEN_MASK (0x3 << 24)
#define HCFG_FRLISTEN_SHIFT 24 #define HCFG_FRLISTEN_SHIFT 24
#define HCFG_FRLISTEN_8 (0 << 24) #define HCFG_FRLISTEN_8 (0 << 24)
#define FRLISTEN_8_SIZE 8 #define FRLISTEN_8_SIZE 8
#define HCFG_FRLISTEN_16 (1 << 24) #define HCFG_FRLISTEN_16 BIT(24)
#define FRLISTEN_16_SIZE 16 #define FRLISTEN_16_SIZE 16
#define HCFG_FRLISTEN_32 (2 << 24) #define HCFG_FRLISTEN_32 (2 << 24)
#define FRLISTEN_32_SIZE 32 #define FRLISTEN_32_SIZE 32
#define HCFG_FRLISTEN_64 (3 << 24) #define HCFG_FRLISTEN_64 (3 << 24)
#define FRLISTEN_64_SIZE 64 #define FRLISTEN_64_SIZE 64
#define HCFG_DESCDMA (1 << 23) #define HCFG_DESCDMA BIT(23)
#define HCFG_RESVALID_MASK (0xff << 8) #define HCFG_RESVALID_MASK (0xff << 8)
#define HCFG_RESVALID_SHIFT 8 #define HCFG_RESVALID_SHIFT 8
#define HCFG_ENA32KHZ (1 << 7) #define HCFG_ENA32KHZ BIT(7)
#define HCFG_FSLSSUPP (1 << 2) #define HCFG_FSLSSUPP BIT(2)
#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
#define HCFG_FSLSPCLKSEL_SHIFT 0 #define HCFG_FSLSPCLKSEL_SHIFT 0
#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 #define HCFG_FSLSPCLKSEL_30_60_MHZ 0
...@@ -672,7 +672,7 @@ ...@@ -672,7 +672,7 @@
#define HFIR HSOTG_REG(0x0404) #define HFIR HSOTG_REG(0x0404)
#define HFIR_FRINT_MASK (0xffff << 0) #define HFIR_FRINT_MASK (0xffff << 0)
#define HFIR_FRINT_SHIFT 0 #define HFIR_FRINT_SHIFT 0
#define HFIR_RLDCTRL (1 << 16) #define HFIR_RLDCTRL BIT(16)
#define HFNUM HSOTG_REG(0x0408) #define HFNUM HSOTG_REG(0x0408)
#define HFNUM_FRREM_MASK (0xffff << 16) #define HFNUM_FRREM_MASK (0xffff << 16)
...@@ -682,12 +682,12 @@ ...@@ -682,12 +682,12 @@
#define HFNUM_MAX_FRNUM 0x3fff #define HFNUM_MAX_FRNUM 0x3fff
#define HPTXSTS HSOTG_REG(0x0410) #define HPTXSTS HSOTG_REG(0x0410)
#define TXSTS_QTOP_ODD (1 << 31) #define TXSTS_QTOP_ODD BIT(31)
#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
#define TXSTS_QTOP_CHNEP_SHIFT 27 #define TXSTS_QTOP_CHNEP_SHIFT 27
#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
#define TXSTS_QTOP_TOKEN_SHIFT 25 #define TXSTS_QTOP_TOKEN_SHIFT 25
#define TXSTS_QTOP_TERMINATE (1 << 24) #define TXSTS_QTOP_TERMINATE BIT(24)
#define TXSTS_QSPCAVAIL_MASK (0xff << 16) #define TXSTS_QSPCAVAIL_MASK (0xff << 16)
#define TXSTS_QSPCAVAIL_SHIFT 16 #define TXSTS_QSPCAVAIL_SHIFT 16
#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) #define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
...@@ -705,39 +705,39 @@ ...@@ -705,39 +705,39 @@
#define HPRT0_SPD_LOW_SPEED 2 #define HPRT0_SPD_LOW_SPEED 2
#define HPRT0_TSTCTL_MASK (0xf << 13) #define HPRT0_TSTCTL_MASK (0xf << 13)
#define HPRT0_TSTCTL_SHIFT 13 #define HPRT0_TSTCTL_SHIFT 13
#define HPRT0_PWR (1 << 12) #define HPRT0_PWR BIT(12)
#define HPRT0_LNSTS_MASK (0x3 << 10) #define HPRT0_LNSTS_MASK (0x3 << 10)
#define HPRT0_LNSTS_SHIFT 10 #define HPRT0_LNSTS_SHIFT 10
#define HPRT0_RST (1 << 8) #define HPRT0_RST BIT(8)
#define HPRT0_SUSP (1 << 7) #define HPRT0_SUSP BIT(7)
#define HPRT0_RES (1 << 6) #define HPRT0_RES BIT(6)
#define HPRT0_OVRCURRCHG (1 << 5) #define HPRT0_OVRCURRCHG BIT(5)
#define HPRT0_OVRCURRACT (1 << 4) #define HPRT0_OVRCURRACT BIT(4)
#define HPRT0_ENACHG (1 << 3) #define HPRT0_ENACHG BIT(3)
#define HPRT0_ENA (1 << 2) #define HPRT0_ENA BIT(2)
#define HPRT0_CONNDET (1 << 1) #define HPRT0_CONNDET BIT(1)
#define HPRT0_CONNSTS (1 << 0) #define HPRT0_CONNSTS BIT(0)
#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
#define HCCHAR_CHENA (1 << 31) #define HCCHAR_CHENA BIT(31)
#define HCCHAR_CHDIS (1 << 30) #define HCCHAR_CHDIS BIT(30)
#define HCCHAR_ODDFRM (1 << 29) #define HCCHAR_ODDFRM BIT(29)
#define HCCHAR_DEVADDR_MASK (0x7f << 22) #define HCCHAR_DEVADDR_MASK (0x7f << 22)
#define HCCHAR_DEVADDR_SHIFT 22 #define HCCHAR_DEVADDR_SHIFT 22
#define HCCHAR_MULTICNT_MASK (0x3 << 20) #define HCCHAR_MULTICNT_MASK (0x3 << 20)
#define HCCHAR_MULTICNT_SHIFT 20 #define HCCHAR_MULTICNT_SHIFT 20
#define HCCHAR_EPTYPE_MASK (0x3 << 18) #define HCCHAR_EPTYPE_MASK (0x3 << 18)
#define HCCHAR_EPTYPE_SHIFT 18 #define HCCHAR_EPTYPE_SHIFT 18
#define HCCHAR_LSPDDEV (1 << 17) #define HCCHAR_LSPDDEV BIT(17)
#define HCCHAR_EPDIR (1 << 15) #define HCCHAR_EPDIR BIT(15)
#define HCCHAR_EPNUM_MASK (0xf << 11) #define HCCHAR_EPNUM_MASK (0xf << 11)
#define HCCHAR_EPNUM_SHIFT 11 #define HCCHAR_EPNUM_SHIFT 11
#define HCCHAR_MPS_MASK (0x7ff << 0) #define HCCHAR_MPS_MASK (0x7ff << 0)
#define HCCHAR_MPS_SHIFT 0 #define HCCHAR_MPS_SHIFT 0
#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
#define HCSPLT_SPLTENA (1 << 31) #define HCSPLT_SPLTENA BIT(31)
#define HCSPLT_COMPSPLT (1 << 16) #define HCSPLT_COMPSPLT BIT(16)
#define HCSPLT_XACTPOS_MASK (0x3 << 14) #define HCSPLT_XACTPOS_MASK (0x3 << 14)
#define HCSPLT_XACTPOS_SHIFT 14 #define HCSPLT_XACTPOS_SHIFT 14
#define HCSPLT_XACTPOS_MID 0 #define HCSPLT_XACTPOS_MID 0
...@@ -752,23 +752,23 @@ ...@@ -752,23 +752,23 @@
#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
#define HCINTMSK_FRM_LIST_ROLL (1 << 13) #define HCINTMSK_FRM_LIST_ROLL BIT(13)
#define HCINTMSK_XCS_XACT (1 << 12) #define HCINTMSK_XCS_XACT BIT(12)
#define HCINTMSK_BNA (1 << 11) #define HCINTMSK_BNA BIT(11)
#define HCINTMSK_DATATGLERR (1 << 10) #define HCINTMSK_DATATGLERR BIT(10)
#define HCINTMSK_FRMOVRUN (1 << 9) #define HCINTMSK_FRMOVRUN BIT(9)
#define HCINTMSK_BBLERR (1 << 8) #define HCINTMSK_BBLERR BIT(8)
#define HCINTMSK_XACTERR (1 << 7) #define HCINTMSK_XACTERR BIT(7)
#define HCINTMSK_NYET (1 << 6) #define HCINTMSK_NYET BIT(6)
#define HCINTMSK_ACK (1 << 5) #define HCINTMSK_ACK BIT(5)
#define HCINTMSK_NAK (1 << 4) #define HCINTMSK_NAK BIT(4)
#define HCINTMSK_STALL (1 << 3) #define HCINTMSK_STALL BIT(3)
#define HCINTMSK_AHBERR (1 << 2) #define HCINTMSK_AHBERR BIT(2)
#define HCINTMSK_CHHLTD (1 << 1) #define HCINTMSK_CHHLTD BIT(1)
#define HCINTMSK_XFERCOMPL (1 << 0) #define HCINTMSK_XFERCOMPL BIT(0)
#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
#define TSIZ_DOPNG (1 << 31) #define TSIZ_DOPNG BIT(31)
#define TSIZ_SC_MC_PID_MASK (0x3 << 29) #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
#define TSIZ_SC_MC_PID_SHIFT 29 #define TSIZ_SC_MC_PID_SHIFT 29
#define TSIZ_SC_MC_PID_DATA0 0 #define TSIZ_SC_MC_PID_DATA0 0
...@@ -808,14 +808,14 @@ struct dwc2_dma_desc { ...@@ -808,14 +808,14 @@ struct dwc2_dma_desc {
/* Host Mode DMA descriptor status quadlet */ /* Host Mode DMA descriptor status quadlet */
#define HOST_DMA_A (1 << 31) #define HOST_DMA_A BIT(31)
#define HOST_DMA_STS_MASK (0x3 << 28) #define HOST_DMA_STS_MASK (0x3 << 28)
#define HOST_DMA_STS_SHIFT 28 #define HOST_DMA_STS_SHIFT 28
#define HOST_DMA_STS_PKTERR (1 << 28) #define HOST_DMA_STS_PKTERR BIT(28)
#define HOST_DMA_EOL (1 << 26) #define HOST_DMA_EOL BIT(26)
#define HOST_DMA_IOC (1 << 25) #define HOST_DMA_IOC BIT(25)
#define HOST_DMA_SUP (1 << 24) #define HOST_DMA_SUP BIT(24)
#define HOST_DMA_ALT_QTD (1 << 23) #define HOST_DMA_ALT_QTD BIT(23)
#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
#define HOST_DMA_QTD_OFFSET_SHIFT 17 #define HOST_DMA_QTD_OFFSET_SHIFT 17
#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
...@@ -837,11 +837,11 @@ struct dwc2_dma_desc { ...@@ -837,11 +837,11 @@ struct dwc2_dma_desc {
#define DEV_DMA_STS_SUCC 0 #define DEV_DMA_STS_SUCC 0
#define DEV_DMA_STS_BUFF_FLUSH 1 #define DEV_DMA_STS_BUFF_FLUSH 1
#define DEV_DMA_STS_BUFF_ERR 3 #define DEV_DMA_STS_BUFF_ERR 3
#define DEV_DMA_L (1 << 27) #define DEV_DMA_L BIT(27)
#define DEV_DMA_SHORT (1 << 26) #define DEV_DMA_SHORT BIT(26)
#define DEV_DMA_IOC (1 << 25) #define DEV_DMA_IOC BIT(25)
#define DEV_DMA_SR (1 << 24) #define DEV_DMA_SR BIT(24)
#define DEV_DMA_MTRF (1 << 23) #define DEV_DMA_MTRF BIT(23)
#define DEV_DMA_ISOC_PID_MASK (0x3 << 23) #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
#define DEV_DMA_ISOC_PID_SHIFT 23 #define DEV_DMA_ISOC_PID_SHIFT 23
#define DEV_DMA_ISOC_PID_DATA0 0 #define DEV_DMA_ISOC_PID_DATA0 0
......
drivers/usb/dwc2/params.c
View file @ 9da51974
...@@ -1131,27 +1131,27 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg, ...@@ -1131,27 +1131,27 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
dwc2_set_param_host_support_fs_ls_low_power(hsotg, dwc2_set_param_host_support_fs_ls_low_power(hsotg,
params->host_support_fs_ls_low_power); params->host_support_fs_ls_low_power);
dwc2_set_param_enable_dynamic_fifo(hsotg, dwc2_set_param_enable_dynamic_fifo(hsotg,
params->enable_dynamic_fifo); params->enable_dynamic_fifo);
dwc2_set_param_max_transfer_size(hsotg, dwc2_set_param_max_transfer_size(hsotg,
params->max_transfer_size); params->max_transfer_size);
dwc2_set_param_max_packet_count(hsotg, dwc2_set_param_max_packet_count(hsotg,
params->max_packet_count); params->max_packet_count);
dwc2_set_param_host_channels(hsotg, params->host_channels); dwc2_set_param_host_channels(hsotg, params->host_channels);
dwc2_set_param_phy_type(hsotg, params->phy_type); dwc2_set_param_phy_type(hsotg, params->phy_type);
dwc2_set_param_speed(hsotg, params->speed); dwc2_set_param_speed(hsotg, params->speed);
dwc2_set_param_host_ls_low_power_phy_clk(hsotg, dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
params->host_ls_low_power_phy_clk); params->host_ls_low_power_phy_clk);
dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
dwc2_set_param_phy_ulpi_ext_vbus(hsotg, dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
params->phy_ulpi_ext_vbus); params->phy_ulpi_ext_vbus);
dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
dwc2_set_param_ts_dline(hsotg, params->ts_dline); dwc2_set_param_ts_dline(hsotg, params->ts_dline);
dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
dwc2_set_param_en_multiple_tx_fifo(hsotg, dwc2_set_param_en_multiple_tx_fifo(hsotg,
params->en_multiple_tx_fifo); params->en_multiple_tx_fifo);
dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
dwc2_set_param_otg_ver(hsotg, params->otg_ver); dwc2_set_param_otg_ver(hsotg, params->otg_ver);
......
drivers/usb/dwc2/pci.c
View file @ 9da51974
...@@ -87,7 +87,7 @@ static void dwc2_pci_remove(struct pci_dev *pci) ...@@ -87,7 +87,7 @@ static void dwc2_pci_remove(struct pci_dev *pci)
} }
static int dwc2_pci_probe(struct pci_dev *pci, static int dwc2_pci_probe(struct pci_dev *pci,
const struct pci_device_id *id) const struct pci_device_id *id)
{ {
struct resource res[2]; struct resource res[2];
struct platform_device *dwc2; struct platform_device *dwc2;
......
drivers/usb/dwc2/platform.c
View file @ 9da51974
...@@ -111,7 +111,7 @@ static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) ...@@ -111,7 +111,7 @@ static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
if (mode != hsotg->dr_mode) { if (mode != hsotg->dr_mode) {
dev_warn(hsotg->dev, dev_warn(hsotg->dev,
"Configuration mismatch. dr_mode forced to %s\n", "Configuration mismatch. dr_mode forced to %s\n",
mode == USB_DR_MODE_HOST ? "host" : "device"); mode == USB_DR_MODE_HOST ? "host" : "device");
hsotg->dr_mode = mode; hsotg->dr_mode = mode;
......
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