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Kirill Smelkov
linux
Commits
9fde9bdd
Commit
9fde9bdd
authored
Jul 09, 2008
by
Grant Likely
Browse files
Options
Browse Files
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Email Patches
Plain Diff
powerpc/440: Convert Virtex ML507 device tree to dts-v1
Signed-off-by:
Grant Likely
<
grant.likely@secretlab.ca
>
parent
c356aa45
Changes
1
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Showing
1 changed file
with
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and
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-99
arch/powerpc/boot/dts/virtex440-ml507.dts
arch/powerpc/boot/dts/virtex440-ml507.dts
+157
-99
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arch/powerpc/boot/dts/virtex440-ml507.dts
View file @
9fde9bdd
...
...
@@ -9,36 +9,42 @@
*
kind
,
whether
express
or
implied
.
*/
/
dts
-
v1
/;
/
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"xlnx,virtex440"
;
dcr
-
parent
=
<&
ppc440_
virtex5_
0
>;
dcr
-
parent
=
<&
ppc440_0
>;
model
=
"testing"
;
DDR2_SDRAM
:
memory
@
0
{
device_type
=
"memory"
;
reg
=
<
0
0x10000000
>;
}
;
chosen
{
bootargs
=
"console=ttyS0 ip=on root=/dev/ram"
;
linux
,
stdout
-
path
=
"/plb@0/serial@
d00
00000"
;
linux
,
stdout
-
path
=
"/plb@0/serial@
83e
00000"
;
}
;
cpus
{
#
address
-
cells
=
<
1
>;
#
cpus
=
<
1
>;
#
size
-
cells
=
<
0
>;
ppc440_
virtex5_
0
:
cpu
@
0
{
clock
-
frequency
=
<
17
d784
00
>;
ppc440_0
:
cpu
@
0
{
clock
-
frequency
=
<
4000000
00
>;
compatible
=
"PowerPC,440"
,
"ibm,ppc440"
;
d
-
cache
-
line
-
size
=
<
20
>;
d
-
cache
-
size
=
<
8000
>;
d
-
cache
-
line
-
size
=
<
0x
20
>;
d
-
cache
-
size
=
<
0x
8000
>;
dcr
-
access
-
method
=
"native"
;
dcr
-
controller
;
device_type
=
"cpu"
;
i
-
cache
-
line
-
size
=
<
20
>;
i
-
cache
-
size
=
<
8000
>;
i
-
cache
-
line
-
size
=
<
0x
20
>;
i
-
cache
-
size
=
<
0x
8000
>;
model
=
"PowerPC,440"
;
reg
=
<
0
>;
timebase
-
frequency
=
<
17
d784
00
>;
timebase
-
frequency
=
<
4000000
00
>;
xlnx
,
apu
-
control
=
<
1
>;
xlnx
,
apu
-
udi
-
0
=
<
c07701
>;
xlnx
,
apu
-
udi
-
1
=
<
c47701
>;
xlnx
,
apu
-
udi
-
0
=
<
0
>;
xlnx
,
apu
-
udi
-
1
=
<
0
>;
xlnx
,
apu
-
udi
-
10
=
<
0
>;
xlnx
,
apu
-
udi
-
11
=
<
0
>;
xlnx
,
apu
-
udi
-
12
=
<
0
>;
...
...
@@ -63,41 +69,41 @@ ppc440_virtex5_0: cpu@0 {
xlnx
,
dcu
-
wr
-
urgent
-
plb
-
prio
=
<
0
>;
xlnx
,
dma0
-
control
=
<
0
>;
xlnx
,
dma0
-
plb
-
prio
=
<
0
>;
xlnx
,
dma0
-
rxchannelctrl
=
<
1010000
>;
xlnx
,
dma0
-
rxirqtimer
=
<
3f
f
>;
xlnx
,
dma0
-
txchannelctrl
=
<
1010000
>;
xlnx
,
dma0
-
txirqtimer
=
<
3f
f
>;
xlnx
,
dma0
-
rxchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma0
-
rxirqtimer
=
<
0x
3ff
>;
xlnx
,
dma0
-
txchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma0
-
txirqtimer
=
<
0x
3ff
>;
xlnx
,
dma1
-
control
=
<
0
>;
xlnx
,
dma1
-
plb
-
prio
=
<
0
>;
xlnx
,
dma1
-
rxchannelctrl
=
<
1010000
>;
xlnx
,
dma1
-
rxirqtimer
=
<
3f
f
>;
xlnx
,
dma1
-
txchannelctrl
=
<
1010000
>;
xlnx
,
dma1
-
txirqtimer
=
<
3f
f
>;
xlnx
,
dma1
-
rxchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma1
-
rxirqtimer
=
<
0x
3ff
>;
xlnx
,
dma1
-
txchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma1
-
txirqtimer
=
<
0x
3ff
>;
xlnx
,
dma2
-
control
=
<
0
>;
xlnx
,
dma2
-
plb
-
prio
=
<
0
>;
xlnx
,
dma2
-
rxchannelctrl
=
<
1010000
>;
xlnx
,
dma2
-
rxirqtimer
=
<
3f
f
>;
xlnx
,
dma2
-
txchannelctrl
=
<
1010000
>;
xlnx
,
dma2
-
txirqtimer
=
<
3f
f
>;
xlnx
,
dma2
-
rxchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma2
-
rxirqtimer
=
<
0x
3ff
>;
xlnx
,
dma2
-
txchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma2
-
txirqtimer
=
<
0x
3ff
>;
xlnx
,
dma3
-
control
=
<
0
>;
xlnx
,
dma3
-
plb
-
prio
=
<
0
>;
xlnx
,
dma3
-
rxchannelctrl
=
<
1010000
>;
xlnx
,
dma3
-
rxirqtimer
=
<
3f
f
>;
xlnx
,
dma3
-
txchannelctrl
=
<
1010000
>;
xlnx
,
dma3
-
txirqtimer
=
<
3f
f
>;
xlnx
,
dma3
-
rxchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma3
-
rxirqtimer
=
<
0x
3ff
>;
xlnx
,
dma3
-
txchannelctrl
=
<
0x
1010000
>;
xlnx
,
dma3
-
txirqtimer
=
<
0x
3ff
>;
xlnx
,
endian
-
reset
=
<
0
>;
xlnx
,
generate
-
plb
-
timespecs
=
<
1
>;
xlnx
,
icu
-
rd
-
fetch
-
plb
-
prio
=
<
0
>;
xlnx
,
icu
-
rd
-
spec
-
plb
-
prio
=
<
0
>;
xlnx
,
icu
-
rd
-
touch
-
plb
-
prio
=
<
0
>;
xlnx
,
interconnect
-
imask
=
<
ffffffff
>;
xlnx
,
interconnect
-
imask
=
<
0x
ffffffff
>;
xlnx
,
mplb
-
allow
-
lock
-
xfer
=
<
1
>;
xlnx
,
mplb
-
arb
-
mode
=
<
0
>;
xlnx
,
mplb
-
awidth
=
<
20
>;
xlnx
,
mplb
-
counter
=
<
500
>;
xlnx
,
mplb
-
dwidth
=
<
80
>;
xlnx
,
mplb
-
awidth
=
<
0x
20
>;
xlnx
,
mplb
-
counter
=
<
0x
500
>;
xlnx
,
mplb
-
dwidth
=
<
0x
80
>;
xlnx
,
mplb
-
max
-
burst
=
<
8
>;
xlnx
,
mplb
-
native
-
dwidth
=
<
80
>;
xlnx
,
mplb
-
native
-
dwidth
=
<
0x
80
>;
xlnx
,
mplb
-
p2p
=
<
0
>;
xlnx
,
mplb
-
prio
-
dcur
=
<
2
>;
xlnx
,
mplb
-
prio
-
dcuw
=
<
3
>;
...
...
@@ -110,54 +116,41 @@ ppc440_virtex5_0: cpu@0 {
xlnx
,
mplb
-
write
-
pipe
-
enable
=
<
1
>;
xlnx
,
mplb
-
write
-
post
-
enable
=
<
1
>;
xlnx
,
num
-
dma
=
<
1
>;
xlnx
,
pir
=
<
f
>;
xlnx
,
pir
=
<
0x
f
>;
xlnx
,
ppc440mc
-
addr
-
base
=
<
0
>;
xlnx
,
ppc440mc
-
addr
-
high
=
<
1
f
ffffff
>;
xlnx
,
ppc440mc
-
addr
-
high
=
<
0x
fffffff
>;
xlnx
,
ppc440mc
-
arb
-
mode
=
<
0
>;
xlnx
,
ppc440mc
-
bank
-
conflict
-
mask
=
<
c00000
>;
xlnx
,
ppc440mc
-
control
=
<
f810008f
>;
xlnx
,
ppc440mc
-
bank
-
conflict
-
mask
=
<
0x
c00000
>;
xlnx
,
ppc440mc
-
control
=
<
0x
f810008f
>;
xlnx
,
ppc440mc
-
max
-
burst
=
<
8
>;
xlnx
,
ppc440mc
-
prio
-
dcur
=
<
2
>;
xlnx
,
ppc440mc
-
prio
-
dcuw
=
<
3
>;
xlnx
,
ppc440mc
-
prio
-
icu
=
<
4
>;
xlnx
,
ppc440mc
-
prio
-
splb0
=
<
1
>;
xlnx
,
ppc440mc
-
prio
-
splb1
=
<
0
>;
xlnx
,
ppc440mc
-
row
-
conflict
-
mask
=
<
3f
fe00
>;
xlnx
,
ppc440mc
-
row
-
conflict
-
mask
=
<
0x
3ffe00
>;
xlnx
,
ppcdm
-
asyncmode
=
<
0
>;
xlnx
,
ppcds
-
asyncmode
=
<
0
>;
xlnx
,
user
-
reset
=
<
0
>;
DMA0
:
sdma
@
80
{
compatible
=
"xlnx,ll-dma-1.00.a"
;
dcr
-
reg
=
<
80
11
>;
interrupt
-
parent
=
<&
opb
_intc_0
>;
interrupts
=
<
5
2
6
2
>;
dcr
-
reg
=
<
0x80
0x
11
>;
interrupt
-
parent
=
<&
xps
_intc_0
>;
interrupts
=
<
9
2
0xa
2
>;
}
;
}
;
}
;
plb_v46_
cfb_
0
:
plb
@
0
{
plb_v46_0
:
plb
@
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"xlnx,plb-v46-1.02.a"
;
compatible
=
"xlnx,plb-v46-1.02.a"
,
"simple-bus"
;
ranges
;
iic_bus
:
i2c
@
d0020000
{
compatible
=
"xlnx,xps-iic-2.00.a"
;
interrupt
-
parent
=
<&
opb_intc_0
>;
interrupts
=
<
7
2
>;
reg
=
<
d0020000
200
>;
xlnx
,
clk
-
freq
=
<
5f5e100
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
gpo
-
width
=
<
1
>;
xlnx
,
iic
-
freq
=
<
186
a0
>;
xlnx
,
scl
-
inertial
-
delay
=
<
0
>;
xlnx
,
sda
-
inertial
-
delay
=
<
0
>;
xlnx
,
ten
-
bit
-
adr
=
<
0
>;
}
;
leds_8bit
:
gpio
@
d0010200
{
DIP_Switches_8Bit
:
gpio
@
81460000
{
compatible
=
"xlnx,xps-gpio-1.00.a"
;
interrupt
-
parent
=
<&
opb
_intc_0
>;
interrupts
=
<
1
2
>;
reg
=
<
d0010200
2
00
>;
xlnx
,
all
-
inputs
=
<
0
>;
interrupt
-
parent
=
<&
xps
_intc_0
>;
interrupts
=
<
6
2
>;
reg
=
<
0x81460000
0x100
00
>;
xlnx
,
all
-
inputs
=
<
1
>;
xlnx
,
all
-
inputs
-
2
=
<
0
>;
xlnx
,
dout
-
default
=
<
0
>;
xlnx
,
dout
-
default
-
2
=
<
0
>;
...
...
@@ -167,72 +160,137 @@ leds_8bit: gpio@d0010200 {
xlnx
,
is
-
bidir
=
<
1
>;
xlnx
,
is
-
bidir
-
2
=
<
1
>;
xlnx
,
is
-
dual
=
<
0
>;
xlnx
,
tri
-
default
=
<
ffffffff
>;
xlnx
,
tri
-
default
-
2
=
<
ffffffff
>;
xlnx
,
tri
-
default
=
<
0x
ffffffff
>;
xlnx
,
tri
-
default
-
2
=
<
0x
ffffffff
>;
}
;
ll_temac_0
:
xps
-
ll
-
temac
@
912
00000
{
Hard_Ethernet_MAC
:
xps
-
ll
-
temac
@
81
c
00000
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"xlnx,compound"
;
ethernet
@
912
00000
{
compatible
=
"xlnx,xps-ll-temac-1.01.
a
"
;
ethernet
@
81
c
00000
{
compatible
=
"xlnx,xps-ll-temac-1.01.
b
"
;
device_type
=
"network"
;
interrupt
-
parent
=
<&
opb
_intc_0
>;
interrupts
=
<
4
2
>;
interrupt
-
parent
=
<&
xps
_intc_0
>;
interrupts
=
<
5
2
>;
llink
-
connected
=
<&
DMA0
>;
local
-
mac
-
address
=
[
02
00
00
00
00
00
];
reg
=
<
91200000
40
>;
reg
=
<
0x81c00000
0x
40
>;
xlnx
,
bus2core
-
clk
-
ratio
=
<
1
>;
xlnx
,
phy
-
type
=
<
1
>;
xlnx
,
phyaddr
=
<
1
>;
xlnx
,
rxcsum
=
<
0
>;
xlnx
,
rxfifo
=
<
4
000
>;
xlnx
,
rxcsum
=
<
1
>;
xlnx
,
rxfifo
=
<
0x1
000
>;
xlnx
,
temac
-
type
=
<
0
>;
xlnx
,
txcsum
=
<
0
>;
xlnx
,
txfifo
=
<
4
000
>;
xlnx
,
txcsum
=
<
1
>;
xlnx
,
txfifo
=
<
0x1
000
>;
}
;
}
;
opb_intc_0
:
interrupt
-
controller
@
d0020200
{
#
interrupt
-
cells
=
<
2
>;
compatible
=
"xlnx,xps-intc-1.00.a"
;
interrupt
-
controller
;
reg
=
<
d0020200
20
>;
xlnx
,
num
-
intr
-
inputs
=
<
8
>;
LEDs_8Bit
:
gpio
@
81400000
{
compatible
=
"xlnx,xps-gpio-1.00.a"
;
reg
=
<
0x81400000
0x10000
>;
xlnx
,
all
-
inputs
=
<
0
>;
xlnx
,
all
-
inputs
-
2
=
<
0
>;
xlnx
,
dout
-
default
=
<
0
>;
xlnx
,
dout
-
default
-
2
=
<
0
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
gpio
-
width
=
<
8
>;
xlnx
,
interrupt
-
present
=
<
0
>;
xlnx
,
is
-
bidir
=
<
1
>;
xlnx
,
is
-
bidir
-
2
=
<
1
>;
xlnx
,
is
-
dual
=
<
0
>;
xlnx
,
tri
-
default
=
<
0xffffffff
>;
xlnx
,
tri
-
default
-
2
=
<
0xffffffff
>;
}
;
plb_bram_if_cntlr_0
:
xps
-
bram
-
if
-
cntlr
@
ffff0000
{
compatible
=
"xlnx,xps-bram-if-cntlr-1.00.a"
;
reg
=
<
ffff0000
10000
>;
LEDs_Positions
:
gpio
@
81420000
{
compatible
=
"xlnx,xps-gpio-1.00.a"
;
reg
=
<
0x81420000
0x10000
>;
xlnx
,
all
-
inputs
=
<
0
>;
xlnx
,
all
-
inputs
-
2
=
<
0
>;
xlnx
,
dout
-
default
=
<
0
>;
xlnx
,
dout
-
default
-
2
=
<
0
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
gpio
-
width
=
<
5
>;
xlnx
,
interrupt
-
present
=
<
0
>;
xlnx
,
is
-
bidir
=
<
1
>;
xlnx
,
is
-
bidir
-
2
=
<
1
>;
xlnx
,
is
-
dual
=
<
0
>;
xlnx
,
tri
-
default
=
<
0xffffffff
>;
xlnx
,
tri
-
default
-
2
=
<
0xffffffff
>;
}
;
plb_bram_if_cntlr_1
:
xps
-
bram
-
if
-
cntlr
@
eee00000
{
compatible
=
"xlnx,xps-bram-if-cntlr-1.00.a"
;
reg
=
<
eee00000
2000
>;
Push_Buttons_5Bit
:
gpio
@
81440000
{
compatible
=
"xlnx,xps-gpio-1.00.a"
;
interrupt
-
parent
=
<&
xps_intc_0
>;
interrupts
=
<
7
2
>;
reg
=
<
0x81440000
0x10000
>;
xlnx
,
all
-
inputs
=
<
1
>;
xlnx
,
all
-
inputs
-
2
=
<
0
>;
xlnx
,
dout
-
default
=
<
0
>;
xlnx
,
dout
-
default
-
2
=
<
0
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
gpio
-
width
=
<
5
>;
xlnx
,
interrupt
-
present
=
<
1
>;
xlnx
,
is
-
bidir
=
<
1
>;
xlnx
,
is
-
bidir
-
2
=
<
1
>;
xlnx
,
is
-
dual
=
<
0
>;
xlnx
,
tri
-
default
=
<
0xffffffff
>;
xlnx
,
tri
-
default
-
2
=
<
0xffffffff
>;
}
;
rs232_uart_0
:
serial
@
d00
00000
{
clock
-
frequency
=
<
1
312
d
00
>;
RS232_Uart_1
:
serial
@
83e
00000
{
clock
-
frequency
=
<
1
000000
00
>;
compatible
=
"xlnx,xps-uart16550-2.00.a"
,
"ns16550"
;
current
-
speed
=
<
2580
>;
current
-
speed
=
<
0x
2580
>;
device_type
=
"serial"
;
interrupt
-
parent
=
<&
opb
_intc_0
>;
interrupts
=
<
0
2
>;
reg
=
<
d0000000
2
000
>;
reg
-
offset
=
<
100
3
>;
interrupt
-
parent
=
<&
xps
_intc_0
>;
interrupts
=
<
8
2
>;
reg
=
<
0x83e00000
0x10
000
>;
reg
-
offset
=
<
3
>;
reg
-
shift
=
<
2
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
has
-
external
-
rclk
=
<
0
>;
xlnx
,
has
-
external
-
xin
=
<
1
>;
xlnx
,
has
-
external
-
xin
=
<
0
>;
xlnx
,
is
-
a
-
16550
=
<
1
>;
}
;
sysace_compactflash
:
sysace
@
d00301
00
{
SysACE_CompactFlash
:
sysace
@
836000
00
{
compatible
=
"xlnx,xps-sysace-1.00.a"
;
reg
=
<
d0030100
80
>;
interrupt
-
parent
=
<&
xps_intc_0
>;
interrupts
=
<
4
2
>;
reg
=
<
0x83600000
0x10000
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
mem
-
width
=
<
10
>;
xlnx
,
mem
-
width
=
<
0x10
>;
}
;
xps_bram_if_cntlr_1
:
xps
-
bram
-
if
-
cntlr
@
ffff0000
{
compatible
=
"xlnx,xps-bram-if-cntlr-1.00.a"
;
reg
=
<
0xffff0000
0x10000
>;
xlnx
,
family
=
"virtex5"
;
}
;
xps_intc_0
:
interrupt
-
controller
@
81800000
{
#
interrupt
-
cells
=
<
2
>;
compatible
=
"xlnx,xps-intc-1.00.a"
;
interrupt
-
controller
;
reg
=
<
0x81800000
0x10000
>;
xlnx
,
num
-
intr
-
inputs
=
<
0xb
>;
}
;
xps_timebase_wdt_1
:
xps
-
timebase
-
wdt
@
83
a00000
{
compatible
=
"xlnx,xps-timebase-wdt-1.00.b"
;
interrupt
-
parent
=
<&
xps_intc_0
>;
interrupts
=
<
2
0
1
2
>;
reg
=
<
0x83a00000
0x10000
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
wdt
-
enable
-
once
=
<
0
>;
xlnx
,
wdt
-
interval
=
<
0x1e
>;
}
;
xps_timer_1
:
timer
@
83
c00000
{
compatible
=
"xlnx,xps-timer-1.00.a"
;
interrupt
-
parent
=
<&
xps_intc_0
>;
interrupts
=
<
3
2
>;
reg
=
<
0x83c00000
0x10000
>;
xlnx
,
count
-
width
=
<
0x20
>;
xlnx
,
family
=
"virtex5"
;
xlnx
,
gen0
-
assert
=
<
1
>;
xlnx
,
gen1
-
assert
=
<
1
>;
xlnx
,
one
-
timer
-
only
=
<
1
>;
xlnx
,
trig0
-
assert
=
<
1
>;
xlnx
,
trig1
-
assert
=
<
1
>;
}
;
}
;
ppc440mc_ddr2_0
:
memory
@
0
{
device_type
=
"memory"
;
reg
=
<
0
20000000
>;
}
;
}
;
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