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Merge series "Cirrus Logic CS35L41 Amplifier" from David Rhodes <drhodes@opensource.cirrus.com>: 

ASoC driver and devicetree documentation for a new
Cirrus Logic amplifier CS35L41

v7 changes:
Remove property 'classh-bst-max-limit'

David Rhodes (2):
  ASoC: cs35l41: CS35L41 Boosted Smart Amplifier
  ASoC: cs35l41: Add bindings for CS35L41

 .../devicetree/bindings/sound/cs35l41.yaml    |  151 ++
 include/sound/cs35l41.h                       |   34 +
 sound/soc/codecs/Kconfig                      |   12 +
 sound/soc/codecs/Makefile                     |    4 +
 sound/soc/codecs/cs35l41-i2c.c                |  114 ++
 sound/soc/codecs/cs35l41-spi.c                |  143 ++
 sound/soc/codecs/cs35l41-tables.c             |  597 +++++++
 sound/soc/codecs/cs35l41.c                    | 1545 +++++++++++++++++
 sound/soc/codecs/cs35l41.h                    |  775 +++++++++
 9 files changed, 3375 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/cs35l41.yaml
 create mode 100644 include/sound/cs35l41.h
 create mode 100644 sound/soc/codecs/cs35l41-i2c.c
 create mode 100644 sound/soc/codecs/cs35l41-spi.c
 create mode 100644 sound/soc/codecs/cs35l41-tables.c
 create mode 100644 sound/soc/codecs/cs35l41.c
 create mode 100644 sound/soc/codecs/cs35l41.h

--
2.25.1
parents 599b1032 8d7ab880
Hide whitespace changes
Inline Side-by-side
Showing with 3375 additions and 0 deletions
Documentation/devicetree/bindings/sound/cs35l41.yaml 0 → 100644
View file @ a13a228e
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/cs35l41.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic CS35L41 Speaker Amplifier
maintainers:
- david.rhodes@cirrus.com
description: |
CS35L41 is a boosted mono Class D amplifier with DSP
speaker protection and equalization
properties:
compatible:
enum:
- cirrus,cs35l40
- cirrus,cs35l41
reg:
maxItems: 1
'#sound-dai-cells':
description:
The first cell indicating the audio interface.
const: 1
reset-gpios:
maxItems: 1
VA-supply:
description: voltage regulator phandle for the VA supply
VP-supply:
description: voltage regulator phandle for the VP supply
cirrus,boost-peak-milliamp:
description:
Boost-converter peak current limit in mA.
Configures the peak current by monitoring the current through the boost FET.
Range starts at 1600 mA and goes to a maximum of 4500 mA with increments
of 50 mA. See section 4.3.6 of the datasheet for details.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 1600
maximum: 4500
default: 4500
cirrus,boost-ind-nanohenry:
description:
Boost inductor value, expressed in nH. Valid
values include 1000, 1200, 1500 and 2200.
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 1000
maximum: 2200
cirrus,boost-cap-microfarad:
description:
Total equivalent boost capacitance on the VBST
and VAMP pins, derated at 11 volts DC. The value must be rounded to the
nearest integer and expressed in uF.
$ref: "/schemas/types.yaml#/definitions/uint32"
cirrus,asp-sdout-hiz:
description:
Audio serial port SDOUT Hi-Z control. Sets the Hi-Z
configuration for SDOUT pin of amplifier.
0 = Logic 0 during unused slots, and while all transmit channels disabled
1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled
2 = (Default) Logic 0 during unused slots, but Hi-Z while all transmit channels disabled
3 = Hi-Z during unused slots and while all transmit channels disabled
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 3
default: 2
cirrus,gpio1-polarity-invert:
description:
Boolean which specifies whether the GPIO1
level is inverted. If this property is not present the level is not inverted.
type: boolean
cirrus,gpio1-output-enable:
description:
Boolean which specifies whether the GPIO1 pin
is configured as an output. If this property is not present the
pin will be configured as an input.
type: boolean
cirrus,gpio1-src-select:
description:
Configures the function of the GPIO1 pin.
Note that the options are different from the GPIO2 pin
0 = High Impedance (Default)
1 = GPIO
2 = Sync
3 = MCLK input
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 3
cirrus,gpio2-polarity-invert:
description:
Boolean which specifies whether the GPIO2
level is inverted. If this property is not present the level is not inverted.
type: boolean
cirrus,gpio2-output-enable:
description:
Boolean which specifies whether the GPIO2 pin
is configured as an output. If this property is not present the
pin will be configured as an input.
type: boolean
cirrus,gpio2-src-select:
description:
Configures the function of the GPIO2 pin.
Note that the options are different from the GPIO1 pin.
0 = High Impedance (Default)
1 = GPIO
2 = Open Drain INTB
3 = MCLK input
4 = Push-pull INTB (active low)
5 = Push-pull INT (active high)
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 5
required:
- compatible
- reg
- "#sound-dai-cells"
- cirrus,boost-peak-milliamp
- cirrus,boost-ind-nanohenry
- cirrus,boost-cap-microfarad
unevaluatedProperties: false
examples:
- |
cs35l41: cs35l41@2 {
compatible = "cirrus,cs35l41";
reg = <2>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
reset-gpios = <&gpio 110 0>;
cirrus,boost-peak-milliamp = <4500>;
cirrus,boost-ind-nanohenry = <1000>;
cirrus,boost-cap-microfarad = <15>;
};
\ No newline at end of file
include/sound/cs35l41.h 0 → 100644
View file @ a13a228e
/* SPDX-License-Identifier: GPL-2.0
*
* linux/sound/cs35l41.h -- Platform data for CS35L41
*
* Copyright (c) 2017-2021 Cirrus Logic Inc.
*
* Author: David Rhodes <david.rhodes@cirrus.com>
*/
#ifndef __CS35L41_H
#define __CS35L41_H
enum cs35l41_clk_ids {
CS35L41_CLKID_SCLK = 0,
CS35L41_CLKID_LRCLK = 1,
CS35L41_CLKID_MCLK = 4,
};
struct cs35l41_irq_cfg {
bool irq_pol_inv;
bool irq_out_en;
int irq_src_sel;
};
struct cs35l41_platform_data {
int bst_ind;
int bst_ipk;
int bst_cap;
int dout_hiz;
struct cs35l41_irq_cfg irq_config1;
struct cs35l41_irq_cfg irq_config2;
};
#endif /* __CS35L41_H */
sound/soc/codecs/Kconfig
View file @ a13a228e
...@@ -61,6 +61,8 @@ config SND_SOC_ALL_CODECS ...@@ -61,6 +61,8 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_CS35L34 imply SND_SOC_CS35L34
imply SND_SOC_CS35L35 imply SND_SOC_CS35L35
imply SND_SOC_CS35L36 imply SND_SOC_CS35L36
imply SND_SOC_CS35L41_SPI
imply SND_SOC_CS35L41_I2C
imply SND_SOC_CS42L42 imply SND_SOC_CS42L42
imply SND_SOC_CS42L51_I2C imply SND_SOC_CS42L51_I2C
imply SND_SOC_CS42L52 imply SND_SOC_CS42L52
...@@ -603,6 +605,16 @@ config SND_SOC_CS35L36 ...@@ -603,6 +605,16 @@ config SND_SOC_CS35L36
tristate "Cirrus Logic CS35L36 CODEC" tristate "Cirrus Logic CS35L36 CODEC"
depends on I2C depends on I2C
config SND_SOC_CS35L41_SPI
tristate "Cirrus Logic CS35L41 CODEC (SPI)"
depends on SPI_MASTER
select REGMAP_SPI
config SND_SOC_CS35L41_I2C
tristate "Cirrus Logic CS35L41 CODEC (I2C)"
depends on I2C
select REGMAP_I2C
config SND_SOC_CS42L42 config SND_SOC_CS42L42
tristate "Cirrus Logic CS42L42 CODEC" tristate "Cirrus Logic CS42L42 CODEC"
depends on I2C depends on I2C
......
sound/soc/codecs/Makefile
View file @ a13a228e
...@@ -54,6 +54,8 @@ snd-soc-cs35l33-objs := cs35l33.o ...@@ -54,6 +54,8 @@ snd-soc-cs35l33-objs := cs35l33.o
snd-soc-cs35l34-objs := cs35l34.o snd-soc-cs35l34-objs := cs35l34.o
snd-soc-cs35l35-objs := cs35l35.o snd-soc-cs35l35-objs := cs35l35.o
snd-soc-cs35l36-objs := cs35l36.o snd-soc-cs35l36-objs := cs35l36.o
snd-soc-cs35l41-spi-objs := cs35l41-spi.o cs35l41.o cs35l41-tables.o
snd-soc-cs35l41-i2c-objs := cs35l41-i2c.o cs35l41.o cs35l41-tables.o
snd-soc-cs42l42-objs := cs42l42.o snd-soc-cs42l42-objs := cs42l42.o
snd-soc-cs42l51-objs := cs42l51.o snd-soc-cs42l51-objs := cs42l51.o
snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
...@@ -386,6 +388,8 @@ obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o ...@@ -386,6 +388,8 @@ obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o
obj-$(CONFIG_SND_SOC_CS35L34) += snd-soc-cs35l34.o obj-$(CONFIG_SND_SOC_CS35L34) += snd-soc-cs35l34.o
obj-$(CONFIG_SND_SOC_CS35L35) += snd-soc-cs35l35.o obj-$(CONFIG_SND_SOC_CS35L35) += snd-soc-cs35l35.o
obj-$(CONFIG_SND_SOC_CS35L36) += snd-soc-cs35l36.o obj-$(CONFIG_SND_SOC_CS35L36) += snd-soc-cs35l36.o
obj-$(CONFIG_SND_SOC_CS35L41_SPI) += snd-soc-cs35l41-spi.o
obj-$(CONFIG_SND_SOC_CS35L41_I2C) += snd-soc-cs35l41-i2c.o
obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42.o obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42.o
obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
......
sound/soc/codecs/cs35l41-i2c.c 0 → 100644
View file @ a13a228e
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41-i2c.c -- CS35l41 I2C driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <david.rhodes@cirrus.com>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/cs35l41.h>
#include "cs35l41.h"
static struct regmap_config cs35l41_regmap_i2c = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = CS35L41_REGSTRIDE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct i2c_device_id cs35l41_id_i2c[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l41_id_i2c);
static int cs35l41_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct cs35l41_private *cs35l41;
struct device *dev = &client->dev;
struct cs35l41_platform_data *pdata = dev_get_platdata(dev);
const struct regmap_config *regmap_config = &cs35l41_regmap_i2c;
int ret;
cs35l41 = devm_kzalloc(dev, sizeof(struct cs35l41_private), GFP_KERNEL);
if (!cs35l41)
return -ENOMEM;
cs35l41->dev = dev;
cs35l41->irq = client->irq;
i2c_set_clientdata(client, cs35l41);
cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(cs35l41->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return cs35l41_probe(cs35l41, pdata);
}
static int cs35l41_i2c_remove(struct i2c_client *client)
{
struct cs35l41_private *cs35l41 = i2c_get_clientdata(client);
return cs35l41_remove(cs35l41);
}
#ifdef CONFIG_OF
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id cs35l41_acpi_match[] = {
{ "CSC3541", 0 }, /* Cirrus Logic PnP ID + part ID */
{},
};
MODULE_DEVICE_TABLE(acpi, cs35l41_acpi_match);
#endif
static struct i2c_driver cs35l41_i2c_driver = {
.driver = {
.name = "cs35l41",
.of_match_table = of_match_ptr(cs35l41_of_match),
.acpi_match_table = ACPI_PTR(cs35l41_acpi_match),
},
.id_table = cs35l41_id_i2c,
.probe = cs35l41_i2c_probe,
.remove = cs35l41_i2c_remove,
};
module_i2c_driver(cs35l41_i2c_driver);
MODULE_DESCRIPTION("I2C CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/cs35l41-spi.c 0 → 100644
View file @ a13a228e
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41-spi.c -- CS35l41 SPI driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <david.rhodes@cirrus.com>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/cs35l41.h>
#include "cs35l41.h"
static struct regmap_config cs35l41_regmap_spi = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = CS35L41_REGSTRIDE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L41_LASTREG,
.reg_defaults = cs35l41_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
.volatile_reg = cs35l41_volatile_reg,
.readable_reg = cs35l41_readable_reg,
.precious_reg = cs35l41_precious_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct spi_device_id cs35l41_id_spi[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, cs35l41_id_spi);
static void cs35l41_spi_otp_setup(struct cs35l41_private *cs35l41,
bool is_pre_setup, unsigned int *freq)
{
struct spi_device *spi;
u32 orig_spi_freq;
spi = to_spi_device(cs35l41->dev);
if (!spi) {
dev_err(cs35l41->dev, "%s: No SPI device\n", __func__);
return;
}
if (is_pre_setup) {
orig_spi_freq = spi->max_speed_hz;
if (orig_spi_freq > CS35L41_SPI_MAX_FREQ_OTP) {
spi->max_speed_hz = CS35L41_SPI_MAX_FREQ_OTP;
spi_setup(spi);
}
*freq = orig_spi_freq;
} else {
if (spi->max_speed_hz != *freq) {
spi->max_speed_hz = *freq;
spi_setup(spi);
}
}
}
static int cs35l41_spi_probe(struct spi_device *spi)
{
const struct regmap_config *regmap_config = &cs35l41_regmap_spi;
struct cs35l41_platform_data *pdata =
dev_get_platdata(&spi->dev);
struct cs35l41_private *cs35l41;
int ret;
cs35l41 = devm_kzalloc(&spi->dev,
sizeof(struct cs35l41_private),
GFP_KERNEL);
if (!cs35l41)
return -ENOMEM;
spi_set_drvdata(spi, cs35l41);
cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
cs35l41->dev = &spi->dev;
cs35l41->irq = spi->irq;
cs35l41->otp_setup = cs35l41_spi_otp_setup;
return cs35l41_probe(cs35l41, pdata);
}
static int cs35l41_spi_remove(struct spi_device *spi)
{
struct cs35l41_private *cs35l41 = spi_get_drvdata(spi);
return cs35l41_remove(cs35l41);
}
#ifdef CONFIG_OF
static const struct of_device_id cs35l41_of_match[] = {
{ .compatible = "cirrus,cs35l40" },
{ .compatible = "cirrus,cs35l41" },
{},
};
MODULE_DEVICE_TABLE(of, cs35l41_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id cs35l41_acpi_match[] = {
{ "CSC3541", 0 }, /* Cirrus Logic PnP ID + part ID */
{},
};
MODULE_DEVICE_TABLE(acpi, cs35l41_acpi_match);
#endif
static struct spi_driver cs35l41_spi_driver = {
.driver = {
.name = "cs35l41",
.of_match_table = of_match_ptr(cs35l41_of_match),
.acpi_match_table = ACPI_PTR(cs35l41_acpi_match),
},
.id_table = cs35l41_id_spi,
.probe = cs35l41_spi_probe,
.remove = cs35l41_spi_remove,
};
module_spi_driver(cs35l41_spi_driver);
MODULE_DESCRIPTION("SPI CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/cs35l41-tables.c 0 → 100644
View file @ a13a228e
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41-tables.c -- CS35L41 ALSA SoC audio driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <david.rhodes@cirrus.com>
#include "cs35l41.h"
const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = {
{CS35L41_PWR_CTRL1, 0x00000000},
{CS35L41_PWR_CTRL3, 0x01000010},
{CS35L41_GPIO_PAD_CONTROL, 0x00000000},
{CS35L41_SP_ENABLES, 0x00000000},
{CS35L41_SP_RATE_CTRL, 0x00000028},
{CS35L41_SP_FORMAT, 0x18180200},
{CS35L41_SP_HIZ_CTRL, 0x00000002},
{CS35L41_SP_FRAME_TX_SLOT, 0x03020100},
{CS35L41_SP_FRAME_RX_SLOT, 0x00000100},
{CS35L41_SP_TX_WL, 0x00000018},
{CS35L41_SP_RX_WL, 0x00000018},
{CS35L41_DAC_PCM1_SRC, 0x00000008},
{CS35L41_ASP_TX1_SRC, 0x00000018},
{CS35L41_ASP_TX2_SRC, 0x00000019},
{CS35L41_ASP_TX3_SRC, 0x00000020},
{CS35L41_ASP_TX4_SRC, 0x00000021},
{CS35L41_DSP1_RX1_SRC, 0x00000008},
{CS35L41_DSP1_RX2_SRC, 0x00000009},
{CS35L41_DSP1_RX3_SRC, 0x00000018},
{CS35L41_DSP1_RX4_SRC, 0x00000019},
{CS35L41_DSP1_RX5_SRC, 0x00000020},
{CS35L41_DSP1_RX6_SRC, 0x00000021},
{CS35L41_DSP1_RX7_SRC, 0x0000003A},
{CS35L41_DSP1_RX8_SRC, 0x00000001},
{CS35L41_NGATE1_SRC, 0x00000008},
{CS35L41_NGATE2_SRC, 0x00000009},
{CS35L41_AMP_DIG_VOL_CTRL, 0x00008000},
{CS35L41_CLASSH_CFG, 0x000B0405},
{CS35L41_WKFET_CFG, 0x00000111},
{CS35L41_NG_CFG, 0x00000033},
{CS35L41_AMP_GAIN_CTRL, 0x00000273},
{CS35L41_GPIO1_CTRL1, 0xE1000001},
{CS35L41_GPIO2_CTRL1, 0xE1000001},
{CS35L41_MIXER_NGATE_CFG, 0x00000000},
{CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303},
{CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303},
};
bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_REVID:
case CS35L41_FABID:
case CS35L41_RELID:
case CS35L41_OTPID:
case CS35L41_TEST_KEY_CTL:
case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_CTRL0:
case CS35L41_OTP_CTRL3:
case CS35L41_OTP_CTRL4:
case CS35L41_OTP_CTRL5:
case CS35L41_OTP_CTRL6:
case CS35L41_OTP_CTRL7:
case CS35L41_OTP_CTRL8:
case CS35L41_PWR_CTRL1:
case CS35L41_PWR_CTRL2:
case CS35L41_PWR_CTRL3:
case CS35L41_CTRL_OVRRIDE:
case CS35L41_AMP_OUT_MUTE:
case CS35L41_PROTECT_REL_ERR_IGN:
case CS35L41_GPIO_PAD_CONTROL:
case CS35L41_JTAG_CONTROL:
case CS35L41_PLL_CLK_CTRL:
case CS35L41_DSP_CLK_CTRL:
case CS35L41_GLOBAL_CLK_CTRL:
case CS35L41_DATA_FS_SEL:
case CS35L41_MDSYNC_EN:
case CS35L41_MDSYNC_TX_ID:
case CS35L41_MDSYNC_PWR_CTRL:
case CS35L41_MDSYNC_DATA_TX:
case CS35L41_MDSYNC_TX_STATUS:
case CS35L41_MDSYNC_DATA_RX:
case CS35L41_MDSYNC_RX_STATUS:
case CS35L41_MDSYNC_ERR_STATUS:
case CS35L41_MDSYNC_SYNC_PTE2:
case CS35L41_MDSYNC_SYNC_PTE3:
case CS35L41_MDSYNC_SYNC_MSM_STATUS:
case CS35L41_BSTCVRT_VCTRL1:
case CS35L41_BSTCVRT_VCTRL2:
case CS35L41_BSTCVRT_PEAK_CUR:
case CS35L41_BSTCVRT_SFT_RAMP:
case CS35L41_BSTCVRT_COEFF:
case CS35L41_BSTCVRT_SLOPE_LBST:
case CS35L41_BSTCVRT_SW_FREQ:
case CS35L41_BSTCVRT_DCM_CTRL:
case CS35L41_BSTCVRT_DCM_MODE_FORCE:
case CS35L41_BSTCVRT_OVERVOLT_CTRL:
case CS35L41_VI_VOL_POL:
case CS35L41_DTEMP_WARN_THLD:
case CS35L41_DTEMP_CFG:
case CS35L41_DTEMP_EN:
case CS35L41_VPVBST_FS_SEL:
case CS35L41_SP_ENABLES:
case CS35L41_SP_RATE_CTRL:
case CS35L41_SP_FORMAT:
case CS35L41_SP_HIZ_CTRL:
case CS35L41_SP_FRAME_TX_SLOT:
case CS35L41_SP_FRAME_RX_SLOT:
case CS35L41_SP_TX_WL:
case CS35L41_SP_RX_WL:
case CS35L41_DAC_PCM1_SRC:
case CS35L41_ASP_TX1_SRC:
case CS35L41_ASP_TX2_SRC:
case CS35L41_ASP_TX3_SRC:
case CS35L41_ASP_TX4_SRC:
case CS35L41_DSP1_RX1_SRC:
case CS35L41_DSP1_RX2_SRC:
case CS35L41_DSP1_RX3_SRC:
case CS35L41_DSP1_RX4_SRC:
case CS35L41_DSP1_RX5_SRC:
case CS35L41_DSP1_RX6_SRC:
case CS35L41_DSP1_RX7_SRC:
case CS35L41_DSP1_RX8_SRC:
case CS35L41_NGATE1_SRC:
case CS35L41_NGATE2_SRC:
case CS35L41_AMP_DIG_VOL_CTRL:
case CS35L41_VPBR_CFG:
case CS35L41_VBBR_CFG:
case CS35L41_VPBR_STATUS:
case CS35L41_VBBR_STATUS:
case CS35L41_OVERTEMP_CFG:
case CS35L41_AMP_ERR_VOL:
case CS35L41_VOL_STATUS_TO_DSP:
case CS35L41_CLASSH_CFG:
case CS35L41_WKFET_CFG:
case CS35L41_NG_CFG:
case CS35L41_AMP_GAIN_CTRL:
case CS35L41_DAC_MSM_CFG:
case CS35L41_IRQ1_CFG:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_MASK1:
case CS35L41_IRQ1_MASK2:
case CS35L41_IRQ1_MASK3:
case CS35L41_IRQ1_MASK4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_CFG:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_MASK1:
case CS35L41_IRQ2_MASK2:
case CS35L41_IRQ2_MASK3:
case CS35L41_IRQ2_MASK4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_GPIO1_CTRL1:
case CS35L41_GPIO2_CTRL1:
case CS35L41_MIXER_NGATE_CFG:
case CS35L41_MIXER_NGATE_CH1_CFG:
case CS35L41_MIXER_NGATE_CH2_CFG:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_CLOCK_DETECT_1:
case CS35L41_DIE_STS1:
case CS35L41_DIE_STS2:
case CS35L41_TEMP_CAL1:
case CS35L41_TEMP_CAL2:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
/*test regs*/
case CS35L41_PLL_OVR:
case CS35L41_BST_TEST_DUTY:
case CS35L41_DIGPWM_IOCTRL:
return true;
default:
return false;
}
}
bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L41_DEVID:
case CS35L41_SFT_RESET:
case CS35L41_FABID:
case CS35L41_REVID:
case CS35L41_DTEMP_EN:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
case CS35L41_IRQ1_STATUS2:
case CS35L41_IRQ1_STATUS3:
case CS35L41_IRQ1_STATUS4:
case CS35L41_IRQ1_RAW_STATUS1:
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
case CS35L41_IRQ1_FRC1:
case CS35L41_IRQ1_FRC2:
case CS35L41_IRQ1_FRC3:
case CS35L41_IRQ1_FRC4:
case CS35L41_IRQ1_EDGE1:
case CS35L41_IRQ1_EDGE4:
case CS35L41_IRQ1_POL1:
case CS35L41_IRQ1_POL2:
case CS35L41_IRQ1_POL3:
case CS35L41_IRQ1_POL4:
case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
case CS35L41_IRQ2_STATUS3:
case CS35L41_IRQ2_STATUS4:
case CS35L41_IRQ2_RAW_STATUS1:
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
case CS35L41_IRQ2_FRC1:
case CS35L41_IRQ2_FRC2:
case CS35L41_IRQ2_FRC3:
case CS35L41_IRQ2_FRC4:
case CS35L41_IRQ2_EDGE1:
case CS35L41_IRQ2_EDGE4:
case CS35L41_IRQ2_POL1:
case CS35L41_IRQ2_POL2:
case CS35L41_IRQ2_POL3:
case CS35L41_IRQ2_POL4:
case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
case CS35L41_OTP_TRIM_1:
case CS35L41_OTP_TRIM_2:
case CS35L41_OTP_TRIM_3:
case CS35L41_OTP_TRIM_4:
case CS35L41_OTP_TRIM_5:
case CS35L41_OTP_TRIM_6:
case CS35L41_OTP_TRIM_7:
case CS35L41_OTP_TRIM_8:
case CS35L41_OTP_TRIM_9:
case CS35L41_OTP_TRIM_10:
case CS35L41_OTP_TRIM_11:
case CS35L41_OTP_TRIM_12:
case CS35L41_OTP_TRIM_13:
case CS35L41_OTP_TRIM_14:
case CS35L41_OTP_TRIM_15:
case CS35L41_OTP_TRIM_16:
case CS35L41_OTP_TRIM_17:
case CS35L41_OTP_TRIM_18:
case CS35L41_OTP_TRIM_19:
case CS35L41_OTP_TRIM_20:
case CS35L41_OTP_TRIM_21:
case CS35L41_OTP_TRIM_22:
case CS35L41_OTP_TRIM_23:
case CS35L41_OTP_TRIM_24:
case CS35L41_OTP_TRIM_25:
case CS35L41_OTP_TRIM_26:
case CS35L41_OTP_TRIM_27:
case CS35L41_OTP_TRIM_28:
case CS35L41_OTP_TRIM_29:
case CS35L41_OTP_TRIM_30:
case CS35L41_OTP_TRIM_31:
case CS35L41_OTP_TRIM_32:
case CS35L41_OTP_TRIM_33:
case CS35L41_OTP_TRIM_34:
case CS35L41_OTP_TRIM_35:
case CS35L41_OTP_TRIM_36:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
return false;
}
}
static const struct cs35l41_otp_packed_element_t
otp_map_1[CS35L41_NUM_OTP_ELEM] = {
/* addr shift size */
{0x00002030, 0, 4}, /*TRIM_OSC_FREQ_TRIM*/
{0x00002030, 7, 1}, /*TRIM_OSC_TRIM_DONE*/
{0x0000208c, 24, 6}, /*TST_DIGREG_VREF_TRIM*/
{0x00002090, 14, 4}, /*TST_REF_TRIM*/
{0x00002090, 10, 4}, /*TST_REF_TEMPCO_TRIM*/
{0x0000300C, 11, 4}, /*PLL_LDOA_TST_VREF_TRIM*/
{0x0000394C, 23, 2}, /*BST_ATEST_CM_VOFF*/
{0x00003950, 0, 7}, /*BST_ATRIM_IADC_OFFSET*/
{0x00003950, 8, 7}, /*BST_ATRIM_IADC_GAIN1*/
{0x00003950, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{0x00003950, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN1*/
{0x00003954, 0, 7}, /*BST_ATRIM_IADC_OFFSET2*/
{0x00003954, 8, 7}, /*BST_ATRIM_IADC_GAIN2*/
{0x00003954, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{0x00003954, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN2*/
{0x00003958, 0, 7}, /*BST_ATRIM_IADC_OFFSET3*/
{0x00003958, 8, 7}, /*BST_ATRIM_IADC_GAIN3*/
{0x00003958, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{0x00003958, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN3*/
{0x0000395C, 0, 7}, /*BST_ATRIM_IADC_OFFSET4*/
{0x0000395C, 8, 7}, /*BST_ATRIM_IADC_GAIN4*/
{0x0000395C, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{0x0000395C, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN4*/
{0x0000416C, 0, 8}, /*VMON_GAIN_OTP_VAL*/
{0x00004160, 0, 7}, /*VMON_OFFSET_OTP_VAL*/
{0x0000416C, 8, 8}, /*IMON_GAIN_OTP_VAL*/
{0x00004160, 16, 10}, /*IMON_OFFSET_OTP_VAL*/
{0x0000416C, 16, 12}, /*VMON_CM_GAIN_OTP_VAL*/
{0x0000416C, 28, 1}, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{0x00004170, 0, 6}, /*IMON_CAL_TEMPCO_OTP_VAL*/
{0x00004170, 6, 1}, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{0x00004170, 8, 6}, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{0x00004170, 14, 1}, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{0x00004170, 16, 9}, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{0x00004360, 0, 5}, /*TEMP_GAIN_OTP_VAL*/
{0x00004360, 6, 9}, /*TEMP_OFFSET_OTP_VAL*/
{0x00004448, 0, 8}, /*VP_SARADC_OFFSET*/
{0x00004448, 8, 8}, /*VP_GAIN_INDEX*/
{0x00004448, 16, 8}, /*VBST_SARADC_OFFSET*/
{0x00004448, 24, 8}, /*VBST_GAIN_INDEX*/
{0x0000444C, 0, 3}, /*ANA_SELINVREF*/
{0x00006E30, 0, 5}, /*GAIN_ERR_COEFF_0*/
{0x00006E30, 8, 5}, /*GAIN_ERR_COEFF_1*/
{0x00006E30, 16, 5}, /*GAIN_ERR_COEFF_2*/
{0x00006E30, 24, 5}, /*GAIN_ERR_COEFF_3*/
{0x00006E34, 0, 5}, /*GAIN_ERR_COEFF_4*/
{0x00006E34, 8, 5}, /*GAIN_ERR_COEFF_5*/
{0x00006E34, 16, 5}, /*GAIN_ERR_COEFF_6*/
{0x00006E34, 24, 5}, /*GAIN_ERR_COEFF_7*/
{0x00006E38, 0, 5}, /*GAIN_ERR_COEFF_8*/
{0x00006E38, 8, 5}, /*GAIN_ERR_COEFF_9*/
{0x00006E38, 16, 5}, /*GAIN_ERR_COEFF_10*/
{0x00006E38, 24, 5}, /*GAIN_ERR_COEFF_11*/
{0x00006E3C, 0, 5}, /*GAIN_ERR_COEFF_12*/
{0x00006E3C, 8, 5}, /*GAIN_ERR_COEFF_13*/
{0x00006E3C, 16, 5}, /*GAIN_ERR_COEFF_14*/
{0x00006E3C, 24, 5}, /*GAIN_ERR_COEFF_15*/
{0x00006E40, 0, 5}, /*GAIN_ERR_COEFF_16*/
{0x00006E40, 8, 5}, /*GAIN_ERR_COEFF_17*/
{0x00006E40, 16, 5}, /*GAIN_ERR_COEFF_18*/
{0x00006E40, 24, 5}, /*GAIN_ERR_COEFF_19*/
{0x00006E44, 0, 5}, /*GAIN_ERR_COEFF_20*/
{0x00006E48, 0, 10}, /*VOFF_GAIN_0*/
{0x00006E48, 10, 10}, /*VOFF_GAIN_1*/
{0x00006E48, 20, 10}, /*VOFF_GAIN_2*/
{0x00006E4C, 0, 10}, /*VOFF_GAIN_3*/
{0x00006E4C, 10, 10}, /*VOFF_GAIN_4*/
{0x00006E4C, 20, 10}, /*VOFF_GAIN_5*/
{0x00006E50, 0, 10}, /*VOFF_GAIN_6*/
{0x00006E50, 10, 10}, /*VOFF_GAIN_7*/
{0x00006E50, 20, 10}, /*VOFF_GAIN_8*/
{0x00006E54, 0, 10}, /*VOFF_GAIN_9*/
{0x00006E54, 10, 10}, /*VOFF_GAIN_10*/
{0x00006E54, 20, 10}, /*VOFF_GAIN_11*/
{0x00006E58, 0, 10}, /*VOFF_GAIN_12*/
{0x00006E58, 10, 10}, /*VOFF_GAIN_13*/
{0x00006E58, 20, 10}, /*VOFF_GAIN_14*/
{0x00006E5C, 0, 10}, /*VOFF_GAIN_15*/
{0x00006E5C, 10, 10}, /*VOFF_GAIN_16*/
{0x00006E5C, 20, 10}, /*VOFF_GAIN_17*/
{0x00006E60, 0, 10}, /*VOFF_GAIN_18*/
{0x00006E60, 10, 10}, /*VOFF_GAIN_19*/
{0x00006E60, 20, 10}, /*VOFF_GAIN_20*/
{0x00006E64, 0, 10}, /*VOFF_INT1*/
{0x00007418, 7, 5}, /*DS_SPK_INT1_CAP_TRIM*/
{0x0000741C, 0, 5}, /*DS_SPK_INT2_CAP_TRIM*/
{0x0000741C, 11, 4}, /*DS_SPK_LPF_CAP_TRIM*/
{0x0000741C, 19, 4}, /*DS_SPK_QUAN_CAP_TRIM*/
{0x00007434, 17, 1}, /*FORCE_CAL*/
{0x00007434, 18, 7}, /*CAL_OVERRIDE*/
{0x00007068, 0, 9}, /*MODIX*/
{0x0000410C, 7, 1}, /*VIMON_DLY_NOT_COMB*/
{0x0000400C, 0, 7}, /*VIMON_DLY*/
{0x00000000, 0, 1}, /*extra bit*/
{0x00017040, 0, 8}, /*X_COORDINATE*/
{0x00017040, 8, 8}, /*Y_COORDINATE*/
{0x00017040, 16, 8}, /*WAFER_ID*/
{0x00017040, 24, 8}, /*DVS*/
{0x00017044, 0, 24}, /*LOT_NUMBER*/
};
static const struct cs35l41_otp_packed_element_t
otp_map_2[CS35L41_NUM_OTP_ELEM] = {
/* addr shift size */
{0x00002030, 0, 4}, /*TRIM_OSC_FREQ_TRIM*/
{0x00002030, 7, 1}, /*TRIM_OSC_TRIM_DONE*/
{0x0000208c, 24, 6}, /*TST_DIGREG_VREF_TRIM*/
{0x00002090, 14, 4}, /*TST_REF_TRIM*/
{0x00002090, 10, 4}, /*TST_REF_TEMPCO_TRIM*/
{0x0000300C, 11, 4}, /*PLL_LDOA_TST_VREF_TRIM*/
{0x0000394C, 23, 2}, /*BST_ATEST_CM_VOFF*/
{0x00003950, 0, 7}, /*BST_ATRIM_IADC_OFFSET*/
{0x00003950, 8, 7}, /*BST_ATRIM_IADC_GAIN1*/
{0x00003950, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{0x00003950, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN1*/
{0x00003954, 0, 7}, /*BST_ATRIM_IADC_OFFSET2*/
{0x00003954, 8, 7}, /*BST_ATRIM_IADC_GAIN2*/
{0x00003954, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{0x00003954, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN2*/
{0x00003958, 0, 7}, /*BST_ATRIM_IADC_OFFSET3*/
{0x00003958, 8, 7}, /*BST_ATRIM_IADC_GAIN3*/
{0x00003958, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{0x00003958, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN3*/
{0x0000395C, 0, 7}, /*BST_ATRIM_IADC_OFFSET4*/
{0x0000395C, 8, 7}, /*BST_ATRIM_IADC_GAIN4*/
{0x0000395C, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{0x0000395C, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN4*/
{0x0000416C, 0, 8}, /*VMON_GAIN_OTP_VAL*/
{0x00004160, 0, 7}, /*VMON_OFFSET_OTP_VAL*/
{0x0000416C, 8, 8}, /*IMON_GAIN_OTP_VAL*/
{0x00004160, 16, 10}, /*IMON_OFFSET_OTP_VAL*/
{0x0000416C, 16, 12}, /*VMON_CM_GAIN_OTP_VAL*/
{0x0000416C, 28, 1}, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{0x00004170, 0, 6}, /*IMON_CAL_TEMPCO_OTP_VAL*/
{0x00004170, 6, 1}, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{0x00004170, 8, 6}, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{0x00004170, 14, 1}, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{0x00004170, 16, 9}, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{0x00004360, 0, 5}, /*TEMP_GAIN_OTP_VAL*/
{0x00004360, 6, 9}, /*TEMP_OFFSET_OTP_VAL*/
{0x00004448, 0, 8}, /*VP_SARADC_OFFSET*/
{0x00004448, 8, 8}, /*VP_GAIN_INDEX*/
{0x00004448, 16, 8}, /*VBST_SARADC_OFFSET*/
{0x00004448, 24, 8}, /*VBST_GAIN_INDEX*/
{0x0000444C, 0, 3}, /*ANA_SELINVREF*/
{0x00006E30, 0, 5}, /*GAIN_ERR_COEFF_0*/
{0x00006E30, 8, 5}, /*GAIN_ERR_COEFF_1*/
{0x00006E30, 16, 5}, /*GAIN_ERR_COEFF_2*/
{0x00006E30, 24, 5}, /*GAIN_ERR_COEFF_3*/
{0x00006E34, 0, 5}, /*GAIN_ERR_COEFF_4*/
{0x00006E34, 8, 5}, /*GAIN_ERR_COEFF_5*/
{0x00006E34, 16, 5}, /*GAIN_ERR_COEFF_6*/
{0x00006E34, 24, 5}, /*GAIN_ERR_COEFF_7*/
{0x00006E38, 0, 5}, /*GAIN_ERR_COEFF_8*/
{0x00006E38, 8, 5}, /*GAIN_ERR_COEFF_9*/
{0x00006E38, 16, 5}, /*GAIN_ERR_COEFF_10*/
{0x00006E38, 24, 5}, /*GAIN_ERR_COEFF_11*/
{0x00006E3C, 0, 5}, /*GAIN_ERR_COEFF_12*/
{0x00006E3C, 8, 5}, /*GAIN_ERR_COEFF_13*/
{0x00006E3C, 16, 5}, /*GAIN_ERR_COEFF_14*/
{0x00006E3C, 24, 5}, /*GAIN_ERR_COEFF_15*/
{0x00006E40, 0, 5}, /*GAIN_ERR_COEFF_16*/
{0x00006E40, 8, 5}, /*GAIN_ERR_COEFF_17*/
{0x00006E40, 16, 5}, /*GAIN_ERR_COEFF_18*/
{0x00006E40, 24, 5}, /*GAIN_ERR_COEFF_19*/
{0x00006E44, 0, 5}, /*GAIN_ERR_COEFF_20*/
{0x00006E48, 0, 10}, /*VOFF_GAIN_0*/
{0x00006E48, 10, 10}, /*VOFF_GAIN_1*/
{0x00006E48, 20, 10}, /*VOFF_GAIN_2*/
{0x00006E4C, 0, 10}, /*VOFF_GAIN_3*/
{0x00006E4C, 10, 10}, /*VOFF_GAIN_4*/
{0x00006E4C, 20, 10}, /*VOFF_GAIN_5*/
{0x00006E50, 0, 10}, /*VOFF_GAIN_6*/
{0x00006E50, 10, 10}, /*VOFF_GAIN_7*/
{0x00006E50, 20, 10}, /*VOFF_GAIN_8*/
{0x00006E54, 0, 10}, /*VOFF_GAIN_9*/
{0x00006E54, 10, 10}, /*VOFF_GAIN_10*/
{0x00006E54, 20, 10}, /*VOFF_GAIN_11*/
{0x00006E58, 0, 10}, /*VOFF_GAIN_12*/
{0x00006E58, 10, 10}, /*VOFF_GAIN_13*/
{0x00006E58, 20, 10}, /*VOFF_GAIN_14*/
{0x00006E5C, 0, 10}, /*VOFF_GAIN_15*/
{0x00006E5C, 10, 10}, /*VOFF_GAIN_16*/
{0x00006E5C, 20, 10}, /*VOFF_GAIN_17*/
{0x00006E60, 0, 10}, /*VOFF_GAIN_18*/
{0x00006E60, 10, 10}, /*VOFF_GAIN_19*/
{0x00006E60, 20, 10}, /*VOFF_GAIN_20*/
{0x00006E64, 0, 10}, /*VOFF_INT1*/
{0x00007418, 7, 5}, /*DS_SPK_INT1_CAP_TRIM*/
{0x0000741C, 0, 5}, /*DS_SPK_INT2_CAP_TRIM*/
{0x0000741C, 11, 4}, /*DS_SPK_LPF_CAP_TRIM*/
{0x0000741C, 19, 4}, /*DS_SPK_QUAN_CAP_TRIM*/
{0x00007434, 17, 1}, /*FORCE_CAL*/
{0x00007434, 18, 7}, /*CAL_OVERRIDE*/
{0x00007068, 0, 9}, /*MODIX*/
{0x0000410C, 7, 1}, /*VIMON_DLY_NOT_COMB*/
{0x0000400C, 0, 7}, /*VIMON_DLY*/
{0x00004000, 11, 1}, /*VMON_POL*/
{0x00017040, 0, 8}, /*X_COORDINATE*/
{0x00017040, 8, 8}, /*Y_COORDINATE*/
{0x00017040, 16, 8}, /*WAFER_ID*/
{0x00017040, 24, 8}, /*DVS*/
{0x00017044, 0, 24}, /*LOT_NUMBER*/
};
const struct cs35l41_otp_map_element_t
cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS] = {
{
.id = 0x01,
.map = otp_map_1,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x02,
.map = otp_map_2,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x03,
.map = otp_map_2,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x06,
.map = otp_map_2,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
{
.id = 0x08,
.map = otp_map_1,
.num_elements = CS35L41_NUM_OTP_ELEM,
.bit_offset = 16,
.word_offset = 2,
},
};
sound/soc/codecs/cs35l41.c 0 → 100644
View file @ a13a228e
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41.c -- CS35l41 ALSA SoC audio driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <david.rhodes@cirrus.com>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "cs35l41.h"
static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
"VA",
"VP",
};
struct cs35l41_pll_sysclk_config {
int freq;
int clk_cfg;
};
static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
{ 32768, 0x00 },
{ 8000, 0x01 },
{ 11025, 0x02 },
{ 12000, 0x03 },
{ 16000, 0x04 },
{ 22050, 0x05 },
{ 24000, 0x06 },
{ 32000, 0x07 },
{ 44100, 0x08 },
{ 48000, 0x09 },
{ 88200, 0x0A },
{ 96000, 0x0B },
{ 128000, 0x0C },
{ 176400, 0x0D },
{ 192000, 0x0E },
{ 256000, 0x0F },
{ 352800, 0x10 },
{ 384000, 0x11 },
{ 512000, 0x12 },
{ 705600, 0x13 },
{ 750000, 0x14 },
{ 768000, 0x15 },
{ 1000000, 0x16 },
{ 1024000, 0x17 },
{ 1200000, 0x18 },
{ 1411200, 0x19 },
{ 1500000, 0x1A },
{ 1536000, 0x1B },
{ 2000000, 0x1C },
{ 2048000, 0x1D },
{ 2400000, 0x1E },
{ 2822400, 0x1F },
{ 3000000, 0x20 },
{ 3072000, 0x21 },
{ 3200000, 0x22 },
{ 4000000, 0x23 },
{ 4096000, 0x24 },
{ 4800000, 0x25 },
{ 5644800, 0x26 },
{ 6000000, 0x27 },
{ 6144000, 0x28 },
{ 6250000, 0x29 },
{ 6400000, 0x2A },
{ 6500000, 0x2B },
{ 6750000, 0x2C },
{ 7526400, 0x2D },
{ 8000000, 0x2E },
{ 8192000, 0x2F },
{ 9600000, 0x30 },
{ 11289600, 0x31 },
{ 12000000, 0x32 },
{ 12288000, 0x33 },
{ 12500000, 0x34 },
{ 12800000, 0x35 },
{ 13000000, 0x36 },
{ 13500000, 0x37 },
{ 19200000, 0x38 },
{ 22579200, 0x39 },
{ 24000000, 0x3A },
{ 24576000, 0x3B },
{ 25000000, 0x3C },
{ 25600000, 0x3D },
{ 26000000, 0x3E },
{ 27000000, 0x3F },
};
struct cs35l41_fs_mon_config {
int freq;
unsigned int fs1;
unsigned int fs2;
};
static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
{ 32768, 2254, 3754 },
{ 8000, 9220, 15364 },
{ 11025, 6148, 10244 },
{ 12000, 6148, 10244 },
{ 16000, 4612, 7684 },
{ 22050, 3076, 5124 },
{ 24000, 3076, 5124 },
{ 32000, 2308, 3844 },
{ 44100, 1540, 2564 },
{ 48000, 1540, 2564 },
{ 88200, 772, 1284 },
{ 96000, 772, 1284 },
{ 128000, 580, 964 },
{ 176400, 388, 644 },
{ 192000, 388, 644 },
{ 256000, 292, 484 },
{ 352800, 196, 324 },
{ 384000, 196, 324 },
{ 512000, 148, 244 },
{ 705600, 100, 164 },
{ 750000, 100, 164 },
{ 768000, 100, 164 },
{ 1000000, 76, 124 },
{ 1024000, 76, 124 },
{ 1200000, 64, 104 },
{ 1411200, 52, 84 },
{ 1500000, 52, 84 },
{ 1536000, 52, 84 },
{ 2000000, 40, 64 },
{ 2048000, 40, 64 },
{ 2400000, 34, 54 },
{ 2822400, 28, 44 },
{ 3000000, 28, 44 },
{ 3072000, 28, 44 },
{ 3200000, 27, 42 },
{ 4000000, 22, 34 },
{ 4096000, 22, 34 },
{ 4800000, 19, 29 },
{ 5644800, 16, 24 },
{ 6000000, 16, 24 },
{ 6144000, 16, 24 },
};
static const unsigned char cs35l41_bst_k1_table[4][5] = {
{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
{ 0x40, 0x32, 0x32, 0x4F, 0x57 },
{ 0x40, 0x32, 0x32, 0x4F, 0x57 }
};
static const unsigned char cs35l41_bst_k2_table[4][5] = {
{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
{ 0x48, 0x49, 0x66, 0xA3, 0xEA },
{ 0x48, 0x49, 0x66, 0xA3, 0xEA }
};
static const unsigned char cs35l41_bst_slope_table[4] = {
0x75, 0x6B, 0x3B, 0x28};
static int cs35l41_get_fs_mon_config_index(int freq)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
if (cs35l41_fs_mon[i].freq == freq)
return i;
}
return -EINVAL;
}
static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
static const struct snd_kcontrol_new dre_ctrl =
SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
static const char * const cs35l41_pcm_sftramp_text[] = {
"Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
CS35L41_AMP_DIG_VOL_CTRL, 0,
cs35l41_pcm_sftramp_text);
static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
CS35L41_DAC_PCM1_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_pcm_source_texts,
cs35l41_pcm_source_values);
static const struct snd_kcontrol_new pcm_source_mux =
SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
static const char * const cs35l41_tx_input_texts[] = {"Zero", "ASPRX1",
"ASPRX2", "VMON",
"IMON", "VPMON",
"VBSTMON",
"DSPTX1", "DSPTX2"};
static const unsigned int cs35l41_tx_input_values[] = {0x00,
CS35L41_INPUT_SRC_ASPRX1,
CS35L41_INPUT_SRC_ASPRX2,
CS35L41_INPUT_SRC_VMON,
CS35L41_INPUT_SRC_IMON,
CS35L41_INPUT_SRC_VPMON,
CS35L41_INPUT_SRC_VBSTMON,
CS35L41_INPUT_DSP_TX1,
CS35L41_INPUT_DSP_TX2};
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
CS35L41_ASP_TX1_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx1_mux =
SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
CS35L41_ASP_TX2_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx2_mux =
SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
CS35L41_ASP_TX3_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx3_mux =
SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
CS35L41_ASP_TX4_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx4_mux =
SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
3, 0x4CF, 0x391, dig_vol_tlv),
SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
amp_gain_tlv),
SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
SOC_SINGLE("Aux Noise Gate CH1 Enable",
CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
SOC_SINGLE("Aux Noise Gate CH1 Threshold",
CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
SOC_SINGLE("Aux Noise Gate CH2 Enable",
CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
SOC_SINGLE("Aux Noise Gate CH2 Threshold",
CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
SOC_SINGLE("SCLK Force", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
SOC_SINGLE("LRCLK Force", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
SOC_SINGLE("Invert Class D", CS35L41_AMP_DIG_VOL_CTRL,
CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
SOC_SINGLE("Amp Gain ZC", CS35L41_AMP_GAIN_CTRL,
CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
};
static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) {
if (cs35l41_otp_map_map[i].id == otp_id)
return &cs35l41_otp_map_map[i];
}
return NULL;
}
static int cs35l41_otp_unpack(void *data)
{
const struct cs35l41_otp_map_element_t *otp_map_match;
const struct cs35l41_otp_packed_element_t *otp_map;
struct cs35l41_private *cs35l41 = data;
int bit_offset, word_offset, ret, i;
unsigned int orig_spi_freq;
unsigned int bit_sum = 8;
u32 otp_val, otp_id_reg;
u32 *otp_mem;
otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem),
GFP_KERNEL);
if (!otp_mem)
return -ENOMEM;
ret = regmap_read(cs35l41->regmap, CS35L41_OTPID, &otp_id_reg);
if (ret < 0) {
dev_err(cs35l41->dev, "Read OTP ID failed\n");
ret = -EINVAL;
goto err_otp_unpack;
}
otp_map_match = cs35l41_find_otp_map(otp_id_reg);
if (!otp_map_match) {
dev_err(cs35l41->dev, "OTP Map matching ID %d not found\n",
otp_id_reg);
ret = -EINVAL;
goto err_otp_unpack;
}
if (cs35l41->otp_setup)
cs35l41->otp_setup(cs35l41, true, &orig_spi_freq);
ret = regmap_bulk_read(cs35l41->regmap, CS35L41_OTP_MEM0, otp_mem,
CS35L41_OTP_SIZE_WORDS);
if (ret < 0) {
dev_err(cs35l41->dev, "Read OTP Mem failed\n");
ret = -EINVAL;
goto err_otp_unpack;
}
if (cs35l41->otp_setup)
cs35l41->otp_setup(cs35l41, false, &orig_spi_freq);
otp_map = otp_map_match->map;
bit_offset = otp_map_match->bit_offset;
word_offset = otp_map_match->word_offset;
ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000055);
if (ret < 0) {
dev_err(cs35l41->dev, "Write Unlock key failed 1/2\n");
ret = -EINVAL;
goto err_otp_unpack;
}
ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000AA);
if (ret < 0) {
dev_err(cs35l41->dev, "Write Unlock key failed 2/2\n");
ret = -EINVAL;
goto err_otp_unpack;
}
for (i = 0; i < otp_map_match->num_elements; i++) {
dev_dbg(cs35l41->dev,
"bitoffset= %d, word_offset=%d, bit_sum mod 32=%d\n",
bit_offset, word_offset, bit_sum % 32);
if (bit_offset + otp_map[i].size - 1 >= 32) {
otp_val = (otp_mem[word_offset] &
GENMASK(31, bit_offset)) >>
bit_offset;
otp_val |= (otp_mem[++word_offset] &
GENMASK(bit_offset +
otp_map[i].size - 33, 0)) <<
(32 - bit_offset);
bit_offset += otp_map[i].size - 32;
} else {
otp_val = (otp_mem[word_offset] &
GENMASK(bit_offset + otp_map[i].size - 1,
bit_offset)) >> bit_offset;
bit_offset += otp_map[i].size;
}
bit_sum += otp_map[i].size;
if (bit_offset == 32) {
bit_offset = 0;
word_offset++;
}
if (otp_map[i].reg != 0) {
ret = regmap_update_bits(cs35l41->regmap,
otp_map[i].reg,
GENMASK(otp_map[i].shift +
otp_map[i].size - 1,
otp_map[i].shift),
otp_val << otp_map[i].shift);
if (ret < 0) {
dev_err(cs35l41->dev, "Write OTP val failed\n");
ret = -EINVAL;
goto err_otp_unpack;
}
}
}
ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000CC);
if (ret < 0) {
dev_err(cs35l41->dev, "Write Lock key failed 1/2\n");
ret = -EINVAL;
goto err_otp_unpack;
}
ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000033);
if (ret < 0) {
dev_err(cs35l41->dev, "Write Lock key failed 2/2\n");
ret = -EINVAL;
goto err_otp_unpack;
}
ret = 0;
err_otp_unpack:
kfree(otp_mem);
return ret;
}
static irqreturn_t cs35l41_irq(int irq, void *data)
{
struct cs35l41_private *cs35l41 = data;
unsigned int status[4] = { 0, 0, 0, 0 };
unsigned int masks[4] = { 0, 0, 0, 0 };
int ret = IRQ_NONE;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(status); i++) {
regmap_read(cs35l41->regmap,
CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
&status[i]);
regmap_read(cs35l41->regmap,
CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
&masks[i]);
}
/* Check to see if unmasked bits are active */
if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
!(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
return IRQ_NONE;
if (status[3] & CS35L41_OTP_BOOT_DONE) {
regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
}
/*
* The following interrupts require a
* protection release cycle to get the
* speaker out of Safe-Mode.
*/
if (status[0] & CS35L41_AMP_SHORT_ERR) {
dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_AMP_SHORT_ERR);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_AMP_SHORT_ERR_RLS,
CS35L41_AMP_SHORT_ERR_RLS);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_AMP_SHORT_ERR_RLS, 0);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_TEMP_WARN) {
dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_TEMP_WARN);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_TEMP_WARN_ERR_RLS,
CS35L41_TEMP_WARN_ERR_RLS);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_TEMP_WARN_ERR_RLS, 0);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_TEMP_ERR) {
dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_TEMP_ERR);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_TEMP_ERR_RLS,
CS35L41_TEMP_ERR_RLS);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_TEMP_ERR_RLS, 0);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_BST_OVP_ERR) {
dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK, 0);
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_BST_OVP_ERR);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_BST_OVP_ERR_RLS,
CS35L41_BST_OVP_ERR_RLS);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_BST_OVP_ERR_RLS, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT <<
CS35L41_BST_EN_SHIFT);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK, 0);
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_BST_DCM_UVP_ERR);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_BST_UVP_ERR_RLS,
CS35L41_BST_UVP_ERR_RLS);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_BST_UVP_ERR_RLS, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT <<
CS35L41_BST_EN_SHIFT);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_BST_SHORT_ERR) {
dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK, 0);
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_BST_SHORT_ERR);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_BST_SHORT_ERR_RLS,
CS35L41_BST_SHORT_ERR_RLS);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
CS35L41_BST_SHORT_ERR_RLS, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT <<
CS35L41_BST_EN_SHIFT);
ret = IRQ_HANDLED;
}
return ret;
}
static const struct reg_sequence cs35l41_pup_patch[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x00002084, 0x002F1AA0 },
{ 0x00000040, 0x000000CC },
{ 0x00000040, 0x00000033 },
};
static const struct reg_sequence cs35l41_pdn_patch[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x00002084, 0x002F1AA3 },
{ 0x00000040, 0x000000CC },
{ 0x00000040, 0x00000033 },
};
static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(component);
unsigned int val;
int ret = 0;
bool pdn;
int i;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_multi_reg_write_bypassed(cs35l41->regmap,
cs35l41_pup_patch,
ARRAY_SIZE(cs35l41_pup_patch));
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1,
CS35L41_GLOBAL_EN_MASK,
1 << CS35L41_GLOBAL_EN_SHIFT);
usleep_range(1000, 1100);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1,
CS35L41_GLOBAL_EN_MASK, 0);
pdn = false;
for (i = 0; i < 100; i++) {
regmap_read(cs35l41->regmap,
CS35L41_IRQ1_STATUS1,
&val);
if (val & CS35L41_PDN_DONE_MASK) {
pdn = true;
break;
}
usleep_range(1000, 1100);
}
if (!pdn)
dev_warn(cs35l41->dev, "PDN failed\n");
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
CS35L41_PDN_DONE_MASK);
regmap_multi_reg_write_bypassed(cs35l41->regmap,
cs35l41_pdn_patch,
ARRAY_SIZE(cs35l41_pdn_patch));
break;
default:
dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
ret = -EINVAL;
}
return ret;
}
static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L41_PWR_CTRL2, 12, 0),
SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L41_PWR_CTRL2, 13, 0),
SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L41_PWR_CTRL2, 8, 0),
SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L41_PWR_CTRL2, 9, 0),
SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, CS35L41_PWR_CTRL2, 10, 0),
SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
cs35l41_main_amp_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_INPUT("VP"),
SND_SOC_DAPM_INPUT("VBST"),
SND_SOC_DAPM_INPUT("ISENSE"),
SND_SOC_DAPM_INPUT("VSENSE"),
SND_SOC_DAPM_INPUT("TEMP"),
SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
};
static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
{"ASP TX1 Source", "VMON", "VMON ADC"},
{"ASP TX1 Source", "IMON", "IMON ADC"},
{"ASP TX1 Source", "VPMON", "VPMON ADC"},
{"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX1 Source", "ASPRX1", "ASPRX1" },
{"ASP TX1 Source", "ASPRX2", "ASPRX2" },
{"ASP TX2 Source", "VMON", "VMON ADC"},
{"ASP TX2 Source", "IMON", "IMON ADC"},
{"ASP TX2 Source", "VPMON", "VPMON ADC"},
{"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX2 Source", "ASPRX1", "ASPRX1" },
{"ASP TX2 Source", "ASPRX2", "ASPRX2" },
{"ASP TX3 Source", "VMON", "VMON ADC"},
{"ASP TX3 Source", "IMON", "IMON ADC"},
{"ASP TX3 Source", "VPMON", "VPMON ADC"},
{"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX3 Source", "ASPRX1", "ASPRX1" },
{"ASP TX3 Source", "ASPRX2", "ASPRX2" },
{"ASP TX4 Source", "VMON", "VMON ADC"},
{"ASP TX4 Source", "IMON", "IMON ADC"},
{"ASP TX4 Source", "VPMON", "VPMON ADC"},
{"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX4 Source", "ASPRX1", "ASPRX1" },
{"ASP TX4 Source", "ASPRX2", "ASPRX2" },
{"ASPTX1", NULL, "ASP TX1 Source"},
{"ASPTX2", NULL, "ASP TX2 Source"},
{"ASPTX3", NULL, "ASP TX3 Source"},
{"ASPTX4", NULL, "ASP TX4 Source"},
{"AMP Capture", NULL, "ASPTX1"},
{"AMP Capture", NULL, "ASPTX2"},
{"AMP Capture", NULL, "ASPTX3"},
{"AMP Capture", NULL, "ASPTX4"},
{"VMON ADC", NULL, "VSENSE"},
{"IMON ADC", NULL, "ISENSE"},
{"VPMON ADC", NULL, "VP"},
{"TEMPMON ADC", NULL, "TEMP"},
{"VBSTMON ADC", NULL, "VBST"},
{"ASPRX1", NULL, "AMP Playback"},
{"ASPRX2", NULL, "AMP Playback"},
{"DRE", "Switch", "CLASS H"},
{"Main AMP", NULL, "CLASS H"},
{"Main AMP", NULL, "DRE"},
{"SPK", NULL, "Main AMP"},
{"PCM Source", "ASP", "ASPRX1"},
{"CLASS H", NULL, "PCM Source"},
};
static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num,
unsigned int *tx_slot, unsigned int rx_num,
unsigned int *rx_slot)
{
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(dai->component);
int i;
if (tx_num > 4 || rx_num > 2)
return -EINVAL;
for (i = 0; i < rx_num; i++) {
dev_dbg(cs35l41->dev, "%s: rx slot %d position = %d\n",
__func__, i, rx_slot[i]);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT,
0x3F << (i * 8), rx_slot[i] << (i * 8));
}
for (i = 0; i < tx_num; i++) {
dev_dbg(cs35l41->dev, "%s: tx slot %d position = %d\n",
__func__, i, tx_slot[i]);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FRAME_TX_SLOT,
0x3F << (i * 8), tx_slot[i] << (i * 8));
}
return 0;
}
static int cs35l41_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(codec_dai->component);
unsigned int asp_fmt, lrclk_fmt, sclk_fmt, clock_provider;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
clock_provider = 1;
break;
case SND_SOC_DAIFMT_CBC_CFC:
clock_provider = 0;
break;
default:
dev_warn(cs35l41->dev,
"%s: Mixed provider/consumer mode unsupported\n",
__func__);
return -EINVAL;
}
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_SCLK_MSTR_MASK,
clock_provider << CS35L41_SCLK_MSTR_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_LRCLK_MSTR_MASK,
clock_provider << CS35L41_LRCLK_MSTR_SHIFT);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
asp_fmt = 0;
break;
case SND_SOC_DAIFMT_I2S:
asp_fmt = 2;
break;
default:
dev_warn(cs35l41->dev,
"%s: Invalid or unsupported DAI format\n", __func__);
return -EINVAL;
}
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_ASP_FMT_MASK,
asp_fmt << CS35L41_ASP_FMT_SHIFT);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
lrclk_fmt = 1;
sclk_fmt = 0;
break;
case SND_SOC_DAIFMT_IB_NF:
lrclk_fmt = 0;
sclk_fmt = 1;
break;
case SND_SOC_DAIFMT_IB_IF:
lrclk_fmt = 1;
sclk_fmt = 1;
break;
case SND_SOC_DAIFMT_NB_NF:
lrclk_fmt = 0;
sclk_fmt = 0;
break;
default:
dev_warn(cs35l41->dev,
"%s: Invalid DAI clock INV\n", __func__);
return -EINVAL;
}
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_LRCLK_INV_MASK,
lrclk_fmt << CS35L41_LRCLK_INV_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_SCLK_INV_MASK,
sclk_fmt << CS35L41_SCLK_INV_SHIFT);
return 0;
}
struct cs35l41_global_fs_config {
int rate;
int fs_cfg;
};
static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
{ 12000, 0x01 },
{ 24000, 0x02 },
{ 48000, 0x03 },
{ 96000, 0x04 },
{ 192000, 0x05 },
{ 11025, 0x09 },
{ 22050, 0x0A },
{ 44100, 0x0B },
{ 88200, 0x0C },
{ 176400, 0x0D },
{ 8000, 0x11 },
{ 16000, 0x12 },
{ 32000, 0x13 },
};
static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(dai->component);
unsigned int rate = params_rate(params);
u8 asp_wl;
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
if (rate == cs35l41_fs_rates[i].rate)
break;
}
if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
dev_err(cs35l41->dev, "%s: Unsupported rate: %u\n",
__func__, rate);
return -EINVAL;
}
asp_wl = params_width(params);
if (i < ARRAY_SIZE(cs35l41_fs_rates))
regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
CS35L41_GLOBAL_FS_MASK,
cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_ASP_WIDTH_RX_MASK,
asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
CS35L41_ASP_RX_WL_MASK,
asp_wl << CS35L41_ASP_RX_WL_SHIFT);
} else {
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_ASP_WIDTH_TX_MASK,
asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
CS35L41_ASP_TX_WL_MASK,
asp_wl << CS35L41_ASP_TX_WL_SHIFT);
}
return 0;
}
static int cs35l41_get_clk_config(int freq)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
if (cs35l41_pll_sysclk[i].freq == freq)
return cs35l41_pll_sysclk[i].clk_cfg;
}
return -EINVAL;
}
static const unsigned int cs35l41_src_rates[] = {
8000, 12000, 11025, 16000, 22050, 24000, 32000,
44100, 48000, 88200, 96000, 176400, 192000
};
static const struct snd_pcm_hw_constraint_list cs35l41_constraints = {
.count = ARRAY_SIZE(cs35l41_src_rates),
.list = cs35l41_src_rates,
};
static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (substream->runtime)
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cs35l41_constraints);
return 0;
}
static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq,
int dir)
{
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(component);
int extclk_cfg, clksrc;
switch (clk_id) {
case CS35L41_CLKID_SCLK:
clksrc = CS35L41_PLLSRC_SCLK;
break;
case CS35L41_CLKID_LRCLK:
clksrc = CS35L41_PLLSRC_LRCLK;
break;
case CS35L41_CLKID_MCLK:
clksrc = CS35L41_PLLSRC_MCLK;
break;
default:
dev_err(cs35l41->dev, "Invalid CLK Config\n");
return -EINVAL;
}
extclk_cfg = cs35l41_get_clk_config(freq);
if (extclk_cfg < 0) {
dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
extclk_cfg, freq);
return -EINVAL;
}
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_OPENLOOP_MASK,
1 << CS35L41_PLL_OPENLOOP_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_REFCLK_FREQ_MASK,
extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_CLK_EN_MASK,
0 << CS35L41_PLL_CLK_EN_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_CLK_SEL_MASK, clksrc);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_OPENLOOP_MASK,
0 << CS35L41_PLL_OPENLOOP_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_CLK_EN_MASK,
1 << CS35L41_PLL_CLK_EN_SHIFT);
return 0;
}
static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(dai->component);
unsigned int fs1_val;
unsigned int fs2_val;
unsigned int val;
int fsIndex;
fsIndex = cs35l41_get_fs_mon_config_index(freq);
if (fsIndex < 0) {
dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
return -EINVAL;
}
dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
if (freq <= 6144000) {
/* Use the lookup table */
fs1_val = cs35l41_fs_mon[fsIndex].fs1;
fs2_val = cs35l41_fs_mon[fsIndex].fs2;
} else {
/* Use hard-coded values */
fs1_val = 0x10;
fs2_val = 0x24;
}
val = fs1_val;
val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
return 0;
}
static int cs35l41_boost_config(struct cs35l41_private *cs35l41,
int boost_ind, int boost_cap, int boost_ipk)
{
unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled;
struct regmap *regmap = cs35l41->regmap;
struct device *dev = cs35l41->dev;
int ret;
switch (boost_ind) {
case 1000: /* 1.0 uH */
bst_lbst_val = 0;
break;
case 1200: /* 1.2 uH */
bst_lbst_val = 1;
break;
case 1500: /* 1.5 uH */
bst_lbst_val = 2;
break;
case 2200: /* 2.2 uH */
bst_lbst_val = 3;
break;
default:
dev_err(dev, "Invalid boost inductor value: %d nH\n",
boost_ind);
return -EINVAL;
}
switch (boost_cap) {
case 0 ... 19:
bst_cbst_range = 0;
break;
case 20 ... 50:
bst_cbst_range = 1;
break;
case 51 ... 100:
bst_cbst_range = 2;
break;
case 101 ... 200:
bst_cbst_range = 3;
break;
default: /* 201 uF and greater */
bst_cbst_range = 4;
}
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF,
CS35L41_BST_K1_MASK,
cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range]
<< CS35L41_BST_K1_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost K1 coefficient\n");
return ret;
}
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF,
CS35L41_BST_K2_MASK,
cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range]
<< CS35L41_BST_K2_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost K2 coefficient\n");
return ret;
}
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST,
CS35L41_BST_SLOPE_MASK,
cs35l41_bst_slope_table[bst_lbst_val]
<< CS35L41_BST_SLOPE_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost slope coefficient\n");
return ret;
}
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST,
CS35L41_BST_LBST_VAL_MASK,
bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost inductor value\n");
return ret;
}
if ((boost_ipk < 1600) || (boost_ipk > 4500)) {
dev_err(dev, "Invalid boost inductor peak current: %d mA\n",
boost_ipk);
return -EINVAL;
}
bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10;
ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR,
CS35L41_BST_IPK_MASK,
bst_ipk_scaled << CS35L41_BST_IPK_SHIFT);
if (ret) {
dev_err(dev, "Failed to write boost inductor peak current\n");
return ret;
}
return 0;
}
static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
{
int ret;
/* Set Platform Data */
/* Required */
if (cs35l41->pdata.bst_ipk &&
cs35l41->pdata.bst_ind && cs35l41->pdata.bst_cap) {
ret = cs35l41_boost_config(cs35l41, cs35l41->pdata.bst_ind,
cs35l41->pdata.bst_cap,
cs35l41->pdata.bst_ipk);
if (ret) {
dev_err(cs35l41->dev, "Error in Boost DT config\n");
return ret;
}
} else {
dev_err(cs35l41->dev, "Incomplete Boost component DT config\n");
return -EINVAL;
}
/* Optional */
if (cs35l41->pdata.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK &&
cs35l41->pdata.dout_hiz >= 0)
regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL,
CS35L41_ASP_DOUT_HIZ_MASK,
cs35l41->pdata.dout_hiz);
return 0;
}
static int cs35l41_irq_gpio_config(struct cs35l41_private *cs35l41)
{
struct cs35l41_irq_cfg *irq_gpio_cfg1 = &cs35l41->pdata.irq_config1;
struct cs35l41_irq_cfg *irq_gpio_cfg2 = &cs35l41->pdata.irq_config2;
int irq_pol = IRQF_TRIGGER_NONE;
if (irq_gpio_cfg1->irq_pol_inv)
regmap_update_bits(cs35l41->regmap,
CS35L41_GPIO1_CTRL1,
CS35L41_GPIO_POL_MASK,
CS35L41_GPIO_POL_MASK);
if (irq_gpio_cfg1->irq_out_en)
regmap_update_bits(cs35l41->regmap,
CS35L41_GPIO1_CTRL1,
CS35L41_GPIO_DIR_MASK,
0);
if (irq_gpio_cfg1->irq_src_sel)
regmap_update_bits(cs35l41->regmap,
CS35L41_GPIO_PAD_CONTROL,
CS35L41_GPIO1_CTRL_MASK,
irq_gpio_cfg1->irq_src_sel <<
CS35L41_GPIO1_CTRL_SHIFT);
if (irq_gpio_cfg2->irq_pol_inv)
regmap_update_bits(cs35l41->regmap,
CS35L41_GPIO2_CTRL1,
CS35L41_GPIO_POL_MASK,
CS35L41_GPIO_POL_MASK);
if (irq_gpio_cfg2->irq_out_en)
regmap_update_bits(cs35l41->regmap,
CS35L41_GPIO2_CTRL1,
CS35L41_GPIO_DIR_MASK,
0);
if (irq_gpio_cfg2->irq_src_sel)
regmap_update_bits(cs35l41->regmap,
CS35L41_GPIO_PAD_CONTROL,
CS35L41_GPIO2_CTRL_MASK,
irq_gpio_cfg2->irq_src_sel <<
CS35L41_GPIO2_CTRL_SHIFT);
if ((irq_gpio_cfg2->irq_src_sel ==
(CS35L41_GPIO_CTRL_ACTV_LO | CS35L41_VALID_PDATA)) ||
(irq_gpio_cfg2->irq_src_sel ==
(CS35L41_GPIO_CTRL_OPEN_INT | CS35L41_VALID_PDATA)))
irq_pol = IRQF_TRIGGER_LOW;
else if (irq_gpio_cfg2->irq_src_sel ==
(CS35L41_GPIO_CTRL_ACTV_HI | CS35L41_VALID_PDATA))
irq_pol = IRQF_TRIGGER_HIGH;
return irq_pol;
}
static const struct snd_soc_dai_ops cs35l41_ops = {
.startup = cs35l41_pcm_startup,
.set_fmt = cs35l41_set_dai_fmt,
.hw_params = cs35l41_pcm_hw_params,
.set_sysclk = cs35l41_dai_set_sysclk,
.set_channel_map = cs35l41_set_channel_map,
};
static struct snd_soc_dai_driver cs35l41_dai[] = {
{
.name = "cs35l41-pcm",
.id = 0,
.playback = {
.stream_name = "AMP Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L41_RX_FORMATS,
},
.capture = {
.stream_name = "AMP Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L41_TX_FORMATS,
},
.ops = &cs35l41_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
.name = "cs35l41-codec",
.dapm_widgets = cs35l41_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
.dapm_routes = cs35l41_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
.controls = cs35l41_aud_controls,
.num_controls = ARRAY_SIZE(cs35l41_aud_controls),
.set_sysclk = cs35l41_component_set_sysclk,
};
static int cs35l41_handle_pdata(struct device *dev,
struct cs35l41_platform_data *pdata,
struct cs35l41_private *cs35l41)
{
struct cs35l41_irq_cfg *irq_gpio1_config = &pdata->irq_config1;
struct cs35l41_irq_cfg *irq_gpio2_config = &pdata->irq_config2;
unsigned int val;
int ret;
ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
if (ret >= 0)
pdata->bst_ipk = val;
ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
if (ret >= 0)
pdata->bst_ind = val;
ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
if (ret >= 0)
pdata->bst_cap = val;
ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
if (ret >= 0)
pdata->dout_hiz = val;
else
pdata->dout_hiz = -1;
/* GPIO1 Pin Config */
irq_gpio1_config->irq_pol_inv = device_property_read_bool(dev,
"cirrus,gpio1-polarity-invert");
irq_gpio1_config->irq_out_en = device_property_read_bool(dev,
"cirrus,gpio1-output-enable");
ret = device_property_read_u32(dev, "cirrus,gpio1-src-select",
&val);
if (ret >= 0) {
val |= CS35L41_VALID_PDATA;
irq_gpio1_config->irq_src_sel = val;
}
/* GPIO2 Pin Config */
irq_gpio2_config->irq_pol_inv = device_property_read_bool(dev,
"cirrus,gpio2-polarity-invert");
irq_gpio2_config->irq_out_en = device_property_read_bool(dev,
"cirrus,gpio2-output-enable");
ret = device_property_read_u32(dev, "cirrus,gpio2-src-select",
&val);
if (ret >= 0) {
val |= CS35L41_VALID_PDATA;
irq_gpio2_config->irq_src_sel = val;
}
return 0;
}
static const struct reg_sequence cs35l41_reva0_errata_patch[] = {
{ 0x00000040, 0x00005555 },
{ 0x00000040, 0x0000AAAA },
{ 0x00003854, 0x05180240 },
{ CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
{ 0x00004310, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000000 },
{ CS35L41_OTP_TRIM_30, 0x9091A1C8 },
{ 0x00003014, 0x0200EE0E },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
{ 0x00000054, 0x00000004 },
{ CS35L41_IRQ1_DB3, 0x00000000 },
{ CS35L41_IRQ2_DB3, 0x00000000 },
{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ 0x00000040, 0x0000CCCC },
{ 0x00000040, 0x00003333 },
};
static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
{ 0x00000040, 0x00005555 },
{ 0x00000040, 0x0000AAAA },
{ CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
{ 0x00004310, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000000 },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ 0x00000040, 0x0000CCCC },
{ 0x00000040, 0x00003333 },
};
static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
{ 0x00000040, 0x00005555 },
{ 0x00000040, 0x0000AAAA },
{ CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
{ 0x00004310, 0x00000000 },
{ CS35L41_VPVBST_FS_SEL, 0x00000000 },
{ CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ 0x00000040, 0x0000CCCC },
{ 0x00000040, 0x00003333 },
};
int cs35l41_probe(struct cs35l41_private *cs35l41,
struct cs35l41_platform_data *pdata)
{
u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
int irq_pol = 0;
int timeout;
int ret;
if (pdata) {
cs35l41->pdata = *pdata;
} else {
ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->pdata,
cs35l41);
if (ret != 0)
return ret;
}
for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
cs35l41->supplies[i].supply = cs35l41_supplies[i];
ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
cs35l41->supplies);
if (ret != 0) {
dev_err(cs35l41->dev,
"Failed to request core supplies: %d\n",
ret);
return ret;
}
ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
if (ret != 0) {
dev_err(cs35l41->dev,
"Failed to enable core supplies: %d\n", ret);
return ret;
}
/* returning NULL can be an option if in stereo mode */
cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs35l41->reset_gpio)) {
ret = PTR_ERR(cs35l41->reset_gpio);
cs35l41->reset_gpio = NULL;
if (ret == -EBUSY) {
dev_info(cs35l41->dev,
"Reset line busy, assuming shared reset\n");
} else {
dev_err(cs35l41->dev,
"Failed to get reset GPIO: %d\n", ret);
goto err;
}
}
if (cs35l41->reset_gpio) {
/* satisfy minimum reset pulse width spec */
usleep_range(2000, 2100);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
}
usleep_range(2000, 2100);
timeout = 100;
do {
if (timeout == 0) {
dev_err(cs35l41->dev,
"Timeout waiting for OTP_BOOT_DONE\n");
ret = -EBUSY;
goto err;
}
usleep_range(1000, 1100);
regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS4, &int_status);
timeout--;
} while (!(int_status & CS35L41_OTP_BOOT_DONE));
regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
if (int_status & CS35L41_OTP_BOOT_ERR) {
dev_err(cs35l41->dev, "OTP Boot error\n");
ret = -EINVAL;
goto err;
}
ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, &regid);
if (ret < 0) {
dev_err(cs35l41->dev, "Get Device ID failed\n");
goto err;
}
ret = regmap_read(cs35l41->regmap, CS35L41_REVID, &reg_revid);
if (ret < 0) {
dev_err(cs35l41->dev, "Get Revision ID failed\n");
goto err;
}
mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
/* CS35L41 will have even MTLREVID
* CS35L41R will have odd MTLREVID
*/
chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
if (regid != chipid_match) {
dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
regid, chipid_match);
ret = -ENODEV;
goto err;
}
switch (reg_revid) {
case CS35L41_REVID_A0:
ret = regmap_register_patch(cs35l41->regmap,
cs35l41_reva0_errata_patch,
ARRAY_SIZE(cs35l41_reva0_errata_patch));
if (ret < 0) {
dev_err(cs35l41->dev,
"Failed to apply A0 errata patch %d\n", ret);
goto err;
}
break;
case CS35L41_REVID_B0:
ret = regmap_register_patch(cs35l41->regmap,
cs35l41_revb0_errata_patch,
ARRAY_SIZE(cs35l41_revb0_errata_patch));
if (ret < 0) {
dev_err(cs35l41->dev,
"Failed to apply B0 errata patch %d\n", ret);
goto err;
}
break;
case CS35L41_REVID_B2:
ret = regmap_register_patch(cs35l41->regmap,
cs35l41_revb2_errata_patch,
ARRAY_SIZE(cs35l41_revb2_errata_patch));
if (ret < 0) {
dev_err(cs35l41->dev,
"Failed to apply B2 errata patch %d\n", ret);
goto err;
}
break;
}
irq_pol = cs35l41_irq_gpio_config(cs35l41);
/* Set interrupt masks for critical errors */
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
CS35L41_INT1_MASK_DEFAULT);
ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL,
cs35l41_irq, IRQF_ONESHOT | IRQF_SHARED | irq_pol,
"cs35l41", cs35l41);
/* CS35L41 needs INT for PDN_DONE */
if (ret != 0) {
dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
ret = -ENODEV;
goto err;
}
ret = cs35l41_otp_unpack(cs35l41);
if (ret < 0) {
dev_err(cs35l41->dev, "OTP Unpack failed\n");
goto err;
}
ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_CCM_CORE_CTRL, 0);
if (ret < 0) {
dev_err(cs35l41->dev, "Write CCM_CORE_CTRL failed\n");
goto err;
}
ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_AMP_EN_MASK, 0);
if (ret < 0) {
dev_err(cs35l41->dev, "Write CS35L41_PWR_CTRL2 failed\n");
goto err;
}
ret = regmap_update_bits(cs35l41->regmap, CS35L41_AMP_GAIN_CTRL,
CS35L41_AMP_GAIN_PCM_MASK, 0);
if (ret < 0) {
dev_err(cs35l41->dev, "Write CS35L41_AMP_GAIN_CTRL failed\n");
goto err;
}
ret = cs35l41_set_pdata(cs35l41);
if (ret < 0) {
dev_err(cs35l41->dev, "%s: Set pdata failed\n", __func__);
goto err;
}
ret = devm_snd_soc_register_component(cs35l41->dev,
&soc_component_dev_cs35l41,
cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
if (ret < 0) {
dev_err(cs35l41->dev, "%s: Register codec failed\n", __func__);
goto err;
}
dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
regid, reg_revid);
return 0;
err:
regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
return ret;
}
int cs35l41_remove(struct cs35l41_private *cs35l41)
{
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
return 0;
}
MODULE_DESCRIPTION("ASoC CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/cs35l41.h 0 → 100644
View file @ a13a228e
/* SPDX-License-Identifier: GPL-2.0
*
* cs35l41.h -- CS35L41 ALSA SoC audio driver
*
* Copyright 2017-2021 Cirrus Logic, Inc.
*
* Author: David Rhodes <david.rhodes@cirrus.com>
*/
#ifndef __CS35L41_H__
#define __CS35L41_H__
#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/cs35l41.h>
#define CS35L41_FIRSTREG 0x00000000
#define CS35L41_LASTREG 0x03804FE8
#define CS35L41_DEVID 0x00000000
#define CS35L41_REVID 0x00000004
#define CS35L41_FABID 0x00000008
#define CS35L41_RELID 0x0000000C
#define CS35L41_OTPID 0x00000010
#define CS35L41_SFT_RESET 0x00000020
#define CS35L41_TEST_KEY_CTL 0x00000040
#define CS35L41_USER_KEY_CTL 0x00000044
#define CS35L41_OTP_MEM0 0x00000400
#define CS35L41_OTP_MEM31 0x0000047C
#define CS35L41_OTP_CTRL0 0x00000500
#define CS35L41_OTP_CTRL1 0x00000504
#define CS35L41_OTP_CTRL3 0x00000508
#define CS35L41_OTP_CTRL4 0x0000050C
#define CS35L41_OTP_CTRL5 0x00000510
#define CS35L41_OTP_CTRL6 0x00000514
#define CS35L41_OTP_CTRL7 0x00000518
#define CS35L41_OTP_CTRL8 0x0000051C
#define CS35L41_PWR_CTRL1 0x00002014
#define CS35L41_PWR_CTRL2 0x00002018
#define CS35L41_PWR_CTRL3 0x0000201C
#define CS35L41_CTRL_OVRRIDE 0x00002020
#define CS35L41_AMP_OUT_MUTE 0x00002024
#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034
#define CS35L41_GPIO_PAD_CONTROL 0x0000242C
#define CS35L41_JTAG_CONTROL 0x00002438
#define CS35L41_PLL_CLK_CTRL 0x00002C04
#define CS35L41_DSP_CLK_CTRL 0x00002C08
#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C
#define CS35L41_DATA_FS_SEL 0x00002C10
#define CS35L41_TST_FS_MON0 0x00002D10
#define CS35L41_MDSYNC_EN 0x00003400
#define CS35L41_MDSYNC_TX_ID 0x00003408
#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C
#define CS35L41_MDSYNC_DATA_TX 0x00003410
#define CS35L41_MDSYNC_TX_STATUS 0x00003414
#define CS35L41_MDSYNC_DATA_RX 0x0000341C
#define CS35L41_MDSYNC_RX_STATUS 0x00003420
#define CS35L41_MDSYNC_ERR_STATUS 0x00003424
#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528
#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C
#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C
#define CS35L41_BSTCVRT_VCTRL1 0x00003800
#define CS35L41_BSTCVRT_VCTRL2 0x00003804
#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808
#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C
#define CS35L41_BSTCVRT_COEFF 0x00003810
#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814
#define CS35L41_BSTCVRT_SW_FREQ 0x00003818
#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C
#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820
#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830
#define CS35L41_VI_VOL_POL 0x00004000
#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100
#define CS35L41_DTEMP_WARN_THLD 0x00004220
#define CS35L41_DTEMP_CFG 0x00004224
#define CS35L41_DTEMP_EN 0x00004308
#define CS35L41_VPVBST_FS_SEL 0x00004400
#define CS35L41_SP_ENABLES 0x00004800
#define CS35L41_SP_RATE_CTRL 0x00004804
#define CS35L41_SP_FORMAT 0x00004808
#define CS35L41_SP_HIZ_CTRL 0x0000480C
#define CS35L41_SP_FRAME_TX_SLOT 0x00004810
#define CS35L41_SP_FRAME_RX_SLOT 0x00004820
#define CS35L41_SP_TX_WL 0x00004830
#define CS35L41_SP_RX_WL 0x00004840
#define CS35L41_ASP_CONTROL4 0x00004854
#define CS35L41_DAC_PCM1_SRC 0x00004C00
#define CS35L41_ASP_TX1_SRC 0x00004C20
#define CS35L41_ASP_TX2_SRC 0x00004C24
#define CS35L41_ASP_TX3_SRC 0x00004C28
#define CS35L41_ASP_TX4_SRC 0x00004C2C
#define CS35L41_DSP1_RX1_SRC 0x00004C40
#define CS35L41_DSP1_RX2_SRC 0x00004C44
#define CS35L41_DSP1_RX3_SRC 0x00004C48
#define CS35L41_DSP1_RX4_SRC 0x00004C4C
#define CS35L41_DSP1_RX5_SRC 0x00004C50
#define CS35L41_DSP1_RX6_SRC 0x00004C54
#define CS35L41_DSP1_RX7_SRC 0x00004C58
#define CS35L41_DSP1_RX8_SRC 0x00004C5C
#define CS35L41_NGATE1_SRC 0x00004C60
#define CS35L41_NGATE2_SRC 0x00004C64
#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000
#define CS35L41_VPBR_CFG 0x00006404
#define CS35L41_VBBR_CFG 0x00006408
#define CS35L41_VPBR_STATUS 0x0000640C
#define CS35L41_VBBR_STATUS 0x00006410
#define CS35L41_OVERTEMP_CFG 0x00006414
#define CS35L41_AMP_ERR_VOL 0x00006418
#define CS35L41_VOL_STATUS_TO_DSP 0x00006450
#define CS35L41_CLASSH_CFG 0x00006800
#define CS35L41_WKFET_CFG 0x00006804
#define CS35L41_NG_CFG 0x00006808
#define CS35L41_AMP_GAIN_CTRL 0x00006C04
#define CS35L41_DAC_MSM_CFG 0x00007400
#define CS35L41_IRQ1_CFG 0x00010000
#define CS35L41_IRQ1_STATUS 0x00010004
#define CS35L41_IRQ1_STATUS1 0x00010010
#define CS35L41_IRQ1_STATUS2 0x00010014
#define CS35L41_IRQ1_STATUS3 0x00010018
#define CS35L41_IRQ1_STATUS4 0x0001001C
#define CS35L41_IRQ1_RAW_STATUS1 0x00010090
#define CS35L41_IRQ1_RAW_STATUS2 0x00010094
#define CS35L41_IRQ1_RAW_STATUS3 0x00010098
#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C
#define CS35L41_IRQ1_MASK1 0x00010110
#define CS35L41_IRQ1_MASK2 0x00010114
#define CS35L41_IRQ1_MASK3 0x00010118
#define CS35L41_IRQ1_MASK4 0x0001011C
#define CS35L41_IRQ1_FRC1 0x00010190
#define CS35L41_IRQ1_FRC2 0x00010194
#define CS35L41_IRQ1_FRC3 0x00010198
#define CS35L41_IRQ1_FRC4 0x0001019C
#define CS35L41_IRQ1_EDGE1 0x00010210
#define CS35L41_IRQ1_EDGE4 0x0001021C
#define CS35L41_IRQ1_POL1 0x00010290
#define CS35L41_IRQ1_POL2 0x00010294
#define CS35L41_IRQ1_POL3 0x00010298
#define CS35L41_IRQ1_POL4 0x0001029C
#define CS35L41_IRQ1_DB3 0x00010318
#define CS35L41_IRQ2_CFG 0x00010800
#define CS35L41_IRQ2_STATUS 0x00010804
#define CS35L41_IRQ2_STATUS1 0x00010810
#define CS35L41_IRQ2_STATUS2 0x00010814
#define CS35L41_IRQ2_STATUS3 0x00010818
#define CS35L41_IRQ2_STATUS4 0x0001081C
#define CS35L41_IRQ2_RAW_STATUS1 0x00010890
#define CS35L41_IRQ2_RAW_STATUS2 0x00010894
#define CS35L41_IRQ2_RAW_STATUS3 0x00010898
#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C
#define CS35L41_IRQ2_MASK1 0x00010910
#define CS35L41_IRQ2_MASK2 0x00010914
#define CS35L41_IRQ2_MASK3 0x00010918
#define CS35L41_IRQ2_MASK4 0x0001091C
#define CS35L41_IRQ2_FRC1 0x00010990
#define CS35L41_IRQ2_FRC2 0x00010994
#define CS35L41_IRQ2_FRC3 0x00010998
#define CS35L41_IRQ2_FRC4 0x0001099C
#define CS35L41_IRQ2_EDGE1 0x00010A10
#define CS35L41_IRQ2_EDGE4 0x00010A1C
#define CS35L41_IRQ2_POL1 0x00010A90
#define CS35L41_IRQ2_POL2 0x00010A94
#define CS35L41_IRQ2_POL3 0x00010A98
#define CS35L41_IRQ2_POL4 0x00010A9C
#define CS35L41_IRQ2_DB3 0x00010B18
#define CS35L41_GPIO_STATUS1 0x00011000
#define CS35L41_GPIO1_CTRL1 0x00011008
#define CS35L41_GPIO2_CTRL1 0x0001100C
#define CS35L41_MIXER_NGATE_CFG 0x00012000
#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004
#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008
#define CS35L41_DSP_MBOX_1 0x00013000
#define CS35L41_DSP_MBOX_2 0x00013004
#define CS35L41_DSP_MBOX_3 0x00013008
#define CS35L41_DSP_MBOX_4 0x0001300C
#define CS35L41_DSP_MBOX_5 0x00013010
#define CS35L41_DSP_MBOX_6 0x00013014
#define CS35L41_DSP_MBOX_7 0x00013018
#define CS35L41_DSP_MBOX_8 0x0001301C
#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020
#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024
#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028
#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C
#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030
#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034
#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038
#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C
#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040
#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044
#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048
#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C
#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050
#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054
#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058
#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C
#define CS35L41_CLOCK_DETECT_1 0x00014000
#define CS35L41_TIMER1_CONTROL 0x00015000
#define CS35L41_TIMER1_COUNT_PRESET 0x00015004
#define CS35L41_TIMER1_START_STOP 0x0001500C
#define CS35L41_TIMER1_STATUS 0x00015010
#define CS35L41_TIMER1_COUNT_READBACK 0x00015014
#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018
#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C
#define CS35L41_TIMER2_CONTROL 0x00015100
#define CS35L41_TIMER2_COUNT_PRESET 0x00015104
#define CS35L41_TIMER2_START_STOP 0x0001510C
#define CS35L41_TIMER2_STATUS 0x00015110
#define CS35L41_TIMER2_COUNT_READBACK 0x00015114
#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118
#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C
#define CS35L41_DFT_JTAG_CONTROL 0x00016000
#define CS35L41_DIE_STS1 0x00017040
#define CS35L41_DIE_STS2 0x00017044
#define CS35L41_TEMP_CAL1 0x00017048
#define CS35L41_TEMP_CAL2 0x0001704C
#define CS35L41_DSP1_XMEM_PACK_0 0x02000000
#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0
#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000
#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8
#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800
#define CS35L41_DSP1_SYS_ID 0x025E0000
#define CS35L41_DSP1_SYS_VERSION 0x025E0004
#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008
#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C
#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010
#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018
#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020
#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028
#define CS35L41_DSP1_SYS_FEATURES 0x025E002C
#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030
#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034
#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038
#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C
#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040
#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000
#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004
#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008
#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C
#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010
#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014
#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018
#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C
#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020
#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024
#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028
#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C
#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030
#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034
#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038
#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044
#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000
#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4
#define CS35L41_DSP1_CTRL_BASE 0x02B80000
#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010
#define CS35L41_DSP1_DEBUG 0x02B80040
#define CS35L41_DSP1_TIMER_CTRL 0x02B80048
#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050
#define CS35L41_DSP1_RX1_RATE 0x02B80080
#define CS35L41_DSP1_RX2_RATE 0x02B80088
#define CS35L41_DSP1_RX3_RATE 0x02B80090
#define CS35L41_DSP1_RX4_RATE 0x02B80098
#define CS35L41_DSP1_RX5_RATE 0x02B800A0
#define CS35L41_DSP1_RX6_RATE 0x02B800A8
#define CS35L41_DSP1_RX7_RATE 0x02B800B0
#define CS35L41_DSP1_RX8_RATE 0x02B800B8
#define CS35L41_DSP1_TX1_RATE 0x02B80280
#define CS35L41_DSP1_TX2_RATE 0x02B80288
#define CS35L41_DSP1_TX3_RATE 0x02B80290
#define CS35L41_DSP1_TX4_RATE 0x02B80298
#define CS35L41_DSP1_TX5_RATE 0x02B802A0
#define CS35L41_DSP1_TX6_RATE 0x02B802A8
#define CS35L41_DSP1_TX7_RATE 0x02B802B0
#define CS35L41_DSP1_TX8_RATE 0x02B802B8
#define CS35L41_DSP1_NMI_CTRL1 0x02B80480
#define CS35L41_DSP1_NMI_CTRL2 0x02B80488
#define CS35L41_DSP1_NMI_CTRL3 0x02B80490
#define CS35L41_DSP1_NMI_CTRL4 0x02B80498
#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0
#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8
#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0
#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8
#define CS35L41_DSP1_RESUME_CTRL 0x02B80500
#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508
#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510
#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518
#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520
#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528
#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530
#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538
#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540
#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548
#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550
#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558
#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560
#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568
#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570
#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578
#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580
#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588
#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590
#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598
#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0
#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8
#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0
#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8
#define CS35L41_DSP1_SCRATCH1 0x02B805C0
#define CS35L41_DSP1_SCRATCH2 0x02B805C8
#define CS35L41_DSP1_SCRATCH3 0x02B805D0
#define CS35L41_DSP1_SCRATCH4 0x02B805D8
#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000
#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008
#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000
#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008
#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010
#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018
#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020
#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078
#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0
#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8
#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0
#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8
#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0
#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138
#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180
#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188
#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C
#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190
#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194
#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198
#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C
#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0
#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4
#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8
#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC
#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0
#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4
#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8
#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC
#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0
#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4
#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8
#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC
#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0
#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4
#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8
#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC
#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0
#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4
#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8
#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC
#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0
#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4
#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8
#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC
#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200
#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204
#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000
#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004
#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008
#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C
#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014
#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018
#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C
#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020
#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024
#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C
#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030
#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034
#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038
#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C
#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044
#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048
#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C
#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050
#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054
#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C
#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100
#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104
#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108
#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C
#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110
#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114
#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140
#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180
#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000
#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004
#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008
#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010
#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014
#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018
#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020
#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024
#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028
#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030
#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034
#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038
#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040
#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044
#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048
#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050
#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054
#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058
#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060
#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064
#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068
#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070
#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074
#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078
#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200
#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204
#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208
#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C
#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210
#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214
#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218
#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C
#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220
#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224
#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228
#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C
#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230
#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234
#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238
#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C
#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400
#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404
#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408
#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C
#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410
#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414
#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418
#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C
#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420
#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424
#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428
#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C
#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430
#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434
#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438
#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C
#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600
#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604
#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608
#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610
#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614
#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618
#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620
#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624
#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628
#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630
#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634
#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638
#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640
#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644
#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648
#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650
#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654
#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658
#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660
#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664
#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668
#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670
#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674
#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678
#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00
#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08
#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000
#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004
#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008
#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010
#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014
#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018
#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C
#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020
#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024
#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028
#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C
#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030
#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034
#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038
#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040
#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000
#define CS35L41_DSP1_WDT_STATUS 0x02BC7008
#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000
#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0
#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000
#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8
#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000
#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4
#define CS35L41_DSP1_PMEM_0 0x03800000
#define CS35L41_DSP1_PMEM_5114 0x03804FE8
/*test regs for emulation bringup*/
#define CS35L41_PLL_OVR 0x00003018
#define CS35L41_BST_TEST_DUTY 0x00003900
#define CS35L41_DIGPWM_IOCTRL 0x0000706C
/*registers populated by OTP*/
#define CS35L41_OTP_TRIM_1 0x0000208c
#define CS35L41_OTP_TRIM_2 0x00002090
#define CS35L41_OTP_TRIM_3 0x00003010
#define CS35L41_OTP_TRIM_4 0x0000300C
#define CS35L41_OTP_TRIM_5 0x0000394C
#define CS35L41_OTP_TRIM_6 0x00003950
#define CS35L41_OTP_TRIM_7 0x00003954
#define CS35L41_OTP_TRIM_8 0x00003958
#define CS35L41_OTP_TRIM_9 0x0000395C
#define CS35L41_OTP_TRIM_10 0x0000416C
#define CS35L41_OTP_TRIM_11 0x00004160
#define CS35L41_OTP_TRIM_12 0x00004170
#define CS35L41_OTP_TRIM_13 0x00004360
#define CS35L41_OTP_TRIM_14 0x00004448
#define CS35L41_OTP_TRIM_15 0x0000444C
#define CS35L41_OTP_TRIM_16 0x00006E30
#define CS35L41_OTP_TRIM_17 0x00006E34
#define CS35L41_OTP_TRIM_18 0x00006E38
#define CS35L41_OTP_TRIM_19 0x00006E3C
#define CS35L41_OTP_TRIM_20 0x00006E40
#define CS35L41_OTP_TRIM_21 0x00006E44
#define CS35L41_OTP_TRIM_22 0x00006E48
#define CS35L41_OTP_TRIM_23 0x00006E4C
#define CS35L41_OTP_TRIM_24 0x00006E50
#define CS35L41_OTP_TRIM_25 0x00006E54
#define CS35L41_OTP_TRIM_26 0x00006E58
#define CS35L41_OTP_TRIM_27 0x00006E5C
#define CS35L41_OTP_TRIM_28 0x00006E60
#define CS35L41_OTP_TRIM_29 0x00006E64
#define CS35L41_OTP_TRIM_30 0x00007418
#define CS35L41_OTP_TRIM_31 0x0000741C
#define CS35L41_OTP_TRIM_32 0x00007434
#define CS35L41_OTP_TRIM_33 0x00007068
#define CS35L41_OTP_TRIM_34 0x0000410C
#define CS35L41_OTP_TRIM_35 0x0000400C
#define CS35L41_OTP_TRIM_36 0x00002030
#define CS35L41_MAX_CACHE_REG 36
#define CS35L41_OTP_SIZE_WORDS 32
#define CS35L41_NUM_OTP_ELEM 100
#define CS35L41_NUM_OTP_MAPS 5
#define CS35L41_VALID_PDATA 0x80000000
#define CS35L41_NUM_SUPPLIES 2
#define CS35L41_SCLK_MSTR_MASK 0x10
#define CS35L41_SCLK_MSTR_SHIFT 4
#define CS35L41_LRCLK_MSTR_MASK 0x01
#define CS35L41_LRCLK_MSTR_SHIFT 0
#define CS35L41_SCLK_INV_MASK 0x40
#define CS35L41_SCLK_INV_SHIFT 6
#define CS35L41_LRCLK_INV_MASK 0x04
#define CS35L41_LRCLK_INV_SHIFT 2
#define CS35L41_SCLK_FRC_MASK 0x20
#define CS35L41_SCLK_FRC_SHIFT 5
#define CS35L41_LRCLK_FRC_MASK 0x02
#define CS35L41_LRCLK_FRC_SHIFT 1
#define CS35L41_AMP_GAIN_PCM_MASK 0x3E0
#define CS35L41_AMP_GAIN_ZC_MASK 0x0400
#define CS35L41_AMP_GAIN_ZC_SHIFT 10
#define CS35L41_BST_CTL_MASK 0xFF
#define CS35L41_BST_CTL_SEL_MASK 0x03
#define CS35L41_BST_CTL_SEL_REG 0x00
#define CS35L41_BST_CTL_SEL_CLASSH 0x01
#define CS35L41_BST_IPK_MASK 0x7F
#define CS35L41_BST_IPK_SHIFT 0
#define CS35L41_BST_LIM_MASK 0x4
#define CS35L41_BST_LIM_SHIFT 2
#define CS35L41_BST_K1_MASK 0x000000FF
#define CS35L41_BST_K1_SHIFT 0
#define CS35L41_BST_K2_MASK 0x0000FF00
#define CS35L41_BST_K2_SHIFT 8
#define CS35L41_BST_SLOPE_MASK 0x0000FF00
#define CS35L41_BST_SLOPE_SHIFT 8
#define CS35L41_BST_LBST_VAL_MASK 0x00000003
#define CS35L41_BST_LBST_VAL_SHIFT 0
#define CS35L41_TEMP_THLD_MASK 0x03
#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF
#define CS35L41_PDM_MODE_MASK 0x01
#define CS35L41_PDM_MODE_SHIFT 0
#define CS35L41_CH_MEM_DEPTH_MASK 0x07
#define CS35L41_CH_MEM_DEPTH_SHIFT 0
#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000
#define CS35L41_CH_HDRM_CTL_SHIFT 16
#define CS35L41_CH_REL_RATE_MASK 0xFF00
#define CS35L41_CH_REL_RATE_SHIFT 8
#define CS35L41_CH_WKFET_DLY_MASK 0x001C
#define CS35L41_CH_WKFET_DLY_SHIFT 2
#define CS35L41_CH_WKFET_THLD_MASK 0x0F00
#define CS35L41_CH_WKFET_THLD_SHIFT 8
#define CS35L41_HW_NG_SEL_MASK 0x3F00
#define CS35L41_HW_NG_SEL_SHIFT 8
#define CS35L41_HW_NG_DLY_MASK 0x0070
#define CS35L41_HW_NG_DLY_SHIFT 4
#define CS35L41_HW_NG_THLD_MASK 0x0007
#define CS35L41_HW_NG_THLD_SHIFT 0
#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000
#define CS35L41_DSP_NG_ENABLE_SHIFT 16
#define CS35L41_DSP_NG_THLD_MASK 0x7
#define CS35L41_DSP_NG_THLD_SHIFT 0
#define CS35L41_DSP_NG_DELAY_MASK 0x0F00
#define CS35L41_DSP_NG_DELAY_SHIFT 8
#define CS35L41_ASP_FMT_MASK 0x0700
#define CS35L41_ASP_FMT_SHIFT 8
#define CS35L41_ASP_DOUT_HIZ_MASK 0x03
#define CS35L41_ASP_DOUT_HIZ_SHIFT 0
#define CS35L41_ASP_WIDTH_16 0x10
#define CS35L41_ASP_WIDTH_24 0x18
#define CS35L41_ASP_WIDTH_32 0x20
#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000
#define CS35L41_ASP_WIDTH_TX_SHIFT 16
#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000
#define CS35L41_ASP_WIDTH_RX_SHIFT 24
#define CS35L41_ASP_RX1_SLOT_MASK 0x3F
#define CS35L41_ASP_RX1_SLOT_SHIFT 0
#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00
#define CS35L41_ASP_RX2_SLOT_SHIFT 8
#define CS35L41_ASP_RX_WL_MASK 0x3F
#define CS35L41_ASP_TX_WL_MASK 0x3F
#define CS35L41_ASP_RX_WL_SHIFT 0
#define CS35L41_ASP_TX_WL_SHIFT 0
#define CS35L41_ASP_SOURCE_MASK 0x7F
#define CS35L41_INPUT_SRC_ASPRX1 0x08
#define CS35L41_INPUT_SRC_ASPRX2 0x09
#define CS35L41_INPUT_SRC_VMON 0x18
#define CS35L41_INPUT_SRC_IMON 0x19
#define CS35L41_INPUT_SRC_CLASSH 0x21
#define CS35L41_INPUT_SRC_VPMON 0x28
#define CS35L41_INPUT_SRC_VBSTMON 0x29
#define CS35L41_INPUT_SRC_TEMPMON 0x3A
#define CS35L41_INPUT_SRC_RSVD 0x3B
#define CS35L41_INPUT_DSP_TX1 0x32
#define CS35L41_INPUT_DSP_TX2 0x33
#define CS35L41_PLL_CLK_SEL_MASK 0x07
#define CS35L41_PLL_CLK_SEL_SHIFT 0
#define CS35L41_PLL_CLK_EN_MASK 0x10
#define CS35L41_PLL_CLK_EN_SHIFT 4
#define CS35L41_PLL_OPENLOOP_MASK 0x0800
#define CS35L41_PLL_OPENLOOP_SHIFT 11
#define CS35L41_PLLSRC_SCLK 0
#define CS35L41_PLLSRC_LRCLK 1
#define CS35L41_PLLSRC_SELF 3
#define CS35L41_PLLSRC_PDMCLK 4
#define CS35L41_PLLSRC_MCLK 5
#define CS35L41_PLLSRC_SWIRE 7
#define CS35L41_REFCLK_FREQ_MASK 0x7E0
#define CS35L41_REFCLK_FREQ_SHIFT 5
#define CS35L41_GLOBAL_FS_MASK 0x1F
#define CS35L41_GLOBAL_FS_SHIFT 0
#define CS35L41_GLOBAL_EN_MASK 0x01
#define CS35L41_GLOBAL_EN_SHIFT 0
#define CS35L41_BST_EN_MASK 0x0030
#define CS35L41_BST_EN_SHIFT 4
#define CS35L41_BST_EN_DEFAULT 0x2
#define CS35L41_AMP_EN_SHIFT 0
#define CS35L41_AMP_EN_MASK 1
#define CS35L41_PDN_DONE_MASK 0x00800000
#define CS35L41_PDN_DONE_SHIFT 23
#define CS35L41_PUP_DONE_MASK 0x01000000
#define CS35L41_PUP_DONE_SHIFT 24
#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F
#define CS35L36_PUP_DONE_IRQ_MASK 0xBF
#define CS35L41_AMP_SHORT_ERR 0x80000000
#define CS35L41_BST_SHORT_ERR 0x0100
#define CS35L41_TEMP_WARN 0x8000
#define CS35L41_TEMP_ERR 0x00020000
#define CS35L41_BST_OVP_ERR 0x40
#define CS35L41_BST_DCM_UVP_ERR 0x80
#define CS35L41_OTP_BOOT_DONE 0x02
#define CS35L41_PLL_UNLOCK 0x10
#define CS35L41_OTP_BOOT_ERR 0x80000000
#define CS35L41_AMP_SHORT_ERR_RLS 0x02
#define CS35L41_BST_SHORT_ERR_RLS 0x04
#define CS35L41_BST_OVP_ERR_RLS 0x08
#define CS35L41_BST_UVP_ERR_RLS 0x10
#define CS35L41_TEMP_WARN_ERR_RLS 0x20
#define CS35L41_TEMP_ERR_RLS 0x40
#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F
#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF
#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF
#define CS35L41_GPIO_DIR_MASK 0x80000000
#define CS35L41_GPIO1_CTRL_MASK 0x00030000
#define CS35L41_GPIO1_CTRL_SHIFT 16
#define CS35L41_GPIO2_CTRL_MASK 0x07000000
#define CS35L41_GPIO2_CTRL_SHIFT 24
#define CS35L41_GPIO_CTRL_OPEN_INT 2
#define CS35L41_GPIO_CTRL_ACTV_LO 4
#define CS35L41_GPIO_CTRL_ACTV_HI 5
#define CS35L41_GPIO_POL_MASK 0x1000
#define CS35L41_GPIO_POL_SHIFT 12
#define CS35L41_AMP_INV_PCM_SHIFT 14
#define CS35L41_AMP_INV_PCM_MASK (1 << CS35L41_AMP_INV_PCM_SHIFT)
#define CS35L41_AMP_PCM_VOL_SHIFT 3
#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3)
#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF
#define CS35L41_CHIP_ID 0x35a40
#define CS35L41R_CHIP_ID 0x35b40
#define CS35L41_MTLREVID_MASK 0x0F
#define CS35L41_REVID_A0 0xA0
#define CS35L41_REVID_B0 0xB0
#define CS35L41_REVID_B2 0xB2
#define CS35L41_HALO_CORE_RESET 0x00000200
#define CS35L41_FS1_WINDOW_MASK 0x000007FF
#define CS35L41_FS2_WINDOW_MASK 0x00FFF800
#define CS35L41_FS2_WINDOW_SHIFT 12
#define CS35L41_SPI_MAX_FREQ_OTP 4000000
#define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
#define CS35L41_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
bool cs35l41_readable_reg(struct device *dev, unsigned int reg);
bool cs35l41_precious_reg(struct device *dev, unsigned int reg);
bool cs35l41_volatile_reg(struct device *dev, unsigned int reg);
struct cs35l41_otp_packed_element_t {
u32 reg;
u8 shift;
u8 size;
};
struct cs35l41_otp_map_element_t {
u32 id;
u32 num_elements;
const struct cs35l41_otp_packed_element_t *map;
u32 bit_offset;
u32 word_offset;
};
extern const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG];
extern const struct cs35l41_otp_map_element_t
cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS];
#define CS35L41_REGSTRIDE 4
struct cs35l41_private {
struct snd_soc_codec *codec;
struct cs35l41_platform_data pdata;
struct device *dev;
struct regmap *regmap;
struct regulator_bulk_data supplies[CS35L41_NUM_SUPPLIES];
int irq;
/* GPIO for /RST */
struct gpio_desc *reset_gpio;
void (*otp_setup)(struct cs35l41_private *cs35l41, bool is_pre_setup,
unsigned int *freq);
};
int cs35l41_probe(struct cs35l41_private *cs35l41,
struct cs35l41_platform_data *pdata);
int cs35l41_remove(struct cs35l41_private *cs35l41);
#endif /*__CS35L41_H__*/
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