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Commit a32b2ffb authored by Ben Skeggs's avatar Ben Skeggs
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drm/nvc0-/gr: generate cs register lists from grctx data 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 70f824ac
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Showing with 1152 additions and 2073 deletions
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
View file @ a32b2ffb
...@@ -29,23 +29,26 @@ ...@@ -29,23 +29,26 @@
*/ */
#ifdef INCLUDE_DATA #ifdef INCLUDE_DATA
gpc_mmio_list_head: .b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head: .b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head: .b32 #mmio_list_base
unk_mmio_list_tail: .b32 #mmio_list_base
gpc_id: .b32 0 gpc_id: .b32 0
gpc_mmio_list_head: .b32 0
gpc_mmio_list_tail: .b32 0
tpc_count: .b32 0 tpc_count: .b32 0
tpc_mask: .b32 0 tpc_mask: .b32 0
tpc_mmio_list_head: .b32 0
tpc_mmio_list_tail: .b32 0
#ifdef NVGK #ifdef NVGK
unk_count: .b32 1 unk_count: .b32 1
unk_mask: .b32 1 unk_mask: .b32 1
unk_mmio_list_head: .b32 #nve4_unk_mmio_head
unk_mmio_list_tail: .b32 #nve4_unk_mmio_tail
#endif #endif
cmd_queue: queue_init cmd_queue: queue_init
mmio_list_base:
#endif #endif
#ifdef INCLUDE_CODE #ifdef INCLUDE_CODE
...@@ -68,7 +71,6 @@ error: ...@@ -68,7 +71,6 @@ error:
// fall through to main loop after completion. // fall through to main loop after completion.
// //
// Input: // Input:
// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
// CC_SCRATCH[1]: context base // CC_SCRATCH[1]: context base
// //
// Output: // Output:
...@@ -113,23 +115,7 @@ init: ...@@ -113,23 +115,7 @@ init:
iord $r2 I[$r1 + 0x000] // MYINDEX iord $r2 I[$r1 + 0x000] // MYINDEX
st b32 D[$r0 + #gpc_id] $r2 st b32 D[$r0 + #gpc_id] $r2
// find context data for this chipset
mov $r2 0x800
shl b32 $r2 6
iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
mov $r1 #chipsets - 12
init_find_chipset:
add b32 $r1 12
ld b32 $r3 D[$r1 + 0x00]
cmpu b32 $r3 $r2
bra e #init_context
cmpu b32 $r3 0
bra ne #init_find_chipset
// unknown chipset
ret
// initialise context base, and size tracking // initialise context base, and size tracking
init_context:
mov $r2 0x800 mov $r2 0x800
shl b32 $r2 6 shl b32 $r2 6
iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
...@@ -143,24 +129,16 @@ init: ...@@ -143,24 +129,16 @@ init:
iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
// calculate GPC mmio context size, store the chipset-specific // calculate GPC mmio context size
// mmio list pointers somewhere we can get at them later without ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
// re-parsing the chipset list ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
clear b32 $r14
clear b32 $r15
ld b16 $r14 D[$r1 + 4]
ld b16 $r15 D[$r1 + 6]
st b16 D[$r0 + #gpc_mmio_list_head] $r14
st b16 D[$r0 + #gpc_mmio_list_tail] $r15
call #mmctx_size call #mmctx_size
add b32 $r2 $r15 add b32 $r2 $r15
add b32 $r3 $r15 add b32 $r3 $r15
// calculate per-TPC mmio context size, store the list pointers // calculate per-TPC mmio context size
ld b16 $r14 D[$r1 + 8] ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
ld b16 $r15 D[$r1 + 10] ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
st b16 D[$r0 + #tpc_mmio_list_head] $r14
st b16 D[$r0 + #tpc_mmio_list_tail] $r15
call #mmctx_size call #mmctx_size
ld b32 $r14 D[$r0 + #tpc_count] ld b32 $r14 D[$r0 + #tpc_count]
mulu $r14 $r15 mulu $r14 $r15
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
View file @ a32b2ffb
...@@ -29,120 +29,6 @@ ...@@ -29,120 +29,6 @@
#define INCLUDE_DATA #define INCLUDE_DATA
#include "com.fuc" #include "com.fuc"
#include "gpc.fuc" #include "gpc.fuc"
chipsets:
.b8 0xc0 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc0_tpc_mmio_tail
.b8 0xc1 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc1_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc1_tpc_mmio_tail
.b8 0xc3 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc3_tpc_mmio_tail
.b8 0xc4 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc3_tpc_mmio_tail
.b8 0xc8 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc0_tpc_mmio_tail
.b8 0xce 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc3_tpc_mmio_tail
.b8 0xcf 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc3_tpc_mmio_tail
.b8 0xd9 0 0 0
.b16 #nvd9_gpc_mmio_head
.b16 #nvc1_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvd9_tpc_mmio_tail
.b8 0xd7 0 0 0
.b16 #nvd9_gpc_mmio_head
.b16 #nvc1_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvd9_tpc_mmio_tail
.b8 0 0 0 0
// GPC mmio lists
nvc0_gpc_mmio_head:
mmctx_data(0x000408, 1)
nvd9_gpc_mmio_head:
mmctx_data(0x000380, 1)
mmctx_data(0x000400, 2);
mmctx_data(0x00040c, 3);
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
mmctx_data(0x000700, 5)
mmctx_data(0x000800, 1)
mmctx_data(0x000808, 3)
mmctx_data(0x000828, 1)
mmctx_data(0x000830, 1)
mmctx_data(0x0008d8, 1)
mmctx_data(0x0008e0, 1)
mmctx_data(0x0008e8, 6)
mmctx_data(0x00091c, 1)
mmctx_data(0x000924, 3)
mmctx_data(0x000b00, 1)
mmctx_data(0x000b08, 6)
mmctx_data(0x000bb8, 1)
mmctx_data(0x000c08, 1)
mmctx_data(0x000c10, 8)
mmctx_data(0x000c80, 1)
mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nvc0_gpc_mmio_tail:
mmctx_data(0x000c6c, 1);
nvc1_gpc_mmio_tail:
// TPC mmio lists
nvc0_tpc_mmio_head:
mmctx_data(0x000018, 1)
mmctx_data(0x00003c, 1)
mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
mmctx_data(0x000300, 6)
mmctx_data(0x0003d0, 1)
mmctx_data(0x0003e0, 2)
mmctx_data(0x000400, 3)
mmctx_data(0x000420, 1)
mmctx_data(0x0004b0, 1)
mmctx_data(0x0004e8, 1)
mmctx_data(0x0004f4, 1)
mmctx_data(0x000520, 2)
mmctx_data(0x000604, 4)
mmctx_data(0x000644, 20)
mmctx_data(0x000698, 1)
mmctx_data(0x000750, 2)
nvc0_tpc_mmio_tail:
mmctx_data(0x00021c, 2)
mmctx_data(0x0002c4, 1)
mmctx_data(0x000730, 8)
mmctx_data(0x000758, 1)
nvc3_tpc_mmio_tail:
mmctx_data(0x000544, 1)
nvc1_tpc_mmio_tail:
mmctx_data(0x000424, 2);
mmctx_data(0x0006e0, 1);
nvd9_tpc_mmio_tail:
#undef INCLUDE_DATA #undef INCLUDE_DATA
.section #nvc0_grgpc_code .section #nvc0_grgpc_code
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
View file @ a32b2ffb
uint32_t nvc0_grgpc_data[] = { uint32_t nvc0_grgpc_data[] = {
/* 0x0000: gpc_id */ /* 0x0000: gpc_mmio_list_head */
0x00000000, 0x00000064,
/* 0x0004: gpc_mmio_list_head */ /* 0x0004: gpc_mmio_list_tail */
0x00000000, /* 0x0004: tpc_mmio_list_head */
/* 0x0008: gpc_mmio_list_tail */ 0x00000064,
0x00000000, /* 0x0008: tpc_mmio_list_tail */
/* 0x000c: tpc_count */ /* 0x0008: unk_mmio_list_head */
0x00000000, 0x00000064,
/* 0x0010: tpc_mask */ /* 0x000c: unk_mmio_list_tail */
0x00000064,
/* 0x0010: gpc_id */
0x00000000, 0x00000000,
/* 0x0014: tpc_mmio_list_head */ /* 0x0014: tpc_count */
0x00000000, 0x00000000,
/* 0x0018: tpc_mmio_list_tail */ /* 0x0018: tpc_mask */
0x00000000, 0x00000000,
/* 0x001c: cmd_queue */ /* 0x001c: cmd_queue */
0x00000000, 0x00000000,
...@@ -32,96 +34,6 @@ uint32_t nvc0_grgpc_data[] = { ...@@ -32,96 +34,6 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
/* 0x0064: chipsets */
0x000000c0,
0x013c00d4,
0x018c0140,
0x000000c1,
0x014000d4,
0x01a00140,
0x000000c3,
0x013c00d4,
0x019c0140,
0x000000c4,
0x013c00d4,
0x019c0140,
0x000000c8,
0x013c00d4,
0x018c0140,
0x000000ce,
0x013c00d4,
0x019c0140,
0x000000cf,
0x013c00d4,
0x019c0140,
0x000000d9,
0x014000d8,
0x01a80140,
0x000000d7,
0x014000d8,
0x01a80140,
0x00000000,
/* 0x00d4: nvc0_gpc_mmio_head */
0x00000408,
/* 0x00d8: nvd9_gpc_mmio_head */
0x00000380,
0x04000400,
0x0800040c,
0x20000450,
0x00000600,
0x00000684,
0x10000700,
0x00000800,
0x08000808,
0x00000828,
0x00000830,
0x000008d8,
0x000008e0,
0x140008e8,
0x0000091c,
0x08000924,
0x00000b00,
0x14000b08,
0x00000bb8,
0x00000c08,
0x1c000c10,
0x00000c80,
0x00000c8c,
0x08001000,
0x00001014,
/* 0x013c: nvc0_gpc_mmio_tail */
0x00000c6c,
/* 0x0140: nvc1_gpc_mmio_tail */
/* 0x0140: nvc0_tpc_mmio_head */
0x00000018,
0x0000003c,
0x00000048,
0x00000064,
0x00000088,
0x14000200,
0x14000300,
0x000003d0,
0x040003e0,
0x08000400,
0x00000420,
0x000004b0,
0x000004e8,
0x000004f4,
0x04000520,
0x0c000604,
0x4c000644,
0x00000698,
0x04000750,
/* 0x018c: nvc0_tpc_mmio_tail */
0x0400021c,
0x000002c4,
0x1c000730,
0x00000758,
/* 0x019c: nvc3_tpc_mmio_tail */
0x00000544,
/* 0x01a0: nvc1_tpc_mmio_tail */
0x04000424,
0x000006e0,
}; };
uint32_t nvc0_grgpc_code[] = { uint32_t nvc0_grgpc_code[] = {
...@@ -355,7 +267,7 @@ uint32_t nvc0_grgpc_code[] = { ...@@ -355,7 +267,7 @@ uint32_t nvc0_grgpc_code[] = {
0xf10004fe, 0xf10004fe,
0xf0120017, 0xf0120017,
0x12d00227, 0x12d00227,
0x3e17f100, 0x0d17f100,
0x0010fe04, 0x0010fe04,
0x040017f1, 0x040017f1,
0xf0c010d0, 0xf0c010d0,
...@@ -367,154 +279,152 @@ uint32_t nvc0_grgpc_code[] = { ...@@ -367,154 +279,152 @@ uint32_t nvc0_grgpc_code[] = {
0x1f24f001, 0x1f24f001,
0xb60432bb, 0xb60432bb,
0x02800132, 0x02800132,
0x04038003, 0x06038005,
0x040010b7, 0x040010b7,
0x800012cf, 0x800012cf,
0x27f10002, 0x27f10402,
0x24b60800, 0x24b60800,
0x0022cf06, 0x4022cf06,
/* 0x035f: init_find_chipset */ 0x47f134bd,
0xb65817f0, 0x44b60700,
0x13980c10, 0x08259506,
0x0432b800, 0xd00045d0,
0xb00b0bf4, 0x0e984045,
0x1bf40034, 0x010f9800,
/* 0x0373: init_context */ 0x013d21f5,
0xf100f8f1, 0xbb002fbb,
0xb6080027, 0x0e98003f,
0x22cf0624, 0x020f9801,
0xf134bd40, 0x013d21f5,
0xb6070047, 0xfd050e98,
0x25950644, 0x2ebb00ef,
0x0045d008, 0x003ebb00,
0xbd4045d0, 0x130040b7,
0x58f4bde4, 0xd00235b6,
0x1f58021e, 0x25b60043,
0x020e4003, 0x0635b608,
0xf5040f40, 0xb60120b6,
0xbb013d21, 0x24b60130,
0x3fbb002f, 0x0834b608,
0x041e5800, 0xf5022fb9,
0x40051f58, 0xbb026321,
0x0f400a0e, 0x17f1003f,
0x3d21f50c, 0x14b60800,
0x030e9801, 0x4013d006,
0xbb00effd, 0x080010b7,
0x3ebb002e, 0x29f024bd,
0x0040b700, 0x0012d01f,
0x0235b613, /* 0x03d0: main */
0xb60043d0, 0xf40031f4,
0x35b60825, 0xd7f00028,
0x0120b606, 0x3921f41c,
0xb60130b6, 0xb0f401f4,
0x34b60824, 0x18f404e4,
0x022fb908, 0x0181fe1e,
0x026321f5, 0xbd0627f0,
0xf1003fbb, 0x0412fd20,
0xb6080017, 0xfd01e4b6,
0x13d00614, 0x18fe051e,
0x0010b740, 0x9221f500,
0xf024bd08, 0xd30ef404,
0x12d01f29, /* 0x0400: main_not_ctx_xfer */
/* 0x0401: main */ 0xf010ef94,
0x0031f400, 0x21f501f5,
0xf00028f4, 0x0ef402ec,
0x21f41cd7, /* 0x040d: ih */
0xf401f439, 0xfe80f9c6,
0xf404e4b0, 0x80f90188,
0x81fe1e18, 0xa0f990f9,
0x0627f001, 0xd0f9b0f9,
0x12fd20bd, 0xf0f9e0f9,
0x01e4b604, 0xc4800acf,
0xfe051efd, 0x0bf404ab,
0x21f50018, 0x00b7f11d,
0x0ef404c3, 0x1cd7f019,
/* 0x0431: main_not_ctx_xfer */ 0xcf40becf,
0x10ef94d3, 0x21f400bf,
0xf501f5f0, 0x00b0b704,
0xf402ec21, 0x01e7f004,
/* 0x043e: ih */ /* 0x0443: ih_no_fifo */
0x80f9c60e, 0xd000bed0,
0xf90188fe, 0xf0fc400a,
0xf990f980, 0xd0fce0fc,
0xf9b0f9a0, 0xa0fcb0fc,
0xf9e0f9d0, 0x80fc90fc,
0x800acff0, 0xfc0088fe,
0xf404abc4, 0x0032f480,
0xb7f11d0b, /* 0x045e: hub_barrier_done */
0xd7f01900, 0xf7f001f8,
0x40becf1c, 0x040e9801,
0xf400bfcf, 0xf104febb,
0xb0b70421, 0xf09418e7,
0xe7f00400, 0x21f440e3,
0x00bed001, /* 0x0473: ctx_redswitch */
/* 0x0474: ih_no_fifo */ 0xf100f88d,
0xfc400ad0, 0xb60614e7,
0xfce0fcf0, 0xf7f006e4,
0xfcb0fcd0, 0x00efd020,
0xfc90fca0, /* 0x0483: ctx_redswitch_delay */
0x0088fe80, 0xb608f7f0,
0x32f480fc, 0x1bf401f2,
/* 0x048f: hub_barrier_done */ 0x20f7f1fd,
0xf001f800, 0x00efd00a,
0x0e9801f7, /* 0x0492: ctx_xfer */
0x04febb00, 0x17f100f8,
0x9418e7f1, 0x14b60a04,
0xf440e3f0, 0x001fd006,
0x00f88d21, 0xf50711f4,
/* 0x04a4: ctx_redswitch */ /* 0x04a3: ctx_xfer_not_load */
0x0614e7f1, 0xf1047321,
0xf006e4b6, 0xf04afc17,
0xefd020f7, 0x27f00213,
0x08f7f000, 0x0012d00c,
/* 0x04b4: ctx_redswitch_delay */ 0x020721f5,
0xf401f2b6, 0x47fc27f1,
0xf7f1fd1b, 0xd00223f0,
0xefd00a20, 0x2cf00020,
/* 0x04c3: ctx_xfer */ 0x0320b601,
0xf100f800, 0xf00012d0,
0xb60a0417, 0xa5f001ac,
0x1fd00614, 0x00b7f002,
0x0711f400, 0x9850b3f0,
0x04a421f5, 0xc4b6040c,
/* 0x04d4: ctx_xfer_not_load */ 0x00bcbb0f,
0x4afc17f1, 0x98000c98,
0xf00213f0, 0xe7f0010d,
0x12d00c27, 0x5c21f500,
0x0721f500, 0x01acf001,
0xfc27f102, 0x4000b7f1,
0x0223f047, 0x9850b3f0,
0xf00020d0, 0xc4b6040c,
0x20b6012c, 0x00bcbb0f,
0x0012d003, 0x98010c98,
0xf001acf0, 0x0f98020d,
0xb7f002a5, 0x00e7f106,
0x50b3f000, 0x5c21f508,
0xb6000c98, 0x0721f501,
0xbcbb0fc4, 0x0601f402,
0x010c9800, /* 0x0517: ctx_xfer_post */
0xf0020d98, 0xf11412f4,
0x21f500e7, 0xf04afc17,
0xacf0015c, 0x27f00213,
0x00b7f101, 0x0012d00d,
0x50b3f040, 0x020721f5,
0xb6000c98, /* 0x0528: ctx_xfer_done */
0xbcbb0fc4, 0x045e21f5,
0x050c9800, 0x000000f8,
0x98060d98, 0x00000000,
0xe7f1040f, 0x00000000,
0x21f50800, 0x00000000,
0x21f5015c, 0x00000000,
0x01f40207, 0x00000000,
0x1412f406, 0x00000000,
/* 0x0548: ctx_xfer_post */ 0x00000000,
0x4afc17f1, 0x00000000,
0xf00213f0, 0x00000000,
0x12d00d27, 0x00000000,
0x0721f500, 0x00000000,
/* 0x0559: ctx_xfer_done */ 0x00000000,
0x8f21f502,
0x0000f804,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
View file @ a32b2ffb
...@@ -29,147 +29,6 @@ ...@@ -29,147 +29,6 @@
#define INCLUDE_DATA #define INCLUDE_DATA
#include "com.fuc" #include "com.fuc"
#include "gpc.fuc" #include "gpc.fuc"
chipsets:
.b8 0xe4 0 0 0
.b16 #nve4_gpc_mmio_head
.b16 #nve4_gpc_mmio_tail
.b16 #nve4_tpc_mmio_head
.b16 #nve4_tpc_mmio_tail
.b8 0xe7 0 0 0
.b16 #nve4_gpc_mmio_head
.b16 #nve4_gpc_mmio_tail
.b16 #nve4_tpc_mmio_head
.b16 #nve4_tpc_mmio_tail
.b8 0xe6 0 0 0
.b16 #nve4_gpc_mmio_head
.b16 #nve4_gpc_mmio_tail
.b16 #nve4_tpc_mmio_head
.b16 #nve4_tpc_mmio_tail
.b8 0xf0 0 0 0
.b16 #nvf0_gpc_mmio_head
.b16 #nvf0_gpc_mmio_tail
.b16 #nvf0_tpc_mmio_head
.b16 #nvf0_tpc_mmio_tail
.b8 0 0 0 0
// GPC mmio lists
nve4_gpc_mmio_head:
mmctx_data(0x000380, 1)
mmctx_data(0x000400, 2)
mmctx_data(0x00040c, 3)
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
mmctx_data(0x000700, 5)
mmctx_data(0x000800, 1)
mmctx_data(0x000808, 3)
mmctx_data(0x000828, 1)
mmctx_data(0x000830, 1)
mmctx_data(0x0008d8, 1)
mmctx_data(0x0008e0, 1)
mmctx_data(0x0008e8, 6)
mmctx_data(0x00091c, 1)
mmctx_data(0x000924, 3)
mmctx_data(0x000b00, 1)
mmctx_data(0x000b08, 6)
mmctx_data(0x000bb8, 1)
mmctx_data(0x000c08, 1)
mmctx_data(0x000c10, 8)
mmctx_data(0x000c40, 1)
mmctx_data(0x000c6c, 1)
mmctx_data(0x000c80, 1)
mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nve4_gpc_mmio_tail:
nvf0_gpc_mmio_head:
mmctx_data(0x000380, 1)
mmctx_data(0x000400, 2)
mmctx_data(0x00040c, 3)
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
mmctx_data(0x000700, 5)
mmctx_data(0x000800, 1)
mmctx_data(0x000808, 3)
mmctx_data(0x000828, 1)
mmctx_data(0x000830, 1)
mmctx_data(0x0008d8, 1)
mmctx_data(0x0008e0, 1)
mmctx_data(0x0008e8, 6)
mmctx_data(0x00091c, 1)
mmctx_data(0x000924, 3)
mmctx_data(0x000b00, 1)
mmctx_data(0x000b08, 6)
mmctx_data(0x000bb8, 1)
mmctx_data(0x000c08, 1)
mmctx_data(0x000c10, 8)
mmctx_data(0x000c40, 1)
mmctx_data(0x000c6c, 1)
mmctx_data(0x000c80, 1)
mmctx_data(0x000c8c, 1)
mmctx_data(0x000d24, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nvf0_gpc_mmio_tail:
// TPC mmio lists
nve4_tpc_mmio_head:
mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
mmctx_data(0x00021c, 2)
mmctx_data(0x000230, 1)
mmctx_data(0x0002c4, 1)
mmctx_data(0x000400, 3)
mmctx_data(0x000420, 3)
mmctx_data(0x0004e8, 1)
mmctx_data(0x0004f4, 1)
mmctx_data(0x000604, 4)
mmctx_data(0x000644, 22)
mmctx_data(0x0006ac, 2)
mmctx_data(0x0006c8, 1)
mmctx_data(0x000730, 8)
mmctx_data(0x000758, 1)
mmctx_data(0x000770, 1)
mmctx_data(0x000778, 2)
nve4_tpc_mmio_tail:
nvf0_tpc_mmio_head:
mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
mmctx_data(0x00021c, 2)
mmctx_data(0x000230, 1)
mmctx_data(0x0002c4, 1)
mmctx_data(0x000400, 3)
mmctx_data(0x000420, 3)
mmctx_data(0x0004e8, 1)
mmctx_data(0x0004f4, 1)
mmctx_data(0x000604, 4)
mmctx_data(0x000644, 22)
mmctx_data(0x0006ac, 2)
mmctx_data(0x0006b8, 1)
mmctx_data(0x0006c8, 1)
mmctx_data(0x000730, 8)
mmctx_data(0x000758, 1)
mmctx_data(0x000770, 1)
mmctx_data(0x000778, 2)
nvf0_tpc_mmio_tail:
// UNK mmio lists
nve4_unk_mmio_head:
mmctx_data(0x000024, 1)
mmctx_data(0x0000c0, 2)
mmctx_data(0x0000e4, 1)
mmctx_data(0x000100, 6)
mmctx_data(0x0001d0, 1)
mmctx_data(0x0001e0, 2)
nve4_unk_mmio_tail:
#undef INCLUDE_DATA #undef INCLUDE_DATA
.section #nve0_grgpc_code .section #nve0_grgpc_code
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
View file @ a32b2ffb
uint32_t nve0_grgpc_data[] = { uint32_t nve0_grgpc_data[] = {
/* 0x0000: gpc_id */ /* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
/* 0x0004: tpc_mmio_list_head */
0x0000006c,
/* 0x0008: tpc_mmio_list_tail */
/* 0x0008: unk_mmio_list_head */
0x0000006c,
/* 0x000c: unk_mmio_list_tail */
0x0000006c,
/* 0x0010: gpc_id */
0x00000000,
/* 0x0014: tpc_count */
0x00000000,
/* 0x0018: tpc_mask */
0x00000000,
/* 0x001c: unk_count */
0x00000001,
/* 0x0020: unk_mask */
0x00000001,
/* 0x0024: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
/* 0x0004: gpc_mmio_list_head */
0x00000000, 0x00000000,
/* 0x0008: gpc_mmio_list_tail */
0x00000000, 0x00000000,
/* 0x000c: tpc_count */
0x00000000, 0x00000000,
/* 0x0010: tpc_mask */
0x00000000, 0x00000000,
/* 0x0014: tpc_mmio_list_head */
0x00000000, 0x00000000,
/* 0x0018: tpc_mmio_list_tail */
0x00000000, 0x00000000,
/* 0x001c: unk_count */
0x00000001,
/* 0x0020: unk_mask */
0x00000001,
/* 0x0024: unk_mmio_list_head */
0x00000220,
/* 0x0028: unk_mmio_list_tail */
0x00000238,
/* 0x002c: cmd_queue */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0074: chipsets */
0x000000e4,
0x011400a8,
0x01d00184,
0x000000e7,
0x011400a8,
0x01d00184,
0x000000e6,
0x011400a8,
0x01d00184,
0x000000f0,
0x01840114,
0x022001d0,
0x00000000,
/* 0x00a8: nve4_gpc_mmio_head */
0x00000380,
0x04000400,
0x0800040c,
0x20000450,
0x00000600,
0x00000684,
0x10000700,
0x00000800,
0x08000808,
0x00000828,
0x00000830,
0x000008d8,
0x000008e0,
0x140008e8,
0x0000091c,
0x08000924,
0x00000b00,
0x14000b08,
0x00000bb8,
0x00000c08,
0x1c000c10,
0x00000c40,
0x00000c6c,
0x00000c80,
0x00000c8c,
0x08001000,
0x00001014,
/* 0x0114: nve4_gpc_mmio_tail */
/* 0x0114: nvf0_gpc_mmio_head */
0x00000380,
0x04000400,
0x0800040c,
0x20000450,
0x00000600,
0x00000684,
0x10000700,
0x00000800,
0x08000808,
0x00000828,
0x00000830,
0x000008d8,
0x000008e0,
0x140008e8,
0x0000091c,
0x08000924,
0x00000b00,
0x14000b08,
0x00000bb8,
0x00000c08,
0x1c000c10,
0x00000c40,
0x00000c6c,
0x00000c80,
0x00000c8c,
0x00000d24,
0x08001000,
0x00001014,
/* 0x0184: nvf0_gpc_mmio_tail */
/* 0x0184: nve4_tpc_mmio_head */
0x00000048,
0x00000064,
0x00000088,
0x14000200,
0x0400021c,
0x00000230,
0x000002c4,
0x08000400,
0x08000420,
0x000004e8,
0x000004f4,
0x0c000604,
0x54000644,
0x040006ac,
0x000006c8,
0x1c000730,
0x00000758,
0x00000770,
0x04000778,
/* 0x01d0: nve4_tpc_mmio_tail */
/* 0x01d0: nvf0_tpc_mmio_head */
0x00000048,
0x00000064,
0x00000088,
0x14000200,
0x0400021c,
0x00000230,
0x000002c4,
0x08000400,
0x08000420,
0x000004e8,
0x000004f4,
0x0c000604,
0x54000644,
0x040006ac,
0x000006b8,
0x000006c8,
0x1c000730,
0x00000758,
0x00000770,
0x04000778,
/* 0x0220: nvf0_tpc_mmio_tail */
/* 0x0220: nve4_unk_mmio_head */
0x00000024,
0x040000c0,
0x000000e4,
0x14000100,
0x000001d0,
0x040001e0,
}; };
uint32_t nve0_grgpc_code[] = { uint32_t nve0_grgpc_code[] = {
...@@ -396,7 +271,7 @@ uint32_t nve0_grgpc_code[] = { ...@@ -396,7 +271,7 @@ uint32_t nve0_grgpc_code[] = {
0xf10004fe, 0xf10004fe,
0xf0120017, 0xf0120017,
0x12d00227, 0x12d00227,
0x5417f100, 0x2317f100,
0x0010fe04, 0x0010fe04,
0x040017f1, 0x040017f1,
0xf0c010d0, 0xf0c010d0,
...@@ -408,169 +283,167 @@ uint32_t nve0_grgpc_code[] = { ...@@ -408,169 +283,167 @@ uint32_t nve0_grgpc_code[] = {
0x1f24f001, 0x1f24f001,
0xb60432bb, 0xb60432bb,
0x02800132, 0x02800132,
0x04038003, 0x06038005,
0x040010b7, 0x040010b7,
0x800012cf, 0x800012cf,
0x27f10002, 0x27f10402,
0x24b60800, 0x24b60800,
0x0022cf06, 0x4022cf06,
/* 0x035f: init_find_chipset */ 0x47f134bd,
0xb66817f0, 0x44b60700,
0x13980c10, 0x08259506,
0x0432b800, 0xd00045d0,
0xb00b0bf4, 0x0e984045,
0x1bf40034, 0x010f9800,
/* 0x0373: init_context */ 0x013d21f5,
0xf100f8f1, 0xbb002fbb,
0xb6080027, 0x0e98003f,
0x22cf0624, 0x020f9801,
0xf134bd40, 0x013d21f5,
0xb6070047, 0xfd050e98,
0x25950644, 0x2ebb00ef,
0x0045d008, 0x003ebb00,
0xbd4045d0, 0x98020e98,
0x58f4bde4, 0x21f5030f,
0x1f58021e, 0x0e98013d,
0x020e4003, 0x00effd07,
0xf5040f40, 0xbb002ebb,
0xbb013d21, 0x40b7003e,
0x3fbb002f, 0x35b61300,
0x041e5800, 0x0043d002,
0x40051f58, 0xb60825b6,
0x0f400a0e, 0x20b60635,
0x3d21f50c, 0x0130b601,
0x030e9801, 0xb60824b6,
0xbb00effd, 0x2fb90834,
0x3ebb002e, 0x6321f502,
0x090e9800, 0x003fbb02,
0xf50a0f98, 0x080017f1,
0x98013d21, 0xd00614b6,
0xeffd070e, 0x10b74013,
0x002ebb00, 0x24bd0800,
0xb7003ebb, 0xd01f29f0,
0xb6130040, /* 0x03e6: main */
0x43d00235, 0x31f40012,
0x0825b600, 0x0028f400,
0xb60635b6, 0xf424d7f0,
0x30b60120, 0x01f43921,
0x0824b601, 0x04e4b0f4,
0xb90834b6, 0xfe1e18f4,
0x21f5022f, 0x27f00181,
0x3fbb0263, 0xfd20bd06,
0x0017f100, 0xe4b60412,
0x0614b608, 0x051efd01,
0xb74013d0, 0xf50018fe,
0xbd080010, 0xf404a821,
0x1f29f024, /* 0x0416: main_not_ctx_xfer */
/* 0x0417: main */ 0xef94d30e,
0xf40012d0, 0x01f5f010,
0x28f40031, 0x02ec21f5,
0x2cd7f000, /* 0x0423: ih */
0xf43921f4, 0xf9c60ef4,
0xe4b0f401, 0x0188fe80,
0x1e18f404, 0x90f980f9,
0xf00181fe, 0xb0f9a0f9,
0x20bd0627, 0xe0f9d0f9,
0xb60412fd, 0x0acff0f9,
0x1efd01e4, 0x04abc480,
0x0018fe05, 0xf11d0bf4,
0x04d921f5, 0xf01900b7,
/* 0x0447: main_not_ctx_xfer */ 0xbecf24d7,
0x94d30ef4, 0x00bfcf40,
0xf5f010ef, 0xb70421f4,
0xec21f501, 0xf00400b0,
0xc60ef402, 0xbed001e7,
/* 0x0454: ih */ /* 0x0459: ih_no_fifo */
0x88fe80f9, 0x400ad000,
0xf980f901, 0xe0fcf0fc,
0xf9a0f990, 0xb0fcd0fc,
0xf9d0f9b0, 0x90fca0fc,
0xcff0f9e0, 0x88fe80fc,
0xabc4800a, 0xf480fc00,
0x1d0bf404, 0x01f80032,
0x1900b7f1, /* 0x0474: hub_barrier_done */
0xcf2cd7f0, 0x9801f7f0,
0xbfcf40be, 0xfebb040e,
0x0421f400, 0x18e7f104,
0x0400b0b7, 0x40e3f094,
0xd001e7f0, 0xf88d21f4,
/* 0x048a: ih_no_fifo */ /* 0x0489: ctx_redswitch */
0x0ad000be, 0x14e7f100,
0xfcf0fc40, 0x06e4b606,
0xfcd0fce0, 0xd020f7f0,
0xfca0fcb0, 0xf7f000ef,
0xfe80fc90, /* 0x0499: ctx_redswitch_delay */
0x80fc0088, 0x01f2b608,
0xf80032f4, 0xf1fd1bf4,
/* 0x04a5: hub_barrier_done */ 0xd00a20f7,
0x01f7f001, 0x00f800ef,
0xbb000e98, /* 0x04a8: ctx_xfer */
0xe7f104fe, 0x0a0417f1,
0xe3f09418, 0xd00614b6,
0x8d21f440, 0x11f4001f,
/* 0x04ba: ctx_redswitch */ 0x8921f507,
0xe7f100f8, /* 0x04b9: ctx_xfer_not_load */
0xe4b60614, 0xfc17f104,
0x20f7f006,
0xf000efd0,
/* 0x04ca: ctx_redswitch_delay */
0xf2b608f7,
0xfd1bf401,
0x0a20f7f1,
0xf800efd0,
/* 0x04d9: ctx_xfer */
0x0417f100,
0x0614b60a,
0xf4001fd0,
0x21f50711,
/* 0x04ea: ctx_xfer_not_load */
0x17f104ba,
0x13f04afc,
0x0c27f002,
0xf50012d0,
0xf1020721,
0xf047fc27,
0x20d00223,
0x012cf000,
0xd00320b6,
0xacf00012,
0x02a5f001,
0xf000b7f0,
0x0c9850b3,
0x0fc4b600,
0x9800bcbb,
0x0d98010c,
0x00e7f002,
0x015c21f5,
0xf101acf0,
0xf04000b7,
0x0c9850b3,
0x0fc4b600,
0x9800bcbb,
0x0d98050c,
0x040f9806,
0x0800e7f1,
0x015c21f5,
0xf001acf0,
0xb7f104a5,
0xb3f03000,
0x000c9850,
0xbb0fc4b6,
0x0c9800bc,
0x0a0d9809,
0xf1080f98,
0xf50200e7,
0xf5015c21,
0xf4020721,
0x12f40601,
/* 0x0585: ctx_xfer_post */
0xfc17f114,
0x0213f04a, 0x0213f04a,
0xd00d27f0, 0xd00c27f0,
0x21f50012, 0x21f50012,
/* 0x0596: ctx_xfer_done */ 0x27f10207,
0x21f50207, 0x23f047fc,
0x00f804a5, 0x0020d002,
0xb6012cf0,
0x12d00320,
0x01acf000,
0xf002a5f0,
0xb3f000b7,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x010d9800,
0xf500e7f0,
0xf0015c21,
0xb7f101ac,
0xb3f04000,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x020d9801,
0xf1060f98,
0xf50800e7,
0xf0015c21,
0xa5f001ac,
0x00b7f104,
0x50b3f030,
0xb6040c98,
0xbcbb0fc4,
0x020c9800,
0x98030d98,
0xe7f1080f,
0x21f50200,
0x21f5015c,
0x01f40207,
0x1412f406,
/* 0x0554: ctx_xfer_post */
0x4afc17f1,
0xf00213f0,
0x12d00d27,
0x0721f500,
/* 0x0565: ctx_xfer_done */
0x7421f502,
0x0000f804,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
View file @ a32b2ffb
...@@ -24,11 +24,12 @@ ...@@ -24,11 +24,12 @@
*/ */
#ifdef INCLUDE_DATA #ifdef INCLUDE_DATA
hub_mmio_list_head: .b32 #hub_mmio_list_base
hub_mmio_list_tail: .b32 #hub_mmio_list_next
gpc_count: .b32 0 gpc_count: .b32 0
rop_count: .b32 0 rop_count: .b32 0
cmd_queue: queue_init cmd_queue: queue_init
hub_mmio_list_head: .b32 0
hub_mmio_list_tail: .b32 0
ctx_current: .b32 0 ctx_current: .b32 0
...@@ -40,6 +41,9 @@ chan_mmio_address: .b32 0 ...@@ -40,6 +41,9 @@ chan_mmio_address: .b32 0
.align 256 .align 256
xfer_data: .skip 256 xfer_data: .skip 256
hub_mmio_list_base:
.b32 0x0417e91c // 0x17e91c, 2
hub_mmio_list_next:
#endif #endif
#ifdef INCLUDE_CODE #ifdef INCLUDE_CODE
...@@ -62,9 +66,6 @@ error: ...@@ -62,9 +66,6 @@ error:
// HUB fuc initialisation, executed by triggering ucode start, will // HUB fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion. // fall through to main loop after completion.
// //
// Input:
// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
//
// Output: // Output:
// CC_SCRATCH[0]: // CC_SCRATCH[0]:
// 31:31: set to signal completion // 31:31: set to signal completion
...@@ -141,31 +142,12 @@ init: ...@@ -141,31 +142,12 @@ init:
iowr I[$r2 + 0x000] $r1 iowr I[$r2 + 0x000] $r1
iowr I[$r2 + 0x100] $r1 iowr I[$r2 + 0x100] $r1
// find context data for this chipset
mov $r2 0x800
shl b32 $r2 6
iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
mov $r15 #chipsets - 8
init_find_chipset:
add b32 $r15 8
ld b32 $r3 D[$r15 + 0x00]
cmpu b32 $r3 $r2
bra e #init_context
cmpu b32 $r3 0
bra ne #init_find_chipset
// unknown chipset
ret
// context size calculation, reserve first 256 bytes for use by fuc // context size calculation, reserve first 256 bytes for use by fuc
init_context:
mov $r1 256 mov $r1 256
// calculate size of mmio context data // calculate size of mmio context data
ld b16 $r14 D[$r15 + 4] ld b32 $r14 D[$r0 + #hub_mmio_list_head]
ld b16 $r15 D[$r15 + 6] ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
sethi $r14 0
st b32 D[$r0 + #hub_mmio_list_head] $r14
st b32 D[$r0 + #hub_mmio_list_tail] $r15
call #mmctx_size call #mmctx_size
// set mmctx base addresses now so we don't have to do it later, // set mmctx base addresses now so we don't have to do it later,
...@@ -204,9 +186,6 @@ init: ...@@ -204,9 +186,6 @@ init:
add b32 $r14 $r4 0x804 add b32 $r14 $r4 0x804
mov b32 $r15 $r1 mov b32 $r15 $r1
call #nv_wr32 // CC_SCRATCH[1] = ctx offset call #nv_wr32 // CC_SCRATCH[1] = ctx offset
add b32 $r14 $r4 0x800
mov b32 $r15 $r2
call #nv_wr32 // CC_SCRATCH[0] = chipset
add b32 $r14 $r4 0x10c add b32 $r14 $r4 0x10c
clear b32 $r15 clear b32 $r15
call #nv_wr32 call #nv_wr32
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
View file @ a32b2ffb
...@@ -29,85 +29,6 @@ ...@@ -29,85 +29,6 @@
#define INCLUDE_DATA #define INCLUDE_DATA
#include "com.fuc" #include "com.fuc"
#include "hub.fuc" #include "hub.fuc"
chipsets:
.b8 0xc0 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xc1 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc1_hub_mmio_tail
.b8 0xc3 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xc4 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xc8 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xce 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xcf 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xd9 0 0 0
.b16 #nvd9_hub_mmio_head
.b16 #nvd9_hub_mmio_tail
.b8 0xd7 0 0 0
.b16 #nvd9_hub_mmio_head
.b16 #nvd9_hub_mmio_tail
.b8 0 0 0 0
nvc0_hub_mmio_head:
mmctx_data(0x40402c, 1)
mmctx_data(0x404174, 1)
nvd9_hub_mmio_head:
mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2)
mmctx_data(0x404004, 10)
mmctx_data(0x404044, 1)
mmctx_data(0x404094, 14)
mmctx_data(0x4040d0, 7)
mmctx_data(0x4040f8, 1)
mmctx_data(0x404130, 3)
mmctx_data(0x404150, 3)
mmctx_data(0x404164, 2)
mmctx_data(0x404178, 2)
mmctx_data(0x404200, 8)
mmctx_data(0x404404, 14)
mmctx_data(0x404460, 4)
mmctx_data(0x404480, 1)
mmctx_data(0x404498, 1)
mmctx_data(0x404604, 4)
mmctx_data(0x404618, 32)
mmctx_data(0x404698, 21)
mmctx_data(0x4046f0, 2)
mmctx_data(0x404700, 22)
mmctx_data(0x405800, 1)
mmctx_data(0x405830, 3)
mmctx_data(0x405854, 1)
mmctx_data(0x405870, 4)
mmctx_data(0x405a00, 2)
mmctx_data(0x405a18, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 2)
mmctx_data(0x4064b4, 2)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
mmctx_data(0x408000, 7)
mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
nvc0_hub_mmio_tail:
mmctx_data(0x4064c0, 2)
nvc1_hub_mmio_tail:
mmctx_data(0x4064bc, 3)
nvd9_hub_mmio_tail:
#undef INCLUDE_DATA #undef INCLUDE_DATA
.section #nvc0_grhub_code .section #nvc0_grhub_code
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
View file @ a32b2ffb
...@@ -29,131 +29,6 @@ ...@@ -29,131 +29,6 @@
#define INCLUDE_DATA #define INCLUDE_DATA
#include "com.fuc" #include "com.fuc"
#include "hub.fuc" #include "hub.fuc"
chipsets:
.b8 0xe4 0 0 0
.b16 #nve4_hub_mmio_head
.b16 #nve4_hub_mmio_tail
.b8 0xe7 0 0 0
.b16 #nve4_hub_mmio_head
.b16 #nve4_hub_mmio_tail
.b8 0xe6 0 0 0
.b16 #nve4_hub_mmio_head
.b16 #nve4_hub_mmio_tail
.b8 0xf0 0 0 0
.b16 #nvf0_hub_mmio_head
.b16 #nvf0_hub_mmio_tail
.b8 0 0 0 0
nve4_hub_mmio_head:
mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2)
mmctx_data(0x404010, 7)
mmctx_data(0x4040a8, 9)
mmctx_data(0x4040d0, 7)
mmctx_data(0x4040f8, 1)
mmctx_data(0x404130, 3)
mmctx_data(0x404150, 3)
mmctx_data(0x404164, 1)
mmctx_data(0x4041a0, 4)
mmctx_data(0x404200, 4)
mmctx_data(0x404404, 14)
mmctx_data(0x404460, 4)
mmctx_data(0x404480, 1)
mmctx_data(0x404498, 1)
mmctx_data(0x404604, 4)
mmctx_data(0x404618, 4)
mmctx_data(0x40462c, 2)
mmctx_data(0x404640, 1)
mmctx_data(0x404654, 1)
mmctx_data(0x404660, 1)
mmctx_data(0x404678, 19)
mmctx_data(0x4046c8, 3)
mmctx_data(0x404700, 3)
mmctx_data(0x404718, 10)
mmctx_data(0x404744, 2)
mmctx_data(0x404754, 1)
mmctx_data(0x405800, 1)
mmctx_data(0x405830, 3)
mmctx_data(0x405854, 1)
mmctx_data(0x405870, 4)
mmctx_data(0x405a00, 2)
mmctx_data(0x405a18, 1)
mmctx_data(0x405b00, 1)
mmctx_data(0x405b10, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 2)
mmctx_data(0x4064b4, 2)
mmctx_data(0x4064c0, 12)
mmctx_data(0x4064fc, 1)
mmctx_data(0x407040, 1)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
mmctx_data(0x408000, 7)
mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408840, 1)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
nve4_hub_mmio_tail:
nvf0_hub_mmio_head:
mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2)
mmctx_data(0x404004, 17)
mmctx_data(0x4040a8, 9)
mmctx_data(0x4040d0, 7)
mmctx_data(0x4040f8, 1)
mmctx_data(0x404100, 10)
mmctx_data(0x404130, 3)
mmctx_data(0x404150, 3)
mmctx_data(0x404164, 1)
mmctx_data(0x40417c, 2)
mmctx_data(0x4041a0, 4)
mmctx_data(0x404200, 4)
mmctx_data(0x404404, 12)
mmctx_data(0x404438, 1)
mmctx_data(0x404460, 4)
mmctx_data(0x404480, 1)
mmctx_data(0x404498, 1)
mmctx_data(0x404604, 4)
mmctx_data(0x404618, 4)
mmctx_data(0x40462c, 2)
mmctx_data(0x404640, 1)
mmctx_data(0x404654, 1)
mmctx_data(0x404660, 1)
mmctx_data(0x404678, 19)
mmctx_data(0x4046c8, 3)
mmctx_data(0x404700, 3)
mmctx_data(0x404718, 10)
mmctx_data(0x404744, 2)
mmctx_data(0x404754, 1)
mmctx_data(0x405800, 1)
mmctx_data(0x405830, 3)
mmctx_data(0x405854, 1)
mmctx_data(0x405870, 4)
mmctx_data(0x405a00, 2)
mmctx_data(0x405a18, 1)
mmctx_data(0x405b00, 1)
mmctx_data(0x405b10, 1)
mmctx_data(0x405b20, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 5)
mmctx_data(0x4064c0, 12)
mmctx_data(0x4064fc, 1)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
mmctx_data(0x408000, 7)
mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408840, 1)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
nvf0_hub_mmio_tail:
#undef INCLUDE_DATA #undef INCLUDE_DATA
.section #nve0_grhub_code .section #nve0_grhub_code
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @ a32b2ffb
...@@ -764,10 +764,46 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, ...@@ -764,10 +764,46 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
} }
} }
static void
nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
struct nvc0_graph_init *init,
u32 falcon, u32 starstar, u32 base)
{
u32 addr = init->addr;
u32 next = addr;
u32 star, temp;
nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
star = nv_rd32(priv, falcon + 0x01c4);
temp = nv_rd32(priv, falcon + 0x01c4);
if (temp > star)
star = temp;
nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
do {
if (init->addr != next) {
while (addr < next) {
u32 nr = min((int)(next - addr) / 4, 32);
nv_wr32(priv, falcon + 0x01c4,
((nr - 1) << 26) | (addr - base));
addr += nr * 4;
star += 4;
}
addr = next = init->addr;
}
next += init->count * 4;
} while ((init++)->count);
nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
nv_wr32(priv, falcon + 0x01c4, star);
}
int int
nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
{ {
struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass; struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
struct nvc0_graph_init *init;
u32 r000260; u32 r000260;
int i; int i;
...@@ -874,6 +910,10 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) ...@@ -874,6 +910,10 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
} }
for (i = 0; (init = cclass->hub[i]); i++) {
nvc0_graph_init_csdata(priv, init, 0x409000, 0x000, 0x000000);
}
/* load GPC microcode */ /* load GPC microcode */
nv_wr32(priv, 0x41a1c0, 0x01000000); nv_wr32(priv, 0x41a1c0, 0x01000000);
for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
...@@ -887,8 +927,14 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) ...@@ -887,8 +927,14 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
} }
nv_wr32(priv, 0x000260, r000260); nv_wr32(priv, 0x000260, r000260);
if ((init = cclass->gpc[0]))
nvc0_graph_init_csdata(priv, init, 0x41a000, 0x000, 0x418000);
if ((init = cclass->gpc[2]))
nvc0_graph_init_csdata(priv, init, 0x41a000, 0x004, 0x419800);
if ((init = cclass->gpc[3]))
nvc0_graph_init_csdata(priv, init, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */ /* start HUB ucode running, it'll init the GPCs */
nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
nv_wr32(priv, 0x40910c, 0x00000000); nv_wr32(priv, 0x40910c, 0x00000000);
nv_wr32(priv, 0x409100, 0x00000002); nv_wr32(priv, 0x409100, 0x00000002);
if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
......
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