Commit a379e16a authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-next

 - Use ARRAY_SIZE in qcom clk drivers
 - Remove some impractical fallback parent names in qcom clk drivers
 - GCC and RPMcc support for Qualcomm QCM2290 SoCs
 - GCC support for Qualcomm MSM8994/MSM8992 SoCs
 - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
 - Support for Mediatek MT8195 SoCs
 - Make Mediatek clk drivers tristate

* clk-qcom: (44 commits)
  clk: qcom: gdsc: enable optional power domain support
  clk: qcom: videocc-sm8250: use runtime PM for the clock controller
  clk: qcom: dispcc-sm8250: use runtime PM for the clock controller
  dt-bindings: clock: qcom,videocc: add mmcx power domain
  dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain
  clk: qcom: gcc-sc7280: Drop unused array
  clk: qcom: camcc: Add camera clock controller driver for SC7280
  dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280
  clk: qcom: Add lpass clock controller driver for SC7280
  dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280
  clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180
  clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc
  clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc
  clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents
  clk: qcom: gcc-msm8994: Add proper msm8992 support
  clk: qcom: gcc-msm8994: Add modem reset
  clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE
  clk: qcom: gcc-msm8994: Add missing clocks
  clk: qcom: gcc-msm8994: Add missing NoC clocks
  clk: qcom: gcc-msm8994: Fix up SPI QUP clocks
  ...

* clk-mtk: (28 commits)
  clk: mediatek: Export clk_ops structures to modules
  clk: mediatek: support COMMON_CLK_MT6779 module build
  clk: mediatek: support COMMON_CLK_MEDIATEK module build
  clk: composite: export clk_register_composite
  clk: mediatek: Add MT8195 apusys clock support
  clk: mediatek: Add MT8195 imp i2c wrapper clock support
  clk: mediatek: Add MT8195 wpesys clock support
  clk: mediatek: Add MT8195 vppsys1 clock support
  clk: mediatek: Add MT8195 vppsys0 clock support
  clk: mediatek: Add MT8195 vencsys clock support
  clk: mediatek: Add MT8195 vdosys1 clock support
  clk: mediatek: Add MT8195 vdosys0 clock support
  clk: mediatek: Add MT8195 vdecsys clock support
  clk: mediatek: Add MT8195 scp adsp clock support
  clk: mediatek: Add MT8195 mfgcfg clock support
  clk: mediatek: Add MT8195 ipesys clock support
  clk: mediatek: Add MT8195 imgsys clock support
  clk: mediatek: Add MT8195 ccusys clock support
  clk: mediatek: Add MT8195 camsys clock support
  clk: mediatek: Add MT8195 infrastructure clock support
  ...

* clk-versatile:
  clk: versatile: hide clock drivers from non-ARM users
  clk: versatile: Rename ICST to CLK_ICST
  clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address
  dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address

* clk-doc:
  dt-bindings: clk: fixed-mmio-clock: Convert to YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek Functional Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The devices except apusys_pll provide clock gate control in different IP blocks.
The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-scp_adsp
- mediatek,mt8195-imp_iic_wrap_s
- mediatek,mt8195-imp_iic_wrap_w
- mediatek,mt8195-mfgcfg
- mediatek,mt8195-vppsys0
- mediatek,mt8195-wpesys
- mediatek,mt8195-wpesys_vpp0
- mediatek,mt8195-wpesys_vpp1
- mediatek,mt8195-vppsys1
- mediatek,mt8195-imgsys
- mediatek,mt8195-imgsys1_dip_top
- mediatek,mt8195-imgsys1_dip_nr
- mediatek,mt8195-imgsys1_wpe
- mediatek,mt8195-ipesys
- mediatek,mt8195-camsys
- mediatek,mt8195-camsys_rawa
- mediatek,mt8195-camsys_yuva
- mediatek,mt8195-camsys_rawb
- mediatek,mt8195-camsys_yuvb
- mediatek,mt8195-camsys_mraw
- mediatek,mt8195-ccusys
- mediatek,mt8195-vdecsys_soc
- mediatek,mt8195-vdecsys
- mediatek,mt8195-vdecsys_core1
- mediatek,mt8195-vencsys
- mediatek,mt8195-vencsys_core1
- mediatek,mt8195-apusys_pll
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0x10720000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_s: clock-controller@11d03000 {
compatible = "mediatek,mt8195-imp_iic_wrap_s";
reg = <0x11d03000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_w: clock-controller@11e05000 {
compatible = "mediatek,mt8195-imp_iic_wrap_w";
reg = <0x11e05000 0x1000>;
#clock-cells = <1>;
};
- |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8195-mfgcfg";
reg = <0x13fbf000 0x1000>;
#clock-cells = <1>;
};
- |
vppsys0: clock-controller@14000000 {
compatible = "mediatek,mt8195-vppsys0";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0x14e00000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp0: clock-controller@14e02000 {
compatible = "mediatek,mt8195-wpesys_vpp0";
reg = <0x14e02000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp1: clock-controller@14e03000 {
compatible = "mediatek,mt8195-wpesys_vpp1";
reg = <0x14e03000 0x1000>;
#clock-cells = <1>;
};
- |
vppsys1: clock-controller@14f00000 {
compatible = "mediatek,mt8195-vppsys1";
reg = <0x14f00000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0x15000000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0x15110000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0x15130000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_wpe: clock-controller@15220000 {
compatible = "mediatek,mt8195-imgsys1_wpe";
reg = <0x15220000 0x1000>;
#clock-cells = <1>;
};
- |
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0x15330000 0x1000>;
#clock-cells = <1>;
};
- |
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0x16000000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0x1604f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuva: clock-controller@1606f000 {
compatible = "mediatek,mt8195-camsys_yuva";
reg = <0x1606f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawb: clock-controller@1608f000 {
compatible = "mediatek,mt8195-camsys_rawb";
reg = <0x1608f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuvb: clock-controller@160af000 {
compatible = "mediatek,mt8195-camsys_yuvb";
reg = <0x160af000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_mraw: clock-controller@16140000 {
compatible = "mediatek,mt8195-camsys_mraw";
reg = <0x16140000 0x1000>;
#clock-cells = <1>;
};
- |
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0x17200000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0x1800f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0x1802f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0x1803f000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys: clock-controller@1a000000 {
compatible = "mediatek,mt8195-vencsys";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
};
- |
apusys_pll: clock-controller@190f3000 {
compatible = "mediatek,mt8195-apusys_pll";
reg = <0x190f3000 0x1000>;
#clock-cells = <1>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek System Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys provides most of PLLs which generated from SoC 26m.
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-topckgen
- mediatek,mt8195-infracfg_ao
- mediatek,mt8195-apmixedsys
- mediatek,mt8195-pericfg_ao
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8195-topckgen", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};
- |
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8195-infracfg_ao", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
};
- |
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8195-apmixedsys", "syscon";
reg = <0x1000c000 0x1000>;
#clock-cells = <1>;
};
- |
pericfg_ao: syscon@11003000 {
compatible = "mediatek,mt8195-pericfg_ao", "syscon";
reg = <0x11003000 0x1000>;
#clock-cells = <1>;
};
......@@ -69,6 +69,10 @@ properties:
- arm,impd1-vco1
- arm,impd1-vco2
reg:
maxItems: 1
description: The VCO register
clocks:
description: Parent clock for the ICST VCO
maxItems: 1
......@@ -83,6 +87,7 @@ properties:
vco-offset:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: Offset to the VCO register for the oscillator
deprecated: true
required:
- "#clock-cells"
......
Binding for simple memory mapped io fixed-rate clock sources.
The driver reads a clock frequency value from a single 32-bit memory mapped
I/O register and registers it as a fixed rate clock.
It was designed for test systems, like FPGA, not for complete, finished SoCs.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "fixed-mmio-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- reg : Address and length of the clock value register set.
Optional properties:
- clock-output-names : From common clock binding.
Example:
sysclock: sysclock@fd020004 {
#clock-cells = <0>;
compatible = "fixed-mmio-clock";
reg = <0xfd020004 0x4>;
};
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for simple memory mapped IO fixed-rate clock sources
description:
This binding describes a fixed-rate clock for which the frequency can
be read from a single 32-bit memory mapped I/O register.
It was designed for test systems, like FPGA, not for complete,
finished SoCs.
maintainers:
- Jan Kotas <jank@cadence.com>
properties:
compatible:
const: fixed-mmio-clock
reg:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
sysclock: sysclock@fd020004 {
compatible = "fixed-mmio-clock";
#clock-cells = <0>;
reg = <0xfd020004 0x4>;
clock-output-names = "sysclk";
};
...
......@@ -6,7 +6,7 @@ menuconfig ARCH_INTEGRATOR
select CMA
select DMA_CMA
select HAVE_TCM
select ICST
select CLK_ICST
select MFD_SYSCON
select PLAT_VERSATILE
select POWER_RESET
......
......@@ -11,7 +11,7 @@ menuconfig ARCH_REALVIEW
select HAVE_ARM_TWD if SMP
select HAVE_PATA_PLATFORM
select HAVE_TCM
select ICST
select CLK_ICST
select MACH_REALVIEW_EB if ARCH_MULTI_V5
select MFD_SYSCON
select PLAT_VERSATILE
......
......@@ -7,7 +7,7 @@ config ARCH_VERSATILE
select ARM_VIC
select CLKSRC_VERSATILE
select CPU_ARM926T
select ICST
select CLK_ICST
select MFD_SYSCON
select PLAT_VERSATILE
select POWER_RESET
......
......@@ -11,7 +11,7 @@ menuconfig ARCH_VEXPRESS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_PATA_PLATFORM
select ICST
select CLK_ICST
select NO_IOPORT_MAP
select PLAT_VERSATILE
select POWER_RESET
......
......@@ -362,6 +362,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
return ERR_CAST(hw);
return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_composite);
struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
const struct clk_parent_data *parent_data,
......
......@@ -6,7 +6,7 @@ menu "Clock driver for MediaTek SoC"
depends on ARCH_MEDIATEK || COMPILE_TEST
config COMMON_CLK_MEDIATEK
bool
tristate
select RESET_CONTROLLER
help
MediaTek SoCs' clock support.
......@@ -204,7 +204,7 @@ config COMMON_CLK_MT6765_MIPI2BSYS
This driver supports MediaTek MT6765 mipi2bsys clocks.
config COMMON_CLK_MT6779
bool "Clock driver for MediaTek MT6779"
tristate "Clock driver for MediaTek MT6779"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK && ARM64
......@@ -212,49 +212,49 @@ config COMMON_CLK_MT6779
This driver supports MediaTek MT6779 basic clocks.
config COMMON_CLK_MT6779_MMSYS
bool "Clock driver for MediaTek MT6779 mmsys"
tristate "Clock driver for MediaTek MT6779 mmsys"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 mmsys clocks.
config COMMON_CLK_MT6779_IMGSYS
bool "Clock driver for MediaTek MT6779 imgsys"
tristate "Clock driver for MediaTek MT6779 imgsys"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 imgsys clocks.
config COMMON_CLK_MT6779_IPESYS
bool "Clock driver for MediaTek MT6779 ipesys"
tristate "Clock driver for MediaTek MT6779 ipesys"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 ipesys clocks.
config COMMON_CLK_MT6779_CAMSYS
bool "Clock driver for MediaTek MT6779 camsys"
tristate "Clock driver for MediaTek MT6779 camsys"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 camsys clocks.
config COMMON_CLK_MT6779_VDECSYS
bool "Clock driver for MediaTek MT6779 vdecsys"
tristate "Clock driver for MediaTek MT6779 vdecsys"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 vdecsys clocks.
config COMMON_CLK_MT6779_VENCSYS
bool "Clock driver for MediaTek MT6779 vencsys"
tristate "Clock driver for MediaTek MT6779 vencsys"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 vencsys clocks.
config COMMON_CLK_MT6779_MFGCFG
bool "Clock driver for MediaTek MT6779 mfgcfg"
tristate "Clock driver for MediaTek MT6779 mfgcfg"
depends on COMMON_CLK_MT6779
help
This driver supports MediaTek MT6779 mfgcfg clocks.
config COMMON_CLK_MT6779_AUDSYS
bool "Clock driver for Mediatek MT6779 audsys"
tristate "Clock driver for Mediatek MT6779 audsys"
depends on COMMON_CLK_MT6779
help
This driver supports Mediatek MT6779 audsys clocks.
......@@ -575,6 +575,14 @@ config COMMON_CLK_MT8192_VENCSYS
help
This driver supports MediaTek MT8192 vencsys clocks.
config COMMON_CLK_MT8195
bool "Clock driver for MediaTek MT8195"
depends on ARM64 || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK
help
This driver supports MediaTek MT8195 clocks.
config COMMON_CLK_MT8516
bool "Clock driver for MediaTek MT8516"
depends on ARCH_MEDIATEK || COMPILE_TEST
......
......@@ -80,5 +80,13 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \
clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o \
clk-mt8195-ipe.o clk-mt8195-mfg.o clk-mt8195-scp_adsp.o \
clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o \
clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \
clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \
clk-mt8195-apusys_pll.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
......@@ -5,6 +5,7 @@
*/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>
......@@ -97,3 +98,5 @@ struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
return clk;
}
MODULE_LICENSE("GPL");
......@@ -6,6 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/slab.h>
#include "clk-mtk.h"
......@@ -106,3 +107,5 @@ int mtk_clk_register_cpumuxes(struct device_node *node,
return 0;
}
MODULE_LICENSE("GPL");
......@@ -11,6 +11,7 @@
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/clkdev.h>
#include <linux/module.h>
#include "clk-mtk.h"
#include "clk-gate.h"
......@@ -122,24 +123,28 @@ const struct clk_ops mtk_clk_gate_ops_setclr = {
.enable = mtk_cg_enable,
.disable = mtk_cg_disable,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv,
.disable = mtk_cg_disable_inv,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
const struct clk_ops mtk_clk_gate_ops_no_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable_no_setclr,
.disable = mtk_cg_disable_no_setclr,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr);
const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv_no_setclr,
.disable = mtk_cg_disable_inv_no_setclr,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
struct clk *mtk_clk_register_gate(
const char *name,
......@@ -181,3 +186,6 @@ struct clk *mtk_clk_register_gate(
return clk;
}
EXPORT_SYMBOL_GPL(mtk_clk_register_gate);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
......@@ -114,4 +115,5 @@ static struct platform_driver clk_mt6779_aud_drv = {
},
};
builtin_platform_driver(clk_mt6779_aud_drv);
module_platform_driver(clk_mt6779_aud_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
......@@ -63,4 +64,5 @@ static struct platform_driver clk_mt6779_cam_drv = {
},
};
builtin_platform_driver(clk_mt6779_cam_drv);
module_platform_driver(clk_mt6779_cam_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
......@@ -55,4 +56,5 @@ static struct platform_driver clk_mt6779_img_drv = {
},
};
builtin_platform_driver(clk_mt6779_img_drv);
module_platform_driver(clk_mt6779_img_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
......@@ -57,4 +58,5 @@ static struct platform_driver clk_mt6779_ipe_drv = {
},
};
builtin_platform_driver(clk_mt6779_ipe_drv);
module_platform_driver(clk_mt6779_ipe_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
......@@ -52,4 +53,5 @@ static struct platform_driver clk_mt6779_mfg_drv = {
},
};
builtin_platform_driver(clk_mt6779_mfg_drv);
module_platform_driver(clk_mt6779_mfg_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
......@@ -105,4 +106,5 @@ static struct platform_driver clk_mt6779_mm_drv = {
},
};
builtin_platform_driver(clk_mt6779_mm_drv);
module_platform_driver(clk_mt6779_mm_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
......@@ -64,4 +65,5 @@ static struct platform_driver clk_mt6779_vdec_drv = {
},
};
builtin_platform_driver(clk_mt6779_vdec_drv);
module_platform_driver(clk_mt6779_vdec_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
......@@ -55,4 +56,5 @@ static struct platform_driver clk_mt6779_venc_drv = {
},
};
builtin_platform_driver(clk_mt6779_venc_drv);
module_platform_driver(clk_mt6779_venc_drv);
MODULE_LICENSE("GPL");
......@@ -4,6 +4,7 @@
* Author: Wendell Lin <wendell.lin@mediatek.com>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
......@@ -1314,3 +1315,4 @@ static int __init clk_mt6779_init(void)
}
arch_initcall(clk_mt6779_init);
MODULE_LICENSE("GPL");
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x8,
.sta_ofs = 0x8,
};
#define GATE_APMIXED(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate apmixed_clks[] = {
GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
};
#define MT8195_PLL_FMAX (3800UL * MHZ)
#define MT8195_PLL_FMIN (1500UL * MHZ)
#define MT8195_INTEGER_BITS 8
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
_pcw_reg, _pcw_shift, _pcw_chg_reg, \
_en_reg, _pll_en_bit) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8195_PLL_FMAX, \
.fmin = MT8195_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = MT8195_INTEGER_BITS, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.en_reg = _en_reg, \
.pll_en_bit = _pll_en_bit, \
}
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
};
static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
{ .compatible = "mediatek,mt8195-apmixedsys", },
{}
};
static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
if (r)
goto free_apmixed_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
goto free_apmixed_data;
return r;
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt8195_apmixed_drv = {
.probe = clk_mt8195_apmixed_probe,
.driver = {
.name = "clk-mt8195-apmixed",
.of_match_table = of_match_clk_mt8195_apmixed,
},
};
builtin_platform_driver(clk_mt8195_apmixed_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#define MT8195_PLL_FMAX (3800UL * MHZ)
#define MT8195_PLL_FMIN (1500UL * MHZ)
#define MT8195_INTEGER_BITS (8)
#define MT8195_PCW_BITS (22)
#define MT8195_POSDIV_SHIFT (24)
#define MT8195_PLL_EN_BIT (0)
#define MT8195_PCW_SHIFT (0)
/*
* The "en_reg" and "pcw_chg_reg" fields are standard offset register compared
* with "reg" field, so set zero to imply it.
* No tuner control in apu pll, so set "tuner_XXX" as zero to imply it.
* No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
* as zero to imply it.
*/
#define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = 0, \
.flags = 0, \
.rst_bar_mask = 0, \
.fmax = MT8195_PLL_FMAX, \
.fmin = MT8195_PLL_FMIN, \
.pcwbits = MT8195_PCW_BITS, \
.pcwibits = MT8195_INTEGER_BITS, \
.pd_reg = _pd_reg, \
.pd_shift = MT8195_POSDIV_SHIFT, \
.tuner_reg = 0, \
.tuner_en_reg = 0, \
.tuner_en_bit = 0, \
.pcw_reg = _pcw_reg, \
.pcw_shift = MT8195_PCW_SHIFT, \
.pcw_chg_reg = 0, \
.en_reg = 0, \
.pll_en_bit = MT8195_PLL_EN_BIT, \
}
static const struct mtk_pll_data apusys_plls[] = {
PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c),
PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c),
PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c),
PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
};
static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
goto free_apusys_pll_data;
return r;
free_apusys_pll_data:
mtk_free_clk_data(clk_data);
return r;
}
static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {
{ .compatible = "mediatek,mt8195-apusys_pll", },
{}
};
static struct platform_driver clk_mt8195_apusys_pll_drv = {
.probe = clk_mt8195_apusys_pll_probe,
.driver = {
.name = "clk-mt8195-apusys_pll",
.of_match_table = of_match_clk_mt8195_apusys_pll,
},
};
builtin_platform_driver(clk_mt8195_apusys_pll_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "top_cam", 0),
GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "top_cam", 1),
GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "top_cam", 3),
GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "top_cam", 4),
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "top_cam", 5),
GATE_CAM(CLK_CAM_GCAMSVA, "cam_gcamsva", "top_cam", 6),
GATE_CAM(CLK_CAM_GCAMSVB, "cam_gcamsvb", "top_cam", 7),
GATE_CAM(CLK_CAM_GCAMSVC, "cam_gcamsvc", "top_cam", 8),
GATE_CAM(CLK_CAM_SCAMSA, "cam_scamsa", "top_cam", 9),
GATE_CAM(CLK_CAM_SCAMSB, "cam_scamsb", "top_cam", 10),
GATE_CAM(CLK_CAM_CAMSV_TOP, "cam_camsv_top", "top_cam", 11),
GATE_CAM(CLK_CAM_CAMSV_CQ, "cam_camsv_cq", "top_cam", 12),
GATE_CAM(CLK_CAM_ADL, "cam_adl", "top_cam", 16),
GATE_CAM(CLK_CAM_ASG, "cam_asg", "top_cam", 17),
GATE_CAM(CLK_CAM_PDA, "cam_pda", "top_cam", 18),
GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "top_cam", 19),
GATE_CAM(CLK_CAM_MAIN_MRAW0, "cam_main_mraw0", "top_cam", 20),
GATE_CAM(CLK_CAM_MAIN_MRAW1, "cam_main_mraw1", "top_cam", 21),
GATE_CAM(CLK_CAM_MAIN_MRAW2, "cam_main_mraw2", "top_cam", 22),
GATE_CAM(CLK_CAM_MAIN_MRAW3, "cam_main_mraw3", "top_cam", 23),
GATE_CAM(CLK_CAM_CAM2MM0_GALS, "cam_cam2mm0_gals", "top_cam", 24),
GATE_CAM(CLK_CAM_CAM2MM1_GALS, "cam_cam2mm1_gals", "top_cam", 25),
GATE_CAM(CLK_CAM_CAM2SYS_GALS, "cam_cam2sys_gals", "top_cam", 26),
};
static const struct mtk_gate cam_mraw_clks[] = {
GATE_CAM(CLK_CAM_MRAW_LARBX, "cam_mraw_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_MRAW_CAMTG, "cam_mraw_camtg", "top_cam", 2),
GATE_CAM(CLK_CAM_MRAW_MRAW0, "cam_mraw_mraw0", "top_cam", 3),
GATE_CAM(CLK_CAM_MRAW_MRAW1, "cam_mraw_mraw1", "top_cam", 4),
GATE_CAM(CLK_CAM_MRAW_MRAW2, "cam_mraw_mraw2", "top_cam", 5),
GATE_CAM(CLK_CAM_MRAW_MRAW3, "cam_mraw_mraw3", "top_cam", 6),
};
static const struct mtk_gate cam_rawa_clks[] = {
GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_rawb_clks[] = {
GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_yuva_clks[] = {
GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_yuvb_clks[] = {
GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct mtk_clk_desc cam_mraw_desc = {
.clks = cam_mraw_clks,
.num_clks = ARRAY_SIZE(cam_mraw_clks),
};
static const struct mtk_clk_desc cam_rawa_desc = {
.clks = cam_rawa_clks,
.num_clks = ARRAY_SIZE(cam_rawa_clks),
};
static const struct mtk_clk_desc cam_rawb_desc = {
.clks = cam_rawb_clks,
.num_clks = ARRAY_SIZE(cam_rawb_clks),
};
static const struct mtk_clk_desc cam_yuva_desc = {
.clks = cam_yuva_clks,
.num_clks = ARRAY_SIZE(cam_yuva_clks),
};
static const struct mtk_clk_desc cam_yuvb_desc = {
.clks = cam_yuvb_clks,
.num_clks = ARRAY_SIZE(cam_yuvb_clks),
};
static const struct of_device_id of_match_clk_mt8195_cam[] = {
{
.compatible = "mediatek,mt8195-camsys",
.data = &cam_desc,
}, {
.compatible = "mediatek,mt8195-camsys_mraw",
.data = &cam_mraw_desc,
}, {
.compatible = "mediatek,mt8195-camsys_rawa",
.data = &cam_rawa_desc,
}, {
.compatible = "mediatek,mt8195-camsys_rawb",
.data = &cam_rawb_desc,
}, {
.compatible = "mediatek,mt8195-camsys_yuva",
.data = &cam_yuva_desc,
}, {
.compatible = "mediatek,mt8195-camsys_yuvb",
.data = &cam_yuvb_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_cam_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-cam",
.of_match_table = of_match_clk_mt8195_cam,
},
};
builtin_platform_driver(clk_mt8195_cam_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs ccu_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CCU(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ccu_clks[] = {
GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "top_ccu", 0),
GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "top_ccu", 3),
};
static const struct mtk_clk_desc ccu_desc = {
.clks = ccu_clks,
.num_clks = ARRAY_SIZE(ccu_clks),
};
static const struct of_device_id of_match_clk_mt8195_ccu[] = {
{
.compatible = "mediatek,mt8195-ccusys",
.data = &ccu_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_ccu_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-ccu",
.of_match_table = of_match_clk_mt8195_ccu,
},
};
builtin_platform_driver(clk_mt8195_ccu_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB9, "img_larb9", "top_img", 0),
GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "top_img", 1),
GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "top_img", 2),
GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "top_img", 3),
GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "top_img", 4),
GATE_IMG(CLK_IMG_DIP0, "img_dip0", "top_img", 8),
GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "top_img", 9),
GATE_IMG(CLK_IMG_IPE, "img_ipe", "top_img", 10),
GATE_IMG(CLK_IMG_DIP1, "img_dip1", "top_img", 11),
GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "top_img", 12),
GATE_IMG(CLK_IMG_GALS, "img_gals", "top_img", 31),
};
static const struct mtk_gate img1_dip_top_clks[] = {
GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "top_img", 0),
GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "top_img", 1),
};
static const struct mtk_gate img1_dip_nr_clks[] = {
GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "top_img", 0),
GATE_IMG(CLK_IMG1_DIP_NR_DIP_NR, "img1_dip_nr_dip_nr", "top_img", 1),
};
static const struct mtk_gate img1_wpe_clks[] = {
GATE_IMG(CLK_IMG1_WPE_LARB11, "img1_wpe_larb11", "top_img", 0),
GATE_IMG(CLK_IMG1_WPE_WPE, "img1_wpe_wpe", "top_img", 1),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct mtk_clk_desc img1_dip_top_desc = {
.clks = img1_dip_top_clks,
.num_clks = ARRAY_SIZE(img1_dip_top_clks),
};
static const struct mtk_clk_desc img1_dip_nr_desc = {
.clks = img1_dip_nr_clks,
.num_clks = ARRAY_SIZE(img1_dip_nr_clks),
};
static const struct mtk_clk_desc img1_wpe_desc = {
.clks = img1_wpe_clks,
.num_clks = ARRAY_SIZE(img1_wpe_clks),
};
static const struct of_device_id of_match_clk_mt8195_img[] = {
{
.compatible = "mediatek,mt8195-imgsys",
.data = &img_desc,
}, {
.compatible = "mediatek,mt8195-imgsys1_dip_top",
.data = &img1_dip_top_desc,
}, {
.compatible = "mediatek,mt8195-imgsys1_dip_nr",
.data = &img1_dip_nr_desc,
}, {
.compatible = "mediatek,mt8195-imgsys1_wpe",
.data = &img1_wpe_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_img_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-img",
.of_match_table = of_match_clk_mt8195_img,
},
};
builtin_platform_driver(clk_mt8195_img_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8195-clk.h>
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,
.sta_ofs = 0xe00,
};
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
static const struct mtk_gate imp_iic_wrap_s_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C5, "imp_iic_wrap_s_i2c5", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C6, "imp_iic_wrap_s_i2c6", "top_i2c", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "top_i2c", 2),
};
static const struct mtk_gate imp_iic_wrap_w_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C0, "imp_iic_wrap_w_i2c0", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C1, "imp_iic_wrap_w_i2c1", "top_i2c", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C2, "imp_iic_wrap_w_i2c2", "top_i2c", 2),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C3, "imp_iic_wrap_w_i2c3", "top_i2c", 3),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C4, "imp_iic_wrap_w_i2c4", "top_i2c", 4),
};
static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
.clks = imp_iic_wrap_s_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
.clks = imp_iic_wrap_w_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
};
static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = {
{
.compatible = "mediatek,mt8195-imp_iic_wrap_s",
.data = &imp_iic_wrap_s_desc,
}, {
.compatible = "mediatek,mt8195-imp_iic_wrap_w",
.data = &imp_iic_wrap_w_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_imp_iic_wrap_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-imp_iic_wrap",
.of_match_table = of_match_clk_mt8195_imp_iic_wrap,
},
};
builtin_platform_driver(clk_mt8195_imp_iic_wrap_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs infra_ao0_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs infra_ao1_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs infra_ao2_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs infra_ao3_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
static const struct mtk_gate_regs infra_ao4_cg_regs = {
.set_ofs = 0xe0,
.clr_ofs = 0xe4,
.sta_ofs = 0xe8,
};
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
static const struct mtk_gate infra_ao_clks[] = {
/* INFRA_AO0 */
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
/* infra_ao_sej is main clock is for secure engine with JTAG support */
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9),
GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, "infra_ao_pwm_h", "top_axi", 15),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25),
GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
/* INFRA_AO1 */
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, "infra_ao_cg1_msdc2", "top_axi", 5),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_src", "top_msdc50_0", 6),
GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, "infra_ao_cec_66m_h", "top_axi", 13),
GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, "infra_ao_irrx", "top_axi", 14),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_src", "top_msdc30_1", 16),
GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, "infra_ao_cec_66m_b", "top_axi", 17),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18),
/* infra_ao_device_apc is for device access permission control module */
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_device_apc", "top_axi", 20,
CLK_IS_CRITICAL),
GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, "infra_ao_ecc_66m_h", "top_axi", 23),
GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24),
GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29),
GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc_f26m", "clk26m", 31),
/* INFRA_AO2 */
GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "top_usb_top", 1),
GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2),
GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, "infra_ao_cldma_b", "top_axi", 3),
GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, "infra_ao_audio_26m_b", "clk26m", 4),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "top_ufs", 11),
GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "top_ufs_tick1us", 12),
GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "top_ufs_mp_sap_cfg", 13),
GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15),
GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17),
GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "top_axi", 18),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, "infra_ao_aes_ufsfde", "top_ufs", 28),
GATE_INFRA_AO2(CLK_INFRA_AO_AES, "infra_ao_aes", "top_aes_ufsfde", 29),
GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, "infra_ao_ufs_tick", "top_ufs_tick1us", 30),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 31),
/* INFRA_AO3 */
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0f", "top_msdc50_0", 0),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1f", "top_msdc50_0", 1),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2f", "top_msdc50_0", 2),
GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5),
GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7),
GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8),
GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, "infra_ao_cg3_msdc2", "top_msdc30_2", 9),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10),
GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, "infra_ao_gcpu_66m_b", "top_axi", 16),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, "infra_ao_gcpu_133m_b", "top_axi", 17),
GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20),
GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24),
/* infra_ao_device_apc_sync is for device access permission control module */
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_device_apc_sync", "top_axi", 25,
CLK_IS_CRITICAL),
GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, "infra_ao_spis0", "top_spis", 28),
GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, "infra_ao_spis1", "top_spis", 29),
/* INFRA_AO4 */
/* infra_ao_133m_m_peri infra_ao_66m_m_peri are main clocks of peripheral */
GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_M_PERI, "infra_ao_133m_m_peri", "top_axi", 0,
CLK_IS_CRITICAL),
GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_M_PERI, "infra_ao_66m_m_peri", "top_axi", 1,
CLK_IS_CRITICAL),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", "pextp_pipe", 7),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, "infra_ao_pcie_pl_p_250m_p1",
"ssusb_u3phy_p1_p_p0", 8),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, "infra_ao_pcie_p1_tl_96m", "top_tl_p1", 17),
GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, "infra_ao_ufs_tx_symbol", "ufs_tx_symbol", 22),
GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, "infra_ao_ufs_rx_symbol", "ufs_rx_symbol", 23),
GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, "infra_ao_ufs_rx_symbol1", "ufs_rx_symbol1", 24),
GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
};
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
};
static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
{
.compatible = "mediatek,mt8195-infracfg_ao",
.data = &infra_ao_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_infra_ao_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-infra_ao",
.of_match_table = of_match_clk_mt8195_infra_ao,
},
};
builtin_platform_driver(clk_mt8195_infra_ao_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),
GATE_IPE(CLK_IPE_TOP, "ipe_top", "top_ipe", 3),
GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt8195_ipe[] = {
{
.compatible = "mediatek,mt8195-ipesys",
.data = &ipe_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_ipe_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-ipe",
.of_match_table = of_match_clk_mt8195_ipe,
},
};
builtin_platform_driver(clk_mt8195_ipe_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt8195_mfg[] = {
{
.compatible = "mediatek,mt8195-mfgcfg",
.data = &mfg_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_mfg_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-mfg",
.of_match_table = of_match_clk_mt8195_mfg,
},
};
builtin_platform_driver(clk_mt8195_mfg_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs peri_ao_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x18,
};
#define GATE_PERI_AO(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate peri_ao_clks[] = {
GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0),
GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1),
GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3),
GATE_PERI_AO(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "top_spinor", 5),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_BUS, "peri_ao_ssusb_1p_bus", "top_usb_top_1p", 7),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_XHCI, "peri_ao_ssusb_1p_xhci", "top_ssusb_xhci_1p", 8),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12),
GATE_PERI_AO(CLK_PERI_AO_SPINFI, "peri_ao_spinfi", "top_spinfi_bclk", 15),
GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac", "top_snps_eth_250m", 16),
GATE_PERI_AO(CLK_PERI_AO_NFI_H, "peri_ao_nfi_h", "top_axi", 19),
GATE_PERI_AO(CLK_PERI_AO_FNFI1X, "peri_ao_fnfi1x", "top_nfi1x", 20),
GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_MEM, "peri_ao_pcie_p0_mem", "mem_466m", 24),
GATE_PERI_AO(CLK_PERI_AO_PCIE_P1_MEM, "peri_ao_pcie_p1_mem", "mem_466m", 25),
};
static const struct mtk_clk_desc peri_ao_desc = {
.clks = peri_ao_clks,
.num_clks = ARRAY_SIZE(peri_ao_clks),
};
static const struct of_device_id of_match_clk_mt8195_peri_ao[] = {
{
.compatible = "mediatek,mt8195-pericfg_ao",
.data = &peri_ao_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_peri_ao_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-peri_ao",
.of_match_table = of_match_clk_mt8195_peri_ao,
},
};
builtin_platform_driver(clk_mt8195_peri_ao_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs scp_adsp_cg_regs = {
.set_ofs = 0x180,
.clr_ofs = 0x180,
.sta_ofs = 0x180,
};
#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate scp_adsp_clks[] = {
GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "top_adsp", 0),
};
static const struct mtk_clk_desc scp_adsp_desc = {
.clks = scp_adsp_clks,
.num_clks = ARRAY_SIZE(scp_adsp_clks),
};
static const struct of_device_id of_match_clk_mt8195_scp_adsp[] = {
{
.compatible = "mediatek,mt8195-scp_adsp",
.data = &scp_adsp_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_scp_adsp_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-scp_adsp",
.of_match_table = of_match_clk_mt8195_scp_adsp,
},
};
builtin_platform_driver(clk_mt8195_scp_adsp_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
static DEFINE_SPINLOCK(mt8195_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 248000000),
FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll", 1, 3),
FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll", 1, 4),
FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc1", 1, 7),
FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
};
static const char * const axi_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6_d2",
"ulposc1_d4"
};
static const char * const spm_parents[] = {
"clk26m",
"ulposc1_d10",
"mainpll_d7_d4",
"clk32k"
};
static const char * const scp_parents[] = {
"clk26m",
"univpll_d4",
"mainpll_d6",
"univpll_d6",
"univpll_d4_d2",
"mainpll_d4_d2",
"mainpll_d4",
"mainpll_d6_d2"
};
static const char * const bus_aximem_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6"
};
static const char * const vpp_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mmpll_d7",
"univpll_d6",
"mainpll_d4",
"mmpll_d5",
"tvdpll1",
"tvdpll2",
"univpll_d4",
"mmpll_d4"
};
static const char * const ethdr_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mmpll_d7",
"univpll_d6",
"mainpll_d4",
"mmpll_d5_d4",
"tvdpll1",
"tvdpll2",
"univpll_d4",
"mmpll_d4"
};
static const char * const ipe_parents[] = {
"clk26m",
"imgpll",
"mainpll_d4",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"univpll_d4_d2",
"mainpll_d4_d2",
"mmpll_d6_d2",
"univpll_d5_d2"
};
static const char * const cam_parents[] = {
"clk26m",
"mainpll_d4",
"mmpll_d4",
"univpll_d4",
"univpll_d5",
"univpll_d6",
"mmpll_d7",
"univpll_d4_d2",
"mainpll_d4_d2",
"imgpll"
};
static const char * const ccu_parents[] = {
"clk26m",
"univpll_d6",
"mainpll_d4_d2",
"mainpll_d4",
"univpll_d5",
"mainpll_d6",
"mmpll_d6",
"mmpll_d7",
"univpll_d4_d2",
"univpll_d7"
};
static const char * const img_parents[] = {
"clk26m",
"imgpll",
"univpll_d4",
"mainpll_d4",
"univpll_d5",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"univpll_d4_d2",
"mainpll_d4_d2",
"univpll_d5_d2"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll_d4_d4",
"univpll_d6_d2",
"univpll_d6_d4"
};
static const char * const dsp_parents[] = {
"clk26m",
"univpll_d6_d2",
"univpll_d4_d2",
"univpll_d5",
"univpll_d4",
"mmpll_d4",
"mainpll_d3",
"univpll_d3"
};
static const char * const dsp1_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d4_d2",
"univpll_d5",
"mmpll_d5",
"univpll_d4",
"mainpll_d3",
"univpll_d3"
};
static const char * const dsp2_parents[] = {
"clk26m",
"univpll_d6_d2",
"univpll_d4_d2",
"mainpll_d4",
"univpll_d4",
"mmpll_d4",
"mainpll_d3",
"univpll_d3"
};
static const char * const ipu_if_parents[] = {
"clk26m",
"univpll_d6_d2",
"univpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"univpll_d5",
"univpll_d4",
"mmpll_d4"
};
static const char * const mfg_parents[] = {
"clk26m",
"mainpll_d5_d2",
"univpll_d6",
"univpll_d7"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d6_d8",
"univpll_192m_d4",
"univpll_d6_d16",
"clk26m_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll_d6_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"mainpll_d5_d4",
"mainpll_d6_d4",
"msdcpll_d4",
"univpll_d6_d2",
"mainpll_d6_d2",
"mainpll_d4_d4",
"univpll_d5_d4"
};
static const char * const spis_parents[] = {
"clk26m",
"univpll_d6",
"mainpll_d6",
"univpll_d4_d2",
"univpll_d6_d2",
"univpll_d4_d4",
"univpll_d6_d4",
"mainpll_d7_d4"
};
static const char * const msdc50_0_h_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll",
"msdcpll_d2",
"univpll_d4_d4",
"mainpll_d6_d2",
"univpll_d4_d2"
};
static const char * const msdc30_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d6_d2",
"mainpll_d7_d2",
"msdcpll_d2"
};
static const char * const intdir_parents[] = {
"clk26m",
"univpll_d6",
"mainpll_d4",
"univpll_d4"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d7_d4"
};
static const char * const audio_h_parents[] = {
"clk26m",
"univpll_d7",
"apll1",
"apll2"
};
static const char * const pwrap_ulposc_parents[] = {
"ulposc1_d10",
"clk26m",
"ulposc1_d4",
"ulposc1_d7",
"ulposc1_d8",
"ulposc1_d16",
"mainpll_d4_d8",
"univpll_d5_d8"
};
static const char * const atb_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d5_d2"
};
static const char * const pwrmcu_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d6_d2",
"mainpll_d5_d2",
"mainpll_d9",
"mainpll_d4_d2"
};
static const char * const dp_parents[] = {
"clk26m",
"tvdpll1_d2",
"tvdpll2_d2",
"tvdpll1_d4",
"tvdpll2_d4",
"tvdpll1_d8",
"tvdpll2_d8",
"tvdpll1_d16",
"tvdpll2_d16"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"univpll_d6_d4",
"ulposc1_d2",
"ulposc1_d4",
"ulposc1_d16"
};
static const char * const usb_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d6_d4",
"univpll_d5_d2"
};
static const char * const i2c_parents[] = {
"clk26m",
"mainpll_d4_d8",
"univpll_d5_d4"
};
static const char * const seninf_parents[] = {
"clk26m",
"univpll_d4_d4",
"univpll_d6_d2",
"univpll_d4_d2",
"univpll_d7",
"univpll_d6",
"mmpll_d6",
"univpll_d5"
};
static const char * const gcpu_parents[] = {
"clk26m",
"mainpll_d6",
"univpll_d4_d2",
"mmpll_d5_d2",
"univpll_d5_d2"
};
static const char * const dxcc_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d4_d4",
"mainpll_d4_d8"
};
static const char * const dpmaif_parents[] = {
"clk26m",
"univpll_d4_d4",
"mainpll_d6",
"mainpll_d4_d2",
"univpll_d4_d2"
};
static const char * const aes_fde_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d4_d4",
"univpll_d4_d2",
"univpll_d6"
};
static const char * const ufs_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d4_d8",
"univpll_d4_d4",
"mainpll_d6_d2",
"univpll_d6_d2",
"msdcpll_d2"
};
static const char * const ufs_tick1us_parents[] = {
"clk26m_d52",
"clk26m"
};
static const char * const ufs_mp_sap_parents[] = {
"clk26m",
"msdcpll_d16"
};
static const char * const venc_parents[] = {
"clk26m",
"mmpll_d4_d2",
"mainpll_d6",
"univpll_d4_d2",
"mainpll_d4_d2",
"univpll_d6",
"mmpll_d6",
"mainpll_d5_d2",
"mainpll_d6_d2",
"mmpll_d9",
"univpll_d4_d4",
"mainpll_d4",
"univpll_d4",
"univpll_d5",
"univpll_d5_d2",
"mainpll_d5"
};
static const char * const vdec_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mainpll_d5",
"mmpll_d6",
"mmpll_d5",
"vdecpll",
"univpll_d4",
"mmpll_d4",
"univpll_d6_d2",
"mmpll_d9",
"univpll_d6",
"univpll_d5",
"mainpll_d4"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll_d4_d8"
};
static const char * const mcupm_parents[] = {
"clk26m",
"mainpll_d6_d2",
"mainpll_d7_d4",
};
static const char * const spmi_parents[] = {
"clk26m",
"clk26m_d2",
"ulposc1_d8",
"ulposc1_d10",
"ulposc1_d16",
"ulposc1_d7",
"clk32k",
"mainpll_d7_d8",
"mainpll_d6_d8",
"mainpll_d5_d8"
};
static const char * const dvfsrc_parents[] = {
"clk26m",
"ulposc1_d10",
"univpll_d6_d8",
"msdcpll_d16"
};
static const char * const tl_parents[] = {
"clk26m",
"univpll_d5_d4",
"mainpll_d4_d4"
};
static const char * const dsi_occ_parents[] = {
"clk26m",
"mainpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2"
};
static const char * const wpe_vpp_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"mainpll_d4_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mainpll_d6",
"mmpll_d7",
"univpll_d6",
"mainpll_d5",
"univpll_d5",
"mainpll_d4",
"tvdpll1",
"univpll_d4"
};
static const char * const hdcp_parents[] = {
"clk26m",
"univpll_d4_d8",
"mainpll_d5_d8",
"univpll_d6_d4"
};
static const char * const hdcp_24m_parents[] = {
"clk26m",
"univpll_192m_d4",
"univpll_192m_d8",
"univpll_d6_d8"
};
static const char * const hd20_dacr_ref_parents[] = {
"clk26m",
"univpll_d4_d2",
"univpll_d4_d4",
"univpll_d4_d8"
};
static const char * const hd20_hdcp_c_parents[] = {
"clk26m",
"msdcpll_d4",
"univpll_d4_d8",
"univpll_d6_d8"
};
static const char * const hdmi_xtal_parents[] = {
"clk26m",
"clk26m_d2"
};
static const char * const hdmi_apb_parents[] = {
"clk26m",
"univpll_d6_d4",
"msdcpll_d2"
};
static const char * const snps_eth_250m_parents[] = {
"clk26m",
"ethpll_d2"
};
static const char * const snps_eth_62p4m_ptp_parents[] = {
"apll2_d3",
"apll1_d3",
"clk26m",
"ethpll_d8"
};
static const char * const snps_eth_50m_rmii_parents[] = {
"clk26m",
"ethpll_d10"
};
static const char * const dgi_out_parents[] = {
"clk26m",
"dgipll",
"dgipll_d2",
"in_dgi",
"in_dgi_d2",
"mmpll_d4_d4"
};
static const char * const nna_parents[] = {
"clk26m",
"nnapll",
"univpll_d4",
"mainpll_d4",
"univpll_d5",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"univpll_d4_d2",
"mainpll_d4_d2",
"mmpll_d6_d2"
};
static const char * const adsp_parents[] = {
"clk26m",
"clk26m_d2",
"mainpll_d6",
"mainpll_d5_d2",
"univpll_d4_d4",
"univpll_d4",
"univpll_d6",
"ulposc1",
"adsppll",
"adsppll_d2",
"adsppll_d4",
"adsppll_d8"
};
static const char * const asm_parents[] = {
"clk26m",
"univpll_d6_d4",
"univpll_d6_d2",
"mainpll_d5_d2"
};
static const char * const apll1_parents[] = {
"clk26m",
"apll1_d4"
};
static const char * const apll2_parents[] = {
"clk26m",
"apll2_d4"
};
static const char * const apll3_parents[] = {
"clk26m",
"apll3_d4"
};
static const char * const apll4_parents[] = {
"clk26m",
"apll4_d4"
};
static const char * const apll5_parents[] = {
"clk26m",
"apll5_d4"
};
static const char * const i2s_parents[] = {
"clk26m",
"apll1",
"apll2",
"apll3",
"apll4",
"apll5",
"hdmirx_apll"
};
static const char * const a1sys_hp_parents[] = {
"clk26m",
"apll1_d4"
};
static const char * const a2sys_parents[] = {
"clk26m",
"apll2_d4"
};
static const char * const a3sys_parents[] = {
"clk26m",
"apll3_d4",
"apll4_d4",
"apll5_d4",
"hdmirx_apll_d3",
"hdmirx_apll_d4",
"hdmirx_apll_d6"
};
static const char * const spinfi_b_parents[] = {
"clk26m",
"univpll_d6_d8",
"univpll_d5_d8",
"mainpll_d4_d8",
"mainpll_d7_d4",
"mainpll_d6_d4",
"univpll_d6_d4",
"univpll_d5_d4"
};
static const char * const nfi1x_parents[] = {
"clk26m",
"univpll_d5_d4",
"mainpll_d7_d4",
"mainpll_d6_d4",
"univpll_d6_d4",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d6_d2"
};
static const char * const ecc_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"univpll_d6"
};
static const char * const audio_local_bus_parents[] = {
"clk26m",
"clk26m_d2",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6_d2",
"mainpll_d7",
"univpll_d6",
"ulposc1",
"ulposc1_d4",
"ulposc1_d2"
};
static const char * const spinor_parents[] = {
"clk26m",
"clk26m_d2",
"mainpll_d7_d8",
"univpll_d6_d8"
};
static const char * const dvio_dgi_ref_parents[] = {
"clk26m",
"in_dgi",
"in_dgi_d2",
"in_dgi_d4",
"in_dgi_d6",
"in_dgi_d8",
"mmpll_d4_d4"
};
static const char * const ulposc_parents[] = {
"ulposc1",
"ethpll_d2",
"mainpll_d4_d2",
"ethpll_d10"
};
static const char * const ulposc_core_parents[] = {
"ulposc2",
"univpll_d7",
"mainpll_d6",
"ethpll_d10"
};
static const char * const srck_parents[] = {
"ulposc1_d10",
"clk26m"
};
static const char * const mfg_fast_parents[] = {
"top_mfg_core_tmp",
"mfgpll"
};
static const struct mtk_mux top_mtk_muxes[] = {
/*
* CLK_CFG_0
* top_axi and top_bus_aximem are bus clocks, should not be closed by Linux.
* top_spm and top_scp are main clocks in always-on co-processor.
*/
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
dsp1_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
dsp1_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
dsp2_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
dsp2_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
dsp2_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
dsp_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
camtg_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
camtg_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
camtg_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
camtg_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
/*
* CLK_CFG_9
* top_pwrmcu is main clock in other co-processor, should not be
* handled by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
disp_pwm_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
disp_pwm_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
seninf_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
seninf_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
seninf_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
aes_fde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
/*
* CLK_CFG_16
* top_mcupm is main clock in other co-processor, should not be
* handled by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL),
/*
* CLK_CFG_17
* top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
spmi_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
/* CLK_CFG_18 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
tl_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
aes_fde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
/* CLK_CFG_19 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
/* CLK_CFG_20 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
/* CLK_CFG_21 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
nna_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
nna_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
/* CLK_CFG_22 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
asm_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
asm_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
asm_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
/* CLK_CFG_23 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
/*
* CLK_CFG_24
* i2so4_mck is not used in MT8195.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
i2s_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
i2s_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
/*
* CLK_CFG_25
* i2so5_mck and i2si4_mck are not used in MT8195.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
i2s_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
i2s_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
/*
* CLK_CFG_26
* i2si5_mck is not used in MT8195.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
i2s_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
i2s_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
/* CLK_CFG_27 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
a3sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
/* CLK_CFG_28 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
/*
* CLK_CFG_29
* top_ulposc/top_ulposc_core/top_srck are clock source of always on co-processor,
* should not be closed by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),
/*
* the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
* by Linux.
*/
};
static struct mtk_composite top_muxes[] = {
/* CLK_MISC_CFG_3 */
MUX(CLK_TOP_MFG_CK_FAST_REF, "mfg_ck_fast_ref", mfg_fast_parents, 0x0250, 8, 1),
};
static const struct mtk_composite top_adj_divs[] = {
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "top_i2so1_mck", 0x0320, 2, 0x0328, 8, 16),
DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "top_i2so2_mck", 0x0320, 3, 0x0328, 8, 24),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
/* apll12_div5 ~ 8 are not used in MT8195. */
DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "top_dptx_mck", 0x0320, 9, 0x0338, 8, 8),
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x238,
.clr_ofs = 0x238,
.sta_ofs = 0x238,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x250,
.clr_ofs = 0x250,
.sta_ofs = 0x250,
};
#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv, _flag)
#define GATE_TOP0(_id, _name, _parent, _shift) \
GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate top_clks[] = {
/* TOP0 */
GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "top_vpp", 0),
GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "top_vpp", 1),
GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "top_vpp", 2),
GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "top_vpp", 3),
GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
/*
* cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south
* are peripheral bus clock branches.
*/
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "top_axi", 10, CLK_IS_CRITICAL),
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "top_axi", 11,
CLK_IS_CRITICAL),
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "top_axi", 12, CLK_IS_CRITICAL),
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "top_axi", 13, CLK_IS_CRITICAL),
GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
/* TOP1 */
GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
};
static const struct of_device_id of_match_clk_mt8195_topck[] = {
{ .compatible = "mediatek,mt8195-topckgen", },
{}
};
static int clk_mt8195_topck_probe(struct platform_device *pdev)
{
struct clk_onecell_data *top_clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
if (!top_clk_data)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
r = PTR_ERR(base);
goto free_top_data;
}
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
top_clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
&mt8195_clk_lock, top_clk_data);
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
&mt8195_clk_lock, top_clk_data);
mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
&mt8195_clk_lock, top_clk_data);
r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
if (r)
goto free_top_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
if (r)
goto free_top_data;
return r;
free_top_data:
mtk_free_clk_data(top_clk_data);
return r;
}
static struct platform_driver clk_mt8195_topck_drv = {
.probe = clk_mt8195_topck_probe,
.driver = {
.name = "clk-mt8195-topck",
.of_match_table = of_match_clk_mt8195_topck,
},
};
builtin_platform_driver(clk_mt8195_topck_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vdec2_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "top_vdec", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "top_vdec", 0),
};
static const struct mtk_gate vdec_core1_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec", "top_vdec", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1", "top_vdec", 0),
};
static const struct mtk_gate vdec_soc_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "top_vdec", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "top_vdec", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct mtk_clk_desc vdec_core1_desc = {
.clks = vdec_core1_clks,
.num_clks = ARRAY_SIZE(vdec_core1_clks),
};
static const struct mtk_clk_desc vdec_soc_desc = {
.clks = vdec_soc_clks,
.num_clks = ARRAY_SIZE(vdec_soc_clks),
};
static const struct of_device_id of_match_clk_mt8195_vdec[] = {
{
.compatible = "mediatek,mt8195-vdecsys",
.data = &vdec_desc,
}, {
.compatible = "mediatek,mt8195-vdecsys_core1",
.data = &vdec_core1_desc,
}, {
.compatible = "mediatek,mt8195-vdecsys_soc",
.data = &vdec_soc_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_vdec_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-vdec",
.of_match_table = of_match_clk_mt8195_vdec,
},
};
builtin_platform_driver(clk_mt8195_vdec_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdo0_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo0_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs vdo0_2_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
#define GATE_VDO0_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vdo0_clks[] = {
/* VDO0_0 */
GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 2),
GATE_VDO0_0(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "top_vpp", 3),
GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
GATE_VDO0_0(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "top_vpp", 5),
GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 6),
GATE_VDO0_0(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "top_vpp", 7),
GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
GATE_VDO0_0(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "top_vpp", 9),
GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
GATE_VDO0_0(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "top_vpp", 11),
GATE_VDO0_0(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "top_vpp", 16),
GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
GATE_VDO0_0(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "top_vpp", 18),
GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
GATE_VDO0_0(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "top_vpp", 20),
GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 26),
GATE_VDO0_0(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "top_vpp", 27),
GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 29),
GATE_VDO0_0(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 30),
/* VDO0_1 */
GATE_VDO0_1(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "top_vpp", 0),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "top_vpp", 1),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 2),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "top_vpp", 3),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "top_vpp", 4),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "top_vpp", 5),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "top_vpp", 6),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "top_vpp", 7),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "top_vpp", 8),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "top_vpp", 9),
GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
/* VDO0_2 */
GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp", 16),
};
static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
if (r)
goto free_vdo0_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
goto free_vdo0_data;
return r;
free_vdo0_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt8195_vdo0_drv = {
.probe = clk_mt8195_vdo0_probe,
.driver = {
.name = "clk-mt8195-vdo0",
},
};
builtin_platform_driver(clk_mt8195_vdo0_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdo1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo1_1_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
static const struct mtk_gate_regs vdo1_2_cg_regs = {
.set_ofs = 0x134,
.clr_ofs = 0x138,
.sta_ofs = 0x130,
};
static const struct mtk_gate_regs vdo1_3_cg_regs = {
.set_ofs = 0x144,
.clr_ofs = 0x148,
.sta_ofs = 0x140,
};
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vdo1_clks[] = {
/* VDO1_0 */
GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng", "top_vpp", 4),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 12),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 13),
GATE_VDO1_0(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 14),
GATE_VDO1_0(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 15),
GATE_VDO1_0(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 16),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 17),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 18),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 19),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 20),
GATE_VDO1_0(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm", "top_vpp", 21),
GATE_VDO1_0(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm", "top_vpp", 22),
GATE_VDO1_0(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm", "top_vpp", 23),
GATE_VDO1_0(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor", "top_vpp", 24),
GATE_VDO1_0(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 25),
GATE_VDO1_0(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 26),
GATE_VDO1_0(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 27),
GATE_VDO1_0(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 28),
GATE_VDO1_0(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 29),
GATE_VDO1_0(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async",
"top_vpp", 30),
GATE_VDO1_0(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async",
"top_vpp", 31),
/* VDO1_1 */
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
GATE_VDO1_1(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
/* VDO1_2 */
GATE_VDO1_2(CLK_VDO1_DPI0, "vdo1_dpi0", "top_vpp", 0),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1),
GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9),
GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17),
/* VDO1_3 */
GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
};
static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
if (r)
goto free_vdo1_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
goto free_vdo1_data;
return r;
free_vdo1_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt8195_vdo1_drv = {
.probe = clk_mt8195_vdo1_probe,
.driver = {
.name = "clk-mt8195-vdo1",
},
};
builtin_platform_driver(clk_mt8195_vdo1_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_LARB, "venc_larb", "top_venc", 0),
GATE_VENC(CLK_VENC_VENC, "venc_venc", "top_venc", 4),
GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "top_venc", 8),
GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "top_venc", 12),
GATE_VENC(CLK_VENC_JPGDEC_C1, "venc_jpgdec_c1", "top_venc", 16),
GATE_VENC(CLK_VENC_GALS, "venc_gals", "top_venc", 28),
};
static const struct mtk_gate venc_core1_clks[] = {
GATE_VENC(CLK_VENC_CORE1_LARB, "venc_core1_larb", "top_venc", 0),
GATE_VENC(CLK_VENC_CORE1_VENC, "venc_core1_venc", "top_venc", 4),
GATE_VENC(CLK_VENC_CORE1_JPGENC, "venc_core1_jpgenc", "top_venc", 8),
GATE_VENC(CLK_VENC_CORE1_JPGDEC, "venc_core1_jpgdec", "top_venc", 12),
GATE_VENC(CLK_VENC_CORE1_JPGDEC_C1, "venc_core1_jpgdec_c1", "top_venc", 16),
GATE_VENC(CLK_VENC_CORE1_GALS, "venc_core1_gals", "top_venc", 28),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct mtk_clk_desc venc_core1_desc = {
.clks = venc_core1_clks,
.num_clks = ARRAY_SIZE(venc_core1_clks),
};
static const struct of_device_id of_match_clk_mt8195_venc[] = {
{
.compatible = "mediatek,mt8195-vencsys",
.data = &venc_desc,
}, {
.compatible = "mediatek,mt8195-vencsys_core1",
.data = &venc_core1_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_venc_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-venc",
.of_match_table = of_match_clk_mt8195_venc,
},
};
builtin_platform_driver(clk_mt8195_venc_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vpp0_0_cg_regs = {
.set_ofs = 0x24,
.clr_ofs = 0x28,
.sta_ofs = 0x20,
};
static const struct mtk_gate_regs vpp0_1_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x34,
.sta_ofs = 0x2c,
};
static const struct mtk_gate_regs vpp0_2_cg_regs = {
.set_ofs = 0x3c,
.clr_ofs = 0x40,
.sta_ofs = 0x38,
};
#define GATE_VPP0_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP0_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP0_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vpp0_clks[] = {
/* VPP0_0 */
GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
GATE_VPP0_0(CLK_VPP0_VPP02VPP1_RELAY, "vpp0_vpp02vpp1_relay", "top_vpp", 14),
GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
/* VPP0_1 */
GATE_VPP0_1(CLK_VPP0_SMI_COMMON, "vpp0_smi_common", "top_vpp", 0),
GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0, "vpp0_gals_vdo0_larb0", "top_vpp", 1),
GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1, "vpp0_gals_vdo0_larb1", "top_vpp", 2),
GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS, "vpp0_gals_vencsys", "top_vpp", 3),
GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1, "vpp0_gals_vencsys_core1", "top_vpp", 4),
GATE_VPP0_1(CLK_VPP0_GALS_INFRA, "vpp0_gals_infra", "top_vpp", 5),
GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS, "vpp0_gals_camsys", "top_vpp", 6),
GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5, "vpp0_gals_vpp1_larb5", "top_vpp", 7),
GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6, "vpp0_gals_vpp1_larb6", "top_vpp", 8),
GATE_VPP0_1(CLK_VPP0_SMI_REORDER, "vpp0_smi_reorder", "top_vpp", 9),
GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPE, "vpp0_gals_vpp1_wpe", "top_vpp", 21),
GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, "vpp0_gals_vdo0_vdo1_vencsys_core1",
"top_vpp", 22),
GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
/* VPP0_2 */
GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
GATE_VPP0_2(CLK_VPP0_WARP0_MDP_DL_ASYNC, "vpp0_warp0_mdp_dl_async", "top_wpe_vpp", 1),
GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3),
};
static const struct mtk_clk_desc vpp0_desc = {
.clks = vpp0_clks,
.num_clks = ARRAY_SIZE(vpp0_clks),
};
static const struct of_device_id of_match_clk_mt8195_vpp0[] = {
{
.compatible = "mediatek,mt8195-vppsys0",
.data = &vpp0_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_vpp0_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-vpp0",
.of_match_table = of_match_clk_mt8195_vpp0,
},
};
builtin_platform_driver(clk_mt8195_vpp0_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vpp1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vpp1_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
#define GATE_VPP1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vpp1_clks[] = {
/* VPP1_0 */
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 16),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 17),
GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 18),
GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 19),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 20),
GATE_VPP1_0(CLK_VPP1_VPPSYS1_GALS, "vpp1_vppsys1_gals", "top_vpp", 21),
GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 22),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 23),
GATE_VPP1_0(CLK_VPP1_VPPSYS1_LARB, "vpp1_vppsys1_larb", "top_vpp", 24),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 25),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 26),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 27),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 28),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 29),
GATE_VPP1_0(CLK_VPP1_DL_ASYNC, "vpp1_dl_async", "top_vpp", 30),
GATE_VPP1_0(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 31),
/* VPP1_1 */
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 0),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 1),
GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 2),
GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 3),
GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 4),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 5),
GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 6),
GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 8),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 9),
GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 10),
GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "hdmirx_p", 11),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "hdmirx_p", 12),
GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "in_dgi", 13),
GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_dgi_out", 14),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_dgi_out", 15),
GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 16),
GATE_VPP1_1(CLK_VPP1_VPP0_DL_RELAY, "vpp1_vpp0_dl_relay", "top_vpp", 17),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26),
};
static const struct mtk_clk_desc vpp1_desc = {
.clks = vpp1_clks,
.num_clks = ARRAY_SIZE(vpp1_clks),
};
static const struct of_device_id of_match_clk_mt8195_vpp1[] = {
{
.compatible = "mediatek,mt8195-vppsys1",
.data = &vpp1_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_vpp1_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-vpp1",
.of_match_table = of_match_clk_mt8195_vpp1,
},
};
builtin_platform_driver(clk_mt8195_vpp1_drv);
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs wpe_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs wpe_vpp0_cg_regs = {
.set_ofs = 0x58,
.clr_ofs = 0x58,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs wpe_vpp1_cg_regs = {
.set_ofs = 0x5c,
.clr_ofs = 0x5c,
.sta_ofs = 0x5c,
};
#define GATE_WPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_WPE_VPP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_WPE_VPP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate wpe_clks[] = {
GATE_WPE(CLK_WPE_VPP0, "wpe_vpp0", "top_wpe_vpp", 16),
GATE_WPE(CLK_WPE_VPP1, "wpe_vpp1", "top_wpe_vpp", 17),
GATE_WPE(CLK_WPE_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18),
GATE_WPE(CLK_WPE_SMI_LARB8, "wpe_smi_larb8", "top_wpe_vpp", 19),
GATE_WPE(CLK_WPE_EVENT_TX, "wpe_event_tx", "top_wpe_vpp", 20),
GATE_WPE(CLK_WPE_SMI_LARB7_P, "wpe_smi_larb7_p", "top_wpe_vpp", 24),
GATE_WPE(CLK_WPE_SMI_LARB8_P, "wpe_smi_larb8_p", "top_wpe_vpp", 25),
};
static const struct mtk_gate wpe_vpp0_clks[] = {
/* WPE_VPP0 */
GATE_WPE_VPP0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
GATE_WPE_VPP0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1),
GATE_WPE_VPP0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10),
GATE_WPE_VPP0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11),
GATE_WPE_VPP0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12),
GATE_WPE_VPP0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13),
GATE_WPE_VPP0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14),
GATE_WPE_VPP0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15),
GATE_WPE_VPP0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16),
GATE_WPE_VPP0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17),
/* WPE_VPP1 */
GATE_WPE_VPP1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0),
GATE_WPE_VPP1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1),
GATE_WPE_VPP1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2),
GATE_WPE_VPP1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3),
GATE_WPE_VPP1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4),
};
static const struct mtk_gate wpe_vpp1_clks[] = {
/* WPE_VPP0 */
GATE_WPE_VPP0(CLK_WPE_VPP1_VGEN, "wpe_vpp1_vgen", "top_img", 0),
GATE_WPE_VPP0(CLK_WPE_VPP1_EXT, "wpe_vpp1_ext", "top_img", 1),
GATE_WPE_VPP0(CLK_WPE_VPP1_VFC, "wpe_vpp1_vfc", "top_img", 2),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_TOP, "wpe_vpp1_cach0_top", "top_img", 3),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_DMA, "wpe_vpp1_cach0_dma", "top_img", 4),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_TOP, "wpe_vpp1_cach1_top", "top_img", 5),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_DMA, "wpe_vpp1_cach1_dma", "top_img", 6),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_TOP, "wpe_vpp1_cach2_top", "top_img", 7),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_DMA, "wpe_vpp1_cach2_dma", "top_img", 8),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_TOP, "wpe_vpp1_cach3_top", "top_img", 9),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_DMA, "wpe_vpp1_cach3_dma", "top_img", 10),
GATE_WPE_VPP0(CLK_WPE_VPP1_PSP, "wpe_vpp1_psp", "top_img", 11),
GATE_WPE_VPP0(CLK_WPE_VPP1_PSP2, "wpe_vpp1_psp2", "top_img", 12),
GATE_WPE_VPP0(CLK_WPE_VPP1_SYNC, "wpe_vpp1_sync", "top_img", 13),
GATE_WPE_VPP0(CLK_WPE_VPP1_C24, "wpe_vpp1_c24", "top_img", 14),
GATE_WPE_VPP0(CLK_WPE_VPP1_MDP_CROP, "wpe_vpp1_mdp_crop", "top_img", 15),
GATE_WPE_VPP0(CLK_WPE_VPP1_ISP_CROP, "wpe_vpp1_isp_crop", "top_img", 16),
GATE_WPE_VPP0(CLK_WPE_VPP1_TOP, "wpe_vpp1_top", "top_img", 17),
/* WPE_VPP1 */
GATE_WPE_VPP1(CLK_WPE_VPP1_VECI, "wpe_vpp1_veci", "top_img", 0),
GATE_WPE_VPP1(CLK_WPE_VPP1_VEC2I, "wpe_vpp1_vec2i", "top_img", 1),
GATE_WPE_VPP1(CLK_WPE_VPP1_VEC3I, "wpe_vpp1_vec3i", "top_img", 2),
GATE_WPE_VPP1(CLK_WPE_VPP1_WPEO, "wpe_vpp1_wpeo", "top_img", 3),
GATE_WPE_VPP1(CLK_WPE_VPP1_MSKO, "wpe_vpp1_msko", "top_img", 4),
};
static const struct mtk_clk_desc wpe_desc = {
.clks = wpe_clks,
.num_clks = ARRAY_SIZE(wpe_clks),
};
static const struct mtk_clk_desc wpe_vpp0_desc = {
.clks = wpe_vpp0_clks,
.num_clks = ARRAY_SIZE(wpe_vpp0_clks),
};
static const struct mtk_clk_desc wpe_vpp1_desc = {
.clks = wpe_vpp1_clks,
.num_clks = ARRAY_SIZE(wpe_vpp1_clks),
};
static const struct of_device_id of_match_clk_mt8195_wpe[] = {
{
.compatible = "mediatek,mt8195-wpesys",
.data = &wpe_desc,
}, {
.compatible = "mediatek,mt8195-wpesys_vpp0",
.data = &wpe_vpp0_desc,
}, {
.compatible = "mediatek,mt8195-wpesys_vpp1",
.data = &wpe_vpp1_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_wpe_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-wpe",
.of_match_table = of_match_clk_mt8195_wpe,
},
};
builtin_platform_driver(clk_mt8195_wpe_drv);
......@@ -11,6 +11,7 @@
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/clkdev.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/device.h>
#include <linux/of_device.h>
......@@ -42,6 +43,16 @@ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
return NULL;
}
EXPORT_SYMBOL_GPL(mtk_alloc_clk_data);
void mtk_free_clk_data(struct clk_onecell_data *clk_data)
{
if (!clk_data)
return;
kfree(clk_data->clks);
kfree(clk_data);
}
void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
int num, struct clk_onecell_data *clk_data)
......@@ -68,6 +79,7 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
clk_data->clks[rc->id] = clk;
}
}
EXPORT_SYMBOL_GPL(mtk_clk_register_fixed_clks);
void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
int num, struct clk_onecell_data *clk_data)
......@@ -94,6 +106,7 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
clk_data->clks[ff->id] = clk;
}
}
EXPORT_SYMBOL_GPL(mtk_clk_register_factors);
int mtk_clk_register_gates_with_dev(struct device_node *node,
const struct mtk_gate *clks,
......@@ -146,6 +159,7 @@ int mtk_clk_register_gates(struct device_node *node,
return mtk_clk_register_gates_with_dev(node,
clks, num, clk_data, NULL);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
void __iomem *base, spinlock_t *lock)
......@@ -259,6 +273,7 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs,
clk_data->clks[mc->id] = clk;
}
}
EXPORT_SYMBOL_GPL(mtk_clk_register_composites);
void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
int num, void __iomem *base, spinlock_t *lock,
......@@ -305,7 +320,17 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, clk_data);
if (r)
return r;
goto free_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
goto free_data;
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return r;
free_data:
mtk_free_clk_data(clk_data);
return r;
}
MODULE_LICENSE("GPL");
......@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
struct clk_onecell_data *clk_data);
struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
void mtk_free_clk_data(struct clk_onecell_data *clk_data);
#define HAVE_RST_BAR BIT(0)
#define PLL_AO BIT(1)
......
......@@ -8,6 +8,7 @@
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "clk-mtk.h"
#include "clk-mux.h"
......@@ -120,6 +121,7 @@ const struct clk_ops mtk_mux_clr_set_upd_ops = {
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
};
EXPORT_SYMBOL_GPL(mtk_mux_clr_set_upd_ops);
const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
.enable = mtk_clk_mux_enable_setclr,
......@@ -128,6 +130,7 @@ const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
struct regmap *regmap,
......@@ -195,3 +198,6 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes,
return 0;
}
EXPORT_SYMBOL_GPL(mtk_clk_register_muxes);
MODULE_LICENSE("GPL");
......@@ -7,6 +7,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
......@@ -332,7 +333,7 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
pll->pcw_chg_addr = pll->base_addr + REG_CON1;
if (data->tuner_reg)
pll->tuner_addr = base + data->tuner_reg;
if (data->tuner_en_reg)
if (data->tuner_en_reg || data->tuner_en_bit)
pll->tuner_en_addr = base + data->tuner_en_reg;
if (data->en_reg)
pll->en_addr = base + data->en_reg;
......@@ -385,3 +386,6 @@ void mtk_clk_register_plls(struct device_node *node,
clk_data->clks[pll->id] = clk;
}
}
EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
MODULE_LICENSE("GPL");
......@@ -137,3 +137,5 @@ void mtk_register_reset_controller_set_clr(struct device_node *np,
mtk_register_reset_controller_common(np, num_regs, regofs,
&mtk_reset_ops_set_clr);
}
MODULE_LICENSE("GPL");
......@@ -2,8 +2,9 @@
menu "Clock driver for ARM Reference designs"
depends on HAS_IOMEM
depends on ARM || ARM64 || COMPILE_TEST
config ICST
config CLK_ICST
bool "Clock driver for ARM Reference designs ICST"
select REGMAP_MMIO
help
......
# SPDX-License-Identifier: GPL-2.0-only
# Makefile for Versatile-specific clocks
obj-$(CONFIG_ICST) += icst.o clk-icst.o clk-versatile.o
obj-$(CONFIG_CLK_ICST) += icst.o clk-icst.o clk-versatile.o
obj-$(CONFIG_INTEGRATOR_IMPD1) += clk-impd1.o
obj-$(CONFIG_CLK_SP810) += clk-sp810.o
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk-vexpress-osc.o
......@@ -501,7 +501,8 @@ static void __init of_syscon_icst_setup(struct device_node *np)
return;
}
if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
if (of_property_read_u32(np, "reg", &icst_desc.vco_offset) &&
of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
pr_err("no VCO register offset for ICST clock\n");
return;
}
......
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT8195_H
#define _DT_BINDINGS_CLK_MT8195_H
/* TOPCKGEN */
#define CLK_TOP_AXI 0
#define CLK_TOP_SPM 1
#define CLK_TOP_SCP 2
#define CLK_TOP_BUS_AXIMEM 3
#define CLK_TOP_VPP 4
#define CLK_TOP_ETHDR 5
#define CLK_TOP_IPE 6
#define CLK_TOP_CAM 7
#define CLK_TOP_CCU 8
#define CLK_TOP_IMG 9
#define CLK_TOP_CAMTM 10
#define CLK_TOP_DSP 11
#define CLK_TOP_DSP1 12
#define CLK_TOP_DSP2 13
#define CLK_TOP_DSP3 14
#define CLK_TOP_DSP4 15
#define CLK_TOP_DSP5 16
#define CLK_TOP_DSP6 17
#define CLK_TOP_DSP7 18
#define CLK_TOP_IPU_IF 19
#define CLK_TOP_MFG_CORE_TMP 20
#define CLK_TOP_CAMTG 21
#define CLK_TOP_CAMTG2 22
#define CLK_TOP_CAMTG3 23
#define CLK_TOP_CAMTG4 24
#define CLK_TOP_CAMTG5 25
#define CLK_TOP_UART 26
#define CLK_TOP_SPI 27
#define CLK_TOP_SPIS 28
#define CLK_TOP_MSDC50_0_HCLK 29
#define CLK_TOP_MSDC50_0 30
#define CLK_TOP_MSDC30_1 31
#define CLK_TOP_MSDC30_2 32
#define CLK_TOP_INTDIR 33
#define CLK_TOP_AUD_INTBUS 34
#define CLK_TOP_AUDIO_H 35
#define CLK_TOP_PWRAP_ULPOSC 36
#define CLK_TOP_ATB 37
#define CLK_TOP_PWRMCU 38
#define CLK_TOP_DP 39
#define CLK_TOP_EDP 40
#define CLK_TOP_DPI 41
#define CLK_TOP_DISP_PWM0 42
#define CLK_TOP_DISP_PWM1 43
#define CLK_TOP_USB_TOP 44
#define CLK_TOP_SSUSB_XHCI 45
#define CLK_TOP_USB_TOP_1P 46
#define CLK_TOP_SSUSB_XHCI_1P 47
#define CLK_TOP_USB_TOP_2P 48
#define CLK_TOP_SSUSB_XHCI_2P 49
#define CLK_TOP_USB_TOP_3P 50
#define CLK_TOP_SSUSB_XHCI_3P 51
#define CLK_TOP_I2C 52
#define CLK_TOP_SENINF 53
#define CLK_TOP_SENINF1 54
#define CLK_TOP_SENINF2 55
#define CLK_TOP_SENINF3 56
#define CLK_TOP_GCPU 57
#define CLK_TOP_DXCC 58
#define CLK_TOP_DPMAIF_MAIN 59
#define CLK_TOP_AES_UFSFDE 60
#define CLK_TOP_UFS 61
#define CLK_TOP_UFS_TICK1US 62
#define CLK_TOP_UFS_MP_SAP_CFG 63
#define CLK_TOP_VENC 64
#define CLK_TOP_VDEC 65
#define CLK_TOP_PWM 66
#define CLK_TOP_MCUPM 67
#define CLK_TOP_SPMI_P_MST 68
#define CLK_TOP_SPMI_M_MST 69
#define CLK_TOP_DVFSRC 70
#define CLK_TOP_TL 71
#define CLK_TOP_TL_P1 72
#define CLK_TOP_AES_MSDCFDE 73
#define CLK_TOP_DSI_OCC 74
#define CLK_TOP_WPE_VPP 75
#define CLK_TOP_HDCP 76
#define CLK_TOP_HDCP_24M 77
#define CLK_TOP_HD20_DACR_REF_CLK 78
#define CLK_TOP_HD20_HDCP_CCLK 79
#define CLK_TOP_HDMI_XTAL 80
#define CLK_TOP_HDMI_APB 81
#define CLK_TOP_SNPS_ETH_250M 82
#define CLK_TOP_SNPS_ETH_62P4M_PTP 83
#define CLK_TOP_SNPS_ETH_50M_RMII 84
#define CLK_TOP_DGI_OUT 85
#define CLK_TOP_NNA0 86
#define CLK_TOP_NNA1 87
#define CLK_TOP_ADSP 88
#define CLK_TOP_ASM_H 89
#define CLK_TOP_ASM_M 90
#define CLK_TOP_ASM_L 91
#define CLK_TOP_APLL1 92
#define CLK_TOP_APLL2 93
#define CLK_TOP_APLL3 94
#define CLK_TOP_APLL4 95
#define CLK_TOP_APLL5 96
#define CLK_TOP_I2SO1_MCK 97
#define CLK_TOP_I2SO2_MCK 98
#define CLK_TOP_I2SI1_MCK 99
#define CLK_TOP_I2SI2_MCK 100
#define CLK_TOP_DPTX_MCK 101
#define CLK_TOP_AUD_IEC_CLK 102
#define CLK_TOP_A1SYS_HP 103
#define CLK_TOP_A2SYS_HF 104
#define CLK_TOP_A3SYS_HF 105
#define CLK_TOP_A4SYS_HF 106
#define CLK_TOP_SPINFI_BCLK 107
#define CLK_TOP_NFI1X 108
#define CLK_TOP_ECC 109
#define CLK_TOP_AUDIO_LOCAL_BUS 110
#define CLK_TOP_SPINOR 111
#define CLK_TOP_DVIO_DGI_REF 112
#define CLK_TOP_ULPOSC 113
#define CLK_TOP_ULPOSC_CORE 114
#define CLK_TOP_SRCK 115
#define CLK_TOP_MFG_CK_FAST_REF 116
#define CLK_TOP_CLK26M_D2 117
#define CLK_TOP_CLK26M_D52 118
#define CLK_TOP_IN_DGI 119
#define CLK_TOP_IN_DGI_D2 120
#define CLK_TOP_IN_DGI_D4 121
#define CLK_TOP_IN_DGI_D6 122
#define CLK_TOP_IN_DGI_D8 123
#define CLK_TOP_MAINPLL_D3 124
#define CLK_TOP_MAINPLL_D4 125
#define CLK_TOP_MAINPLL_D4_D2 126
#define CLK_TOP_MAINPLL_D4_D4 127
#define CLK_TOP_MAINPLL_D4_D8 128
#define CLK_TOP_MAINPLL_D5 129
#define CLK_TOP_MAINPLL_D5_D2 130
#define CLK_TOP_MAINPLL_D5_D4 131
#define CLK_TOP_MAINPLL_D5_D8 132
#define CLK_TOP_MAINPLL_D6 133
#define CLK_TOP_MAINPLL_D6_D2 134
#define CLK_TOP_MAINPLL_D6_D4 135
#define CLK_TOP_MAINPLL_D6_D8 136
#define CLK_TOP_MAINPLL_D7 137
#define CLK_TOP_MAINPLL_D7_D2 138
#define CLK_TOP_MAINPLL_D7_D4 139
#define CLK_TOP_MAINPLL_D7_D8 140
#define CLK_TOP_MAINPLL_D9 141
#define CLK_TOP_UNIVPLL_D2 142
#define CLK_TOP_UNIVPLL_D3 143
#define CLK_TOP_UNIVPLL_D4 144
#define CLK_TOP_UNIVPLL_D4_D2 145
#define CLK_TOP_UNIVPLL_D4_D4 146
#define CLK_TOP_UNIVPLL_D4_D8 147
#define CLK_TOP_UNIVPLL_D5 148
#define CLK_TOP_UNIVPLL_D5_D2 149
#define CLK_TOP_UNIVPLL_D5_D4 150
#define CLK_TOP_UNIVPLL_D5_D8 151
#define CLK_TOP_UNIVPLL_D6 152
#define CLK_TOP_UNIVPLL_D6_D2 153
#define CLK_TOP_UNIVPLL_D6_D4 154
#define CLK_TOP_UNIVPLL_D6_D8 155
#define CLK_TOP_UNIVPLL_D6_D16 156
#define CLK_TOP_UNIVPLL_D7 157
#define CLK_TOP_UNIVPLL_192M 158
#define CLK_TOP_UNIVPLL_192M_D4 159
#define CLK_TOP_UNIVPLL_192M_D8 160
#define CLK_TOP_UNIVPLL_192M_D16 161
#define CLK_TOP_UNIVPLL_192M_D32 162
#define CLK_TOP_APLL1_D3 163
#define CLK_TOP_APLL1_D4 164
#define CLK_TOP_APLL2_D3 165
#define CLK_TOP_APLL2_D4 166
#define CLK_TOP_APLL3_D4 167
#define CLK_TOP_APLL4_D4 168
#define CLK_TOP_APLL5_D4 169
#define CLK_TOP_HDMIRX_APLL_D3 170
#define CLK_TOP_HDMIRX_APLL_D4 171
#define CLK_TOP_HDMIRX_APLL_D6 172
#define CLK_TOP_MMPLL_D4 173
#define CLK_TOP_MMPLL_D4_D2 174
#define CLK_TOP_MMPLL_D4_D4 175
#define CLK_TOP_MMPLL_D5 176
#define CLK_TOP_MMPLL_D5_D2 177
#define CLK_TOP_MMPLL_D5_D4 178
#define CLK_TOP_MMPLL_D6 179
#define CLK_TOP_MMPLL_D6_D2 180
#define CLK_TOP_MMPLL_D7 181
#define CLK_TOP_MMPLL_D9 182
#define CLK_TOP_TVDPLL1_D2 183
#define CLK_TOP_TVDPLL1_D4 184
#define CLK_TOP_TVDPLL1_D8 185
#define CLK_TOP_TVDPLL1_D16 186
#define CLK_TOP_TVDPLL2_D2 187
#define CLK_TOP_TVDPLL2_D4 188
#define CLK_TOP_TVDPLL2_D8 189
#define CLK_TOP_TVDPLL2_D16 190
#define CLK_TOP_MSDCPLL_D2 191
#define CLK_TOP_MSDCPLL_D4 192
#define CLK_TOP_MSDCPLL_D16 193
#define CLK_TOP_ETHPLL_D2 194
#define CLK_TOP_ETHPLL_D8 195
#define CLK_TOP_ETHPLL_D10 196
#define CLK_TOP_DGIPLL_D2 197
#define CLK_TOP_ULPOSC1 198
#define CLK_TOP_ULPOSC1_D2 199
#define CLK_TOP_ULPOSC1_D4 200
#define CLK_TOP_ULPOSC1_D7 201
#define CLK_TOP_ULPOSC1_D8 202
#define CLK_TOP_ULPOSC1_D10 203
#define CLK_TOP_ULPOSC1_D16 204
#define CLK_TOP_ULPOSC2 205
#define CLK_TOP_ADSPPLL_D2 206
#define CLK_TOP_ADSPPLL_D4 207
#define CLK_TOP_ADSPPLL_D8 208
#define CLK_TOP_MEM_466M 209
#define CLK_TOP_MPHONE_SLAVE_B 210
#define CLK_TOP_PEXTP_PIPE 211
#define CLK_TOP_UFS_RX_SYMBOL 212
#define CLK_TOP_UFS_TX_SYMBOL 213
#define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214
#define CLK_TOP_UFS_RX_SYMBOL1 215
#define CLK_TOP_FPC 216
#define CLK_TOP_HDMIRX_P 217
#define CLK_TOP_APLL12_DIV0 218
#define CLK_TOP_APLL12_DIV1 219
#define CLK_TOP_APLL12_DIV2 220
#define CLK_TOP_APLL12_DIV3 221
#define CLK_TOP_APLL12_DIV4 222
#define CLK_TOP_APLL12_DIV9 223
#define CLK_TOP_CFG_VPP0 224
#define CLK_TOP_CFG_VPP1 225
#define CLK_TOP_CFG_VDO0 226
#define CLK_TOP_CFG_VDO1 227
#define CLK_TOP_CFG_UNIPLL_SES 228
#define CLK_TOP_CFG_26M_VPP0 229
#define CLK_TOP_CFG_26M_VPP1 230
#define CLK_TOP_CFG_26M_AUD 231
#define CLK_TOP_CFG_AXI_EAST 232
#define CLK_TOP_CFG_AXI_EAST_NORTH 233
#define CLK_TOP_CFG_AXI_NORTH 234
#define CLK_TOP_CFG_AXI_SOUTH 235
#define CLK_TOP_CFG_EXT_TEST 236
#define CLK_TOP_SSUSB_REF 237
#define CLK_TOP_SSUSB_PHY_REF 238
#define CLK_TOP_SSUSB_P1_REF 239
#define CLK_TOP_SSUSB_PHY_P1_REF 240
#define CLK_TOP_SSUSB_P2_REF 241
#define CLK_TOP_SSUSB_PHY_P2_REF 242
#define CLK_TOP_SSUSB_P3_REF 243
#define CLK_TOP_SSUSB_PHY_P3_REF 244
#define CLK_TOP_NR_CLK 245
/* INFRACFG_AO */
#define CLK_INFRA_AO_PMIC_TMR 0
#define CLK_INFRA_AO_PMIC_AP 1
#define CLK_INFRA_AO_PMIC_MD 2
#define CLK_INFRA_AO_PMIC_CONN 3
#define CLK_INFRA_AO_SEJ 4
#define CLK_INFRA_AO_APXGPT 5
#define CLK_INFRA_AO_GCE 6
#define CLK_INFRA_AO_GCE2 7
#define CLK_INFRA_AO_THERM 8
#define CLK_INFRA_AO_PWM_H 9
#define CLK_INFRA_AO_PWM1 10
#define CLK_INFRA_AO_PWM2 11
#define CLK_INFRA_AO_PWM3 12
#define CLK_INFRA_AO_PWM4 13
#define CLK_INFRA_AO_PWM 14
#define CLK_INFRA_AO_UART0 15
#define CLK_INFRA_AO_UART1 16
#define CLK_INFRA_AO_UART2 17
#define CLK_INFRA_AO_UART3 18
#define CLK_INFRA_AO_UART4 19
#define CLK_INFRA_AO_GCE_26M 20
#define CLK_INFRA_AO_CQ_DMA_FPC 21
#define CLK_INFRA_AO_UART5 22
#define CLK_INFRA_AO_HDMI_26M 23
#define CLK_INFRA_AO_SPI0 24
#define CLK_INFRA_AO_MSDC0 25
#define CLK_INFRA_AO_MSDC1 26
#define CLK_INFRA_AO_CG1_MSDC2 27
#define CLK_INFRA_AO_MSDC0_SRC 28
#define CLK_INFRA_AO_TRNG 29
#define CLK_INFRA_AO_AUXADC 30
#define CLK_INFRA_AO_CPUM 31
#define CLK_INFRA_AO_HDMI_32K 32
#define CLK_INFRA_AO_CEC_66M_H 33
#define CLK_INFRA_AO_IRRX 34
#define CLK_INFRA_AO_PCIE_TL_26M 35
#define CLK_INFRA_AO_MSDC1_SRC 36
#define CLK_INFRA_AO_CEC_66M_B 37
#define CLK_INFRA_AO_PCIE_TL_96M 38
#define CLK_INFRA_AO_DEVICE_APC 39
#define CLK_INFRA_AO_ECC_66M_H 40
#define CLK_INFRA_AO_DEBUGSYS 41
#define CLK_INFRA_AO_AUDIO 42
#define CLK_INFRA_AO_PCIE_TL_32K 43
#define CLK_INFRA_AO_DBG_TRACE 44
#define CLK_INFRA_AO_DRAMC_F26M 45
#define CLK_INFRA_AO_IRTX 46
#define CLK_INFRA_AO_SSUSB 47
#define CLK_INFRA_AO_DISP_PWM 48
#define CLK_INFRA_AO_CLDMA_B 49
#define CLK_INFRA_AO_AUDIO_26M_B 50
#define CLK_INFRA_AO_SPI1 51
#define CLK_INFRA_AO_SPI2 52
#define CLK_INFRA_AO_SPI3 53
#define CLK_INFRA_AO_UNIPRO_SYS 54
#define CLK_INFRA_AO_UNIPRO_TICK 55
#define CLK_INFRA_AO_UFS_MP_SAP_B 56
#define CLK_INFRA_AO_PWRMCU 57
#define CLK_INFRA_AO_PWRMCU_BUS_H 58
#define CLK_INFRA_AO_APDMA_B 59
#define CLK_INFRA_AO_SPI4 60
#define CLK_INFRA_AO_SPI5 61
#define CLK_INFRA_AO_CQ_DMA 62
#define CLK_INFRA_AO_AES_UFSFDE 63
#define CLK_INFRA_AO_AES 64
#define CLK_INFRA_AO_UFS_TICK 65
#define CLK_INFRA_AO_SSUSB_XHCI 66
#define CLK_INFRA_AO_MSDC0_SELF 67
#define CLK_INFRA_AO_MSDC1_SELF 68
#define CLK_INFRA_AO_MSDC2_SELF 69
#define CLK_INFRA_AO_I2S_DMA 70
#define CLK_INFRA_AO_AP_MSDC0 71
#define CLK_INFRA_AO_MD_MSDC0 72
#define CLK_INFRA_AO_CG3_MSDC2 73
#define CLK_INFRA_AO_GCPU 74
#define CLK_INFRA_AO_PCIE_PERI_26M 75
#define CLK_INFRA_AO_GCPU_66M_B 76
#define CLK_INFRA_AO_GCPU_133M_B 77
#define CLK_INFRA_AO_DISP_PWM1 78
#define CLK_INFRA_AO_FBIST2FPC 79
#define CLK_INFRA_AO_DEVICE_APC_SYNC 80
#define CLK_INFRA_AO_PCIE_P1_PERI_26M 81
#define CLK_INFRA_AO_SPIS0 82
#define CLK_INFRA_AO_SPIS1 83
#define CLK_INFRA_AO_133M_M_PERI 84
#define CLK_INFRA_AO_66M_M_PERI 85
#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86
#define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87
#define CLK_INFRA_AO_PCIE_P1_TL_96M 88
#define CLK_INFRA_AO_AES_MSDCFDE_0P 89
#define CLK_INFRA_AO_UFS_TX_SYMBOL 90
#define CLK_INFRA_AO_UFS_RX_SYMBOL 91
#define CLK_INFRA_AO_UFS_RX_SYMBOL1 92
#define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93
#define CLK_INFRA_AO_NR_CLK 94
/* APMIXEDSYS */
#define CLK_APMIXED_NNAPLL 0
#define CLK_APMIXED_RESPLL 1
#define CLK_APMIXED_ETHPLL 2
#define CLK_APMIXED_MSDCPLL 3
#define CLK_APMIXED_TVDPLL1 4
#define CLK_APMIXED_TVDPLL2 5
#define CLK_APMIXED_MMPLL 6
#define CLK_APMIXED_MAINPLL 7
#define CLK_APMIXED_VDECPLL 8
#define CLK_APMIXED_IMGPLL 9
#define CLK_APMIXED_UNIVPLL 10
#define CLK_APMIXED_HDMIPLL1 11
#define CLK_APMIXED_HDMIPLL2 12
#define CLK_APMIXED_HDMIRX_APLL 13
#define CLK_APMIXED_USB1PLL 14
#define CLK_APMIXED_ADSPPLL 15
#define CLK_APMIXED_APLL1 16
#define CLK_APMIXED_APLL2 17
#define CLK_APMIXED_APLL3 18
#define CLK_APMIXED_APLL4 19
#define CLK_APMIXED_APLL5 20
#define CLK_APMIXED_MFGPLL 21
#define CLK_APMIXED_DGIPLL 22
#define CLK_APMIXED_PLL_SSUSB26M 23
#define CLK_APMIXED_NR_CLK 24
/* SCP_ADSP */
#define CLK_SCP_ADSP_AUDIODSP 0
#define CLK_SCP_ADSP_NR_CLK 1
/* PERICFG_AO */
#define CLK_PERI_AO_ETHERNET 0
#define CLK_PERI_AO_ETHERNET_BUS 1
#define CLK_PERI_AO_FLASHIF_BUS 2
#define CLK_PERI_AO_FLASHIF_FLASH 3
#define CLK_PERI_AO_SSUSB_1P_BUS 4
#define CLK_PERI_AO_SSUSB_1P_XHCI 5
#define CLK_PERI_AO_SSUSB_2P_BUS 6
#define CLK_PERI_AO_SSUSB_2P_XHCI 7
#define CLK_PERI_AO_SSUSB_3P_BUS 8
#define CLK_PERI_AO_SSUSB_3P_XHCI 9
#define CLK_PERI_AO_SPINFI 10
#define CLK_PERI_AO_ETHERNET_MAC 11
#define CLK_PERI_AO_NFI_H 12
#define CLK_PERI_AO_FNFI1X 13
#define CLK_PERI_AO_PCIE_P0_MEM 14
#define CLK_PERI_AO_PCIE_P1_MEM 15
#define CLK_PERI_AO_NR_CLK 16
/* IMP_IIC_WRAP_S */
#define CLK_IMP_IIC_WRAP_S_I2C5 0
#define CLK_IMP_IIC_WRAP_S_I2C6 1
#define CLK_IMP_IIC_WRAP_S_I2C7 2
#define CLK_IMP_IIC_WRAP_S_NR_CLK 3
/* IMP_IIC_WRAP_W */
#define CLK_IMP_IIC_WRAP_W_I2C0 0
#define CLK_IMP_IIC_WRAP_W_I2C1 1
#define CLK_IMP_IIC_WRAP_W_I2C2 2
#define CLK_IMP_IIC_WRAP_W_I2C3 3
#define CLK_IMP_IIC_WRAP_W_I2C4 4
#define CLK_IMP_IIC_WRAP_W_NR_CLK 5
/* MFGCFG */
#define CLK_MFG_BG3D 0
#define CLK_MFG_NR_CLK 1
/* VPPSYS0 */
#define CLK_VPP0_MDP_FG 0
#define CLK_VPP0_STITCH 1
#define CLK_VPP0_PADDING 2
#define CLK_VPP0_MDP_TCC 3
#define CLK_VPP0_WARP0_ASYNC_TX 4
#define CLK_VPP0_WARP1_ASYNC_TX 5
#define CLK_VPP0_MUTEX 6
#define CLK_VPP0_VPP02VPP1_RELAY 7
#define CLK_VPP0_VPP12VPP0_ASYNC 8
#define CLK_VPP0_MMSYSRAM_TOP 9
#define CLK_VPP0_MDP_AAL 10
#define CLK_VPP0_MDP_RSZ 11
#define CLK_VPP0_SMI_COMMON 12
#define CLK_VPP0_GALS_VDO0_LARB0 13
#define CLK_VPP0_GALS_VDO0_LARB1 14
#define CLK_VPP0_GALS_VENCSYS 15
#define CLK_VPP0_GALS_VENCSYS_CORE1 16
#define CLK_VPP0_GALS_INFRA 17
#define CLK_VPP0_GALS_CAMSYS 18
#define CLK_VPP0_GALS_VPP1_LARB5 19
#define CLK_VPP0_GALS_VPP1_LARB6 20
#define CLK_VPP0_SMI_REORDER 21
#define CLK_VPP0_SMI_IOMMU 22
#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23
#define CLK_VPP0_MDP_RDMA 24
#define CLK_VPP0_MDP_WROT 25
#define CLK_VPP0_GALS_EMI0_EMI1 26
#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27
#define CLK_VPP0_SMI_RSI 28
#define CLK_VPP0_SMI_COMMON_LARB4 29
#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30
#define CLK_VPP0_GALS_VPP1_WPE 31
#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32
#define CLK_VPP0_FAKE_ENG 33
#define CLK_VPP0_MDP_HDR 34
#define CLK_VPP0_MDP_TDSHP 35
#define CLK_VPP0_MDP_COLOR 36
#define CLK_VPP0_MDP_OVL 37
#define CLK_VPP0_WARP0_RELAY 38
#define CLK_VPP0_WARP0_MDP_DL_ASYNC 39
#define CLK_VPP0_WARP1_RELAY 40
#define CLK_VPP0_WARP1_MDP_DL_ASYNC 41
#define CLK_VPP0_NR_CLK 42
/* WPESYS */
#define CLK_WPE_VPP0 0
#define CLK_WPE_VPP1 1
#define CLK_WPE_SMI_LARB7 2
#define CLK_WPE_SMI_LARB8 3
#define CLK_WPE_EVENT_TX 4
#define CLK_WPE_SMI_LARB7_P 5
#define CLK_WPE_SMI_LARB8_P 6
#define CLK_WPE_NR_CLK 7
/* WPESYS_VPP0 */
#define CLK_WPE_VPP0_VECI 0
#define CLK_WPE_VPP0_VEC2I 1
#define CLK_WPE_VPP0_VEC3I 2
#define CLK_WPE_VPP0_WPEO 3
#define CLK_WPE_VPP0_MSKO 4
#define CLK_WPE_VPP0_VGEN 5
#define CLK_WPE_VPP0_EXT 6
#define CLK_WPE_VPP0_VFC 7
#define CLK_WPE_VPP0_CACH0_TOP 8
#define CLK_WPE_VPP0_CACH0_DMA 9
#define CLK_WPE_VPP0_CACH1_TOP 10
#define CLK_WPE_VPP0_CACH1_DMA 11
#define CLK_WPE_VPP0_CACH2_TOP 12
#define CLK_WPE_VPP0_CACH2_DMA 13
#define CLK_WPE_VPP0_CACH3_TOP 14
#define CLK_WPE_VPP0_CACH3_DMA 15
#define CLK_WPE_VPP0_PSP 16
#define CLK_WPE_VPP0_PSP2 17
#define CLK_WPE_VPP0_SYNC 18
#define CLK_WPE_VPP0_C24 19
#define CLK_WPE_VPP0_MDP_CROP 20
#define CLK_WPE_VPP0_ISP_CROP 21
#define CLK_WPE_VPP0_TOP 22
#define CLK_WPE_VPP0_NR_CLK 23
/* WPESYS_VPP1 */
#define CLK_WPE_VPP1_VECI 0
#define CLK_WPE_VPP1_VEC2I 1
#define CLK_WPE_VPP1_VEC3I 2
#define CLK_WPE_VPP1_WPEO 3
#define CLK_WPE_VPP1_MSKO 4
#define CLK_WPE_VPP1_VGEN 5
#define CLK_WPE_VPP1_EXT 6
#define CLK_WPE_VPP1_VFC 7
#define CLK_WPE_VPP1_CACH0_TOP 8
#define CLK_WPE_VPP1_CACH0_DMA 9
#define CLK_WPE_VPP1_CACH1_TOP 10
#define CLK_WPE_VPP1_CACH1_DMA 11
#define CLK_WPE_VPP1_CACH2_TOP 12
#define CLK_WPE_VPP1_CACH2_DMA 13
#define CLK_WPE_VPP1_CACH3_TOP 14
#define CLK_WPE_VPP1_CACH3_DMA 15
#define CLK_WPE_VPP1_PSP 16
#define CLK_WPE_VPP1_PSP2 17
#define CLK_WPE_VPP1_SYNC 18
#define CLK_WPE_VPP1_C24 19
#define CLK_WPE_VPP1_MDP_CROP 20
#define CLK_WPE_VPP1_ISP_CROP 21
#define CLK_WPE_VPP1_TOP 22
#define CLK_WPE_VPP1_NR_CLK 23
/* VPPSYS1 */
#define CLK_VPP1_SVPP1_MDP_OVL 0
#define CLK_VPP1_SVPP1_MDP_TCC 1
#define CLK_VPP1_SVPP1_MDP_WROT 2
#define CLK_VPP1_SVPP1_VPP_PAD 3
#define CLK_VPP1_SVPP2_MDP_WROT 4
#define CLK_VPP1_SVPP2_VPP_PAD 5
#define CLK_VPP1_SVPP3_MDP_WROT 6
#define CLK_VPP1_SVPP3_VPP_PAD 7
#define CLK_VPP1_SVPP1_MDP_RDMA 8
#define CLK_VPP1_SVPP1_MDP_FG 9
#define CLK_VPP1_SVPP2_MDP_RDMA 10
#define CLK_VPP1_SVPP2_MDP_FG 11
#define CLK_VPP1_SVPP3_MDP_RDMA 12
#define CLK_VPP1_SVPP3_MDP_FG 13
#define CLK_VPP1_VPP_SPLIT 14
#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15
#define CLK_VPP1_SVPP1_MDP_TDSHP 16
#define CLK_VPP1_SVPP1_MDP_COLOR 17
#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18
#define CLK_VPP1_SVPP2_VPP_MERGE 19
#define CLK_VPP1_SVPP2_MDP_COLOR 20
#define CLK_VPP1_VPPSYS1_GALS 21
#define CLK_VPP1_SVPP3_VPP_MERGE 22
#define CLK_VPP1_SVPP3_MDP_COLOR 23
#define CLK_VPP1_VPPSYS1_LARB 24
#define CLK_VPP1_SVPP1_MDP_RSZ 25
#define CLK_VPP1_SVPP1_MDP_HDR 26
#define CLK_VPP1_SVPP1_MDP_AAL 27
#define CLK_VPP1_SVPP2_MDP_HDR 28
#define CLK_VPP1_SVPP2_MDP_AAL 29
#define CLK_VPP1_DL_ASYNC 30
#define CLK_VPP1_LARB5_FAKE_ENG 31
#define CLK_VPP1_SVPP3_MDP_HDR 32
#define CLK_VPP1_SVPP3_MDP_AAL 33
#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34
#define CLK_VPP1_LARB6_FAKE_ENG 35
#define CLK_VPP1_SVPP2_MDP_RSZ 36
#define CLK_VPP1_SVPP3_MDP_RSZ 37
#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38
#define CLK_VPP1_DISP_MUTEX 39
#define CLK_VPP1_SVPP2_MDP_TDSHP 40
#define CLK_VPP1_SVPP3_MDP_TDSHP 41
#define CLK_VPP1_VPP0_DL1_RELAY 42
#define CLK_VPP1_HDMI_META 43
#define CLK_VPP1_VPP_SPLIT_HDMI 44
#define CLK_VPP1_DGI_IN 45
#define CLK_VPP1_DGI_OUT 46
#define CLK_VPP1_VPP_SPLIT_DGI 47
#define CLK_VPP1_VPP0_DL_ASYNC 48
#define CLK_VPP1_VPP0_DL_RELAY 49
#define CLK_VPP1_VPP_SPLIT_26M 50
#define CLK_VPP1_NR_CLK 51
/* IMGSYS */
#define CLK_IMG_LARB9 0
#define CLK_IMG_TRAW0 1
#define CLK_IMG_TRAW1 2
#define CLK_IMG_TRAW2 3
#define CLK_IMG_TRAW3 4
#define CLK_IMG_DIP0 5
#define CLK_IMG_WPE0 6
#define CLK_IMG_IPE 7
#define CLK_IMG_DIP1 8
#define CLK_IMG_WPE1 9
#define CLK_IMG_GALS 10
#define CLK_IMG_NR_CLK 11
/* IMGSYS1_DIP_TOP */
#define CLK_IMG1_DIP_TOP_LARB10 0
#define CLK_IMG1_DIP_TOP_DIP_TOP 1
#define CLK_IMG1_DIP_TOP_NR_CLK 2
/* IMGSYS1_DIP_NR */
#define CLK_IMG1_DIP_NR_RESERVE 0
#define CLK_IMG1_DIP_NR_DIP_NR 1
#define CLK_IMG1_DIP_NR_NR_CLK 2
/* IMGSYS1_WPE */
#define CLK_IMG1_WPE_LARB11 0
#define CLK_IMG1_WPE_WPE 1
#define CLK_IMG1_WPE_NR_CLK 2
/* IPESYS */
#define CLK_IPE_DPE 0
#define CLK_IPE_FDVT 1
#define CLK_IPE_ME 2
#define CLK_IPE_TOP 3
#define CLK_IPE_SMI_LARB12 4
#define CLK_IPE_NR_CLK 5
/* CAMSYS */
#define CLK_CAM_LARB13 0
#define CLK_CAM_LARB14 1
#define CLK_CAM_MAIN_CAM 2
#define CLK_CAM_MAIN_CAMTG 3
#define CLK_CAM_SENINF 4
#define CLK_CAM_GCAMSVA 5
#define CLK_CAM_GCAMSVB 6
#define CLK_CAM_GCAMSVC 7
#define CLK_CAM_SCAMSA 8
#define CLK_CAM_SCAMSB 9
#define CLK_CAM_CAMSV_TOP 10
#define CLK_CAM_CAMSV_CQ 11
#define CLK_CAM_ADL 12
#define CLK_CAM_ASG 13
#define CLK_CAM_PDA 14
#define CLK_CAM_FAKE_ENG 15
#define CLK_CAM_MAIN_MRAW0 16
#define CLK_CAM_MAIN_MRAW1 17
#define CLK_CAM_MAIN_MRAW2 18
#define CLK_CAM_MAIN_MRAW3 19
#define CLK_CAM_CAM2MM0_GALS 20
#define CLK_CAM_CAM2MM1_GALS 21
#define CLK_CAM_CAM2SYS_GALS 22
#define CLK_CAM_NR_CLK 23
/* CAMSYS_RAWA */
#define CLK_CAM_RAWA_LARBX 0
#define CLK_CAM_RAWA_CAM 1
#define CLK_CAM_RAWA_CAMTG 2
#define CLK_CAM_RAWA_NR_CLK 3
/* CAMSYS_YUVA */
#define CLK_CAM_YUVA_LARBX 0
#define CLK_CAM_YUVA_CAM 1
#define CLK_CAM_YUVA_CAMTG 2
#define CLK_CAM_YUVA_NR_CLK 3
/* CAMSYS_RAWB */
#define CLK_CAM_RAWB_LARBX 0
#define CLK_CAM_RAWB_CAM 1
#define CLK_CAM_RAWB_CAMTG 2
#define CLK_CAM_RAWB_NR_CLK 3
/* CAMSYS_YUVB */
#define CLK_CAM_YUVB_LARBX 0
#define CLK_CAM_YUVB_CAM 1
#define CLK_CAM_YUVB_CAMTG 2
#define CLK_CAM_YUVB_NR_CLK 3
/* CAMSYS_MRAW */
#define CLK_CAM_MRAW_LARBX 0
#define CLK_CAM_MRAW_CAMTG 1
#define CLK_CAM_MRAW_MRAW0 2
#define CLK_CAM_MRAW_MRAW1 3
#define CLK_CAM_MRAW_MRAW2 4
#define CLK_CAM_MRAW_MRAW3 5
#define CLK_CAM_MRAW_NR_CLK 6
/* CCUSYS */
#define CLK_CCU_LARB18 0
#define CLK_CCU_AHB 1
#define CLK_CCU_CCU0 2
#define CLK_CCU_CCU1 3
#define CLK_CCU_NR_CLK 4
/* VDECSYS_SOC */
#define CLK_VDEC_SOC_LARB1 0
#define CLK_VDEC_SOC_LAT 1
#define CLK_VDEC_SOC_VDEC 2
#define CLK_VDEC_SOC_NR_CLK 3
/* VDECSYS */
#define CLK_VDEC_LARB1 0
#define CLK_VDEC_LAT 1
#define CLK_VDEC_VDEC 2
#define CLK_VDEC_NR_CLK 3
/* VDECSYS_CORE1 */
#define CLK_VDEC_CORE1_LARB1 0
#define CLK_VDEC_CORE1_LAT 1
#define CLK_VDEC_CORE1_VDEC 2
#define CLK_VDEC_CORE1_NR_CLK 3
/* APUSYS_PLL */
#define CLK_APUSYS_PLL_APUPLL 0
#define CLK_APUSYS_PLL_NPUPLL 1
#define CLK_APUSYS_PLL_APUPLL1 2
#define CLK_APUSYS_PLL_APUPLL2 3
#define CLK_APUSYS_PLL_NR_CLK 4
/* VENCSYS */
#define CLK_VENC_LARB 0
#define CLK_VENC_VENC 1
#define CLK_VENC_JPGENC 2
#define CLK_VENC_JPGDEC 3
#define CLK_VENC_JPGDEC_C1 4
#define CLK_VENC_GALS 5
#define CLK_VENC_NR_CLK 6
/* VENCSYS_CORE1 */
#define CLK_VENC_CORE1_LARB 0
#define CLK_VENC_CORE1_VENC 1
#define CLK_VENC_CORE1_JPGENC 2
#define CLK_VENC_CORE1_JPGDEC 3
#define CLK_VENC_CORE1_JPGDEC_C1 4
#define CLK_VENC_CORE1_GALS 5
#define CLK_VENC_CORE1_NR_CLK 6
/* VDOSYS0 */
#define CLK_VDO0_DISP_OVL0 0
#define CLK_VDO0_DISP_COLOR0 1
#define CLK_VDO0_DISP_COLOR1 2
#define CLK_VDO0_DISP_CCORR0 3
#define CLK_VDO0_DISP_CCORR1 4
#define CLK_VDO0_DISP_AAL0 5
#define CLK_VDO0_DISP_AAL1 6
#define CLK_VDO0_DISP_GAMMA0 7
#define CLK_VDO0_DISP_GAMMA1 8
#define CLK_VDO0_DISP_DITHER0 9
#define CLK_VDO0_DISP_DITHER1 10
#define CLK_VDO0_DISP_OVL1 11
#define CLK_VDO0_DISP_WDMA0 12
#define CLK_VDO0_DISP_WDMA1 13
#define CLK_VDO0_DISP_RDMA0 14
#define CLK_VDO0_DISP_RDMA1 15
#define CLK_VDO0_DSI0 16
#define CLK_VDO0_DSI1 17
#define CLK_VDO0_DSC_WRAP0 18
#define CLK_VDO0_VPP_MERGE0 19
#define CLK_VDO0_DP_INTF0 20
#define CLK_VDO0_DISP_MUTEX0 21
#define CLK_VDO0_DISP_IL_ROT0 22
#define CLK_VDO0_APB_BUS 23
#define CLK_VDO0_FAKE_ENG0 24
#define CLK_VDO0_FAKE_ENG1 25
#define CLK_VDO0_DL_ASYNC0 26
#define CLK_VDO0_DL_ASYNC1 27
#define CLK_VDO0_DL_ASYNC2 28
#define CLK_VDO0_DL_ASYNC3 29
#define CLK_VDO0_DL_ASYNC4 30
#define CLK_VDO0_DISP_MONITOR0 31
#define CLK_VDO0_DISP_MONITOR1 32
#define CLK_VDO0_DISP_MONITOR2 33
#define CLK_VDO0_DISP_MONITOR3 34
#define CLK_VDO0_DISP_MONITOR4 35
#define CLK_VDO0_SMI_GALS 36
#define CLK_VDO0_SMI_COMMON 37
#define CLK_VDO0_SMI_EMI 38
#define CLK_VDO0_SMI_IOMMU 39
#define CLK_VDO0_SMI_LARB 40
#define CLK_VDO0_SMI_RSI 41
#define CLK_VDO0_DSI0_DSI 42
#define CLK_VDO0_DSI1_DSI 43
#define CLK_VDO0_DP_INTF0_DP_INTF 44
#define CLK_VDO0_NR_CLK 45
/* VDOSYS1 */
#define CLK_VDO1_SMI_LARB2 0
#define CLK_VDO1_SMI_LARB3 1
#define CLK_VDO1_GALS 2
#define CLK_VDO1_FAKE_ENG0 3
#define CLK_VDO1_FAKE_ENG 4
#define CLK_VDO1_MDP_RDMA0 5
#define CLK_VDO1_MDP_RDMA1 6
#define CLK_VDO1_MDP_RDMA2 7
#define CLK_VDO1_MDP_RDMA3 8
#define CLK_VDO1_VPP_MERGE0 9
#define CLK_VDO1_VPP_MERGE1 10
#define CLK_VDO1_VPP_MERGE2 11
#define CLK_VDO1_VPP_MERGE3 12
#define CLK_VDO1_VPP_MERGE4 13
#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14
#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15
#define CLK_VDO1_DISP_MUTEX 16
#define CLK_VDO1_MDP_RDMA4 17
#define CLK_VDO1_MDP_RDMA5 18
#define CLK_VDO1_MDP_RDMA6 19
#define CLK_VDO1_MDP_RDMA7 20
#define CLK_VDO1_DP_INTF0_MM 21
#define CLK_VDO1_DPI0_MM 22
#define CLK_VDO1_DPI1_MM 23
#define CLK_VDO1_DISP_MONITOR 24
#define CLK_VDO1_MERGE0_DL_ASYNC 25
#define CLK_VDO1_MERGE1_DL_ASYNC 26
#define CLK_VDO1_MERGE2_DL_ASYNC 27
#define CLK_VDO1_MERGE3_DL_ASYNC 28
#define CLK_VDO1_MERGE4_DL_ASYNC 29
#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30
#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
#define CLK_VDO1_HDR_VDO_FE0 32
#define CLK_VDO1_HDR_GFX_FE0 33
#define CLK_VDO1_HDR_VDO_BE 34
#define CLK_VDO1_HDR_VDO_FE1 35
#define CLK_VDO1_HDR_GFX_FE1 36
#define CLK_VDO1_DISP_MIXER 37
#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38
#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39
#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40
#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41
#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42
#define CLK_VDO1_DPI0 43
#define CLK_VDO1_DISP_MONITOR_DPI0 44
#define CLK_VDO1_DPI1 45
#define CLK_VDO1_DISP_MONITOR_DPI1 46
#define CLK_VDO1_DPINTF 47
#define CLK_VDO1_DISP_MONITOR_DPINTF 48
#define CLK_VDO1_26M_SLOW 49
#define CLK_VDO1_NR_CLK 50
#endif /* _DT_BINDINGS_CLK_MT8195_H */
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