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Commit a4c75ba8 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'testing/bcmring' into next/cleanups 

This attempts to get the bcmring platform better in line with the
other platforms. Moving the header files below mach/ helps with
the future reorganization for multiplatform kernels, and using
MMIO accessors is generally the right thing.

* testing/bcmring:
  ARM: bcmring: use proper MMIO accessors
  ARM: bcmring: remove include/csp/ subdir
  ARM: bcmring: move cfg_global header to mach/
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 19ec6cac 878040ef
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Showing with 366 additions and 671 deletions
arch/arm/mach-bcmring/arch.c
View file @ a4c75ba8
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
#include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h> #include <mach/csp/chipcHw_inline.h>
#include <cfg_global.h> #include <mach/cfg_global.h>
#include "core.h" #include "core.h"
......
arch/arm/mach-bcmring/core.c
View file @ a4c75ba8
...@@ -43,11 +43,10 @@ ...@@ -43,11 +43,10 @@
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <cfg_global.h> #include <mach/cfg_global.h>
#include "clock.h" #include "clock.h"
#include <csp/secHw.h>
#include <mach/csp/secHw_def.h> #include <mach/csp/secHw_def.h>
#include <mach/csp/chipcHw_inline.h> #include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h> #include <mach/csp/tmrHw_reg.h>
......
arch/arm/mach-bcmring/csp/chipc/chipcHw.c
View file @ a4c75ba8
This diff is collapsed.
arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
View file @ a4c75ba8
...@@ -26,15 +26,15 @@ ...@@ -26,15 +26,15 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/errno.h> #include <linux/errno.h>
#include <csp/stdint.h> #include <linux/types.h>
#include <csp/module.h> #include <linux/export.h>
#include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h> #include <mach/csp/chipcHw_inline.h>
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <csp/delay.h> #include <linux/delay.h>
/* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Constants and Types --------------------------------------- */
/* /*
...@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) ...@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig2 = writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET,
chipcHw_REG_PLL_CONFIG_A_RESET; &pChipcHw->PLLConfig2);
pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
...@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) ...@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
/* Enable CHIPC registers to control the PLL */ /* Enable CHIPC registers to control the PLL */
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
/* Set pre divider to get desired VCO frequency */ /* Set pre divider to get desired VCO frequency */
pChipcHw->PLLPreDivider2 = pllPreDivider2; writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
/* Set NDIV Frac */ /* Set NDIV Frac */
pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
/* This has to be removed once the default values are fixed for PLL2. */ /* This has to be removed once the default values are fixed for PLL2. */
pChipcHw->PLLControl12 = 0x38000700; writel(0x38000700, &pChipcHw->PLLControl12);
pChipcHw->PLLControl22 = 0x00000015; writel(0x00000015, &pChipcHw->PLLControl22);
/* Reset PLL2 */ /* Reset PLL2 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN; chipcHw_REG_PLL_CONFIG_POWER_DOWN,
&pChipcHw->PLLConfig2);
} else { } else {
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN; chipcHw_REG_PLL_CONFIG_POWER_DOWN,
&pChipcHw->PLLConfig2);
} }
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
...@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) ...@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */ /* Remove analog reset and Power on the PLL */
pChipcHw->PLLConfig2 &= writel(readl(&pChipcHw->PLLConfig2) &
~(chipcHw_REG_PLL_CONFIG_A_RESET | ~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN); chipcHw_REG_PLL_CONFIG_POWER_DOWN),
&pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
/* Wait until PLL is locked */ /* Wait until PLL is locked */
while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
; ;
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
/* Remove digital reset */ /* Remove digital reset */
pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; writel(readl(&pChipcHw->PLLConfig2) &
~chipcHw_REG_PLL_CONFIG_D_RESET,
&pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
...@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) ...@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig = writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET,
chipcHw_REG_PLL_CONFIG_A_RESET; &pChipcHw->PLLConfig);
/* Setting VCO frequency */ /* Setting VCO frequency */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pllPreDivider = pllPreDivider =
...@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) ...@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
} }
/* Enable CHIPC registers to control the PLL */ /* Enable CHIPC registers to control the PLL */
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
/* Set pre divider to get desired VCO frequency */ /* Set pre divider to get desired VCO frequency */
pChipcHw->PLLPreDivider = pllPreDivider; writel(pllPreDivider, &pChipcHw->PLLPreDivider);
/* Set NDIV Frac */ /* Set NDIV Frac */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
} else { } else {
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
chipcHw_REG_PLL_DIVIDER_NDIV_f;
} }
/* Reset PLL1 */ /* Reset PLL1 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
} else { } else {
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
} }
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
...@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) ...@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */ /* Remove analog reset and Power on the PLL */
pChipcHw->PLLConfig &= writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
/* Wait until PLL is locked */ /* Wait until PLL is locked */
while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
|| !(pChipcHw-> || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
; ;
/* Remove digital reset */ /* Remove digital reset */
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
} }
...@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ ...@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
pChipcHw->ACLKClock = writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
(pChipcHw->
ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
armBusRatio &
chipcHw_REG_ACLKClock_CLK_DIV_MASK);
/* Set various core component frequencies. The order in which this is done is important for some. */ /* Set various core component frequencies. The order in which this is done is important for some. */
/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
......
arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
View file @ a4c75ba8
...@@ -13,11 +13,11 @@ ...@@ -13,11 +13,11 @@
*****************************************************************************/ *****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h> #include <linux/types.h>
#include <mach/csp/chipcHw_def.h> #include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h> #include <mach/csp/chipcHw_inline.h>
#include <csp/intcHw.h> #include <mach/csp/intcHw_reg.h>
#include <csp/cache.h> #include <asm/cacheflush.h>
/* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Constants and Types --------------------------------------- */
/* ---- Private Variables ------------------------------------------------- */ /* ---- Private Variables ------------------------------------------------- */
...@@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask) ...@@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask)
chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
} }
/* Bypass the PLL clocks before reboot */ /* Bypass the PLL clocks before reboot */
pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; &pChipcHw->UARTClock);
writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
&pChipcHw->SPIClock);
/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
do { do {
((uint32_t *) MM_IO_BASE_ARAM)[i] = writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
((uint32_t *) &chipcHw_reset_run_from_aram)[i];
i++; i++;
} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
CSP_CACHE_FLUSH_ALL; flush_cache_all();
/* run the function from ARAM */ /* run the function from ARAM */
runFunc(); runFunc();
......
arch/arm/mach-bcmring/csp/dmac/dmacHw.c
View file @ a4c75ba8
...@@ -25,11 +25,11 @@ ...@@ -25,11 +25,11 @@
/****************************************************************************/ /****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h> #include <linux/types.h>
#include <csp/string.h> #include <linux/string.h>
#include <stddef.h> #include <linux/stddef.h>
#include <csp/dmacHw.h> #include <mach/csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h> #include <mach/csp/dmacHw_reg.h>
#include <mach/csp/dmacHw_priv.h> #include <mach/csp/dmacHw_priv.h>
#include <mach/csp/chipcHw_inline.h> #include <mach/csp/chipcHw_inline.h>
...@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl ...@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl
) { ) {
uint32_t val = 0; uint32_t val = 0;
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
dmacHw_MISC_t *pMiscReg = dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
(dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
switch (pCblk->channel) { switch (pCblk->channel) {
case 0: case 0:
val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
break; break;
case 1: case 1:
val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
break; break;
case 2: case 2:
val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
break; break;
case 3: case 3:
val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
break; break;
case 4: case 4:
val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
break; break;
case 5: case 5:
val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
break; break;
case 6: case 6:
val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
break; break;
case 7: case 7:
val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
break; break;
} }
......
arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
View file @ a4c75ba8
...@@ -26,10 +26,10 @@ ...@@ -26,10 +26,10 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h> #include <linux/types.h>
#include <stddef.h> #include <linux/stddef.h>
#include <csp/dmacHw.h> #include <mach/csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h> #include <mach/csp/dmacHw_reg.h>
#include <mach/csp/dmacHw_priv.h> #include <mach/csp/dmacHw_priv.h>
......
arch/arm/mach-bcmring/csp/tmr/tmrHw.c
View file @ a4c75ba8
...@@ -26,10 +26,10 @@ ...@@ -26,10 +26,10 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/errno.h> #include <linux/errno.h>
#include <csp/stdint.h> #include <linux/types.h>
#include <csp/tmrHw.h> #include <mach/csp/tmrHw.h>
#include <mach/csp/tmrHw_reg.h> #include <mach/csp/tmrHw_reg.h>
#define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0
......
arch/arm/mach-bcmring/include/cfg_global.h deleted 100644 → 0
View file @ 19ec6cac
#ifndef _CFG_GLOBAL_H_
#define _CFG_GLOBAL_H_
#include <cfg_global_defines.h>
#define CFG_GLOBAL_CHIP BCM11107
#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
#define CFG_GLOBAL_CHIP_REV 0xB0
#define CFG_GLOBAL_RAM_SIZE 0x10000000
#define CFG_GLOBAL_RAM_BASE 0x00000000
#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
#endif /* _CFG_GLOBAL_H_ */
arch/arm/mach-bcmring/include/csp/cache.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_CACHE_H
#define CSP_CACHE_H
/* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h>
/* ---- Public Constants and Types --------------------------------------- */
#if defined(__KERNEL__) && !defined(STANDALONE)
#include <asm/cacheflush.h>
#define CSP_CACHE_FLUSH_ALL flush_cache_all()
#else
#define CSP_CACHE_FLUSH_ALL
#endif
#endif /* CSP_CACHE_H */
arch/arm/mach-bcmring/include/csp/delay.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_DELAY_H
#define CSP_DELAY_H
/* ---- Include Files ---------------------------------------------------- */
/* Some CSP routines require use of the following delay routines. Use the OS */
/* version if available, otherwise use a CSP specific definition. */
/* void udelay(unsigned long usecs); */
/* void mdelay(unsigned long msecs); */
#if defined(__KERNEL__) && !defined(STANDALONE)
#include <linux/delay.h>
#else
#include <mach/csp/delay.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_DELAY_H */
arch/arm/mach-bcmring/include/csp/errno.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_ERRNO_H
#define CSP_ERRNO_H
/* ---- Include Files ---------------------------------------------------- */
#if defined(__KERNEL__)
#include <linux/errno.h>
#elif defined(CSP_SIMULATION)
#include <asm-generic/errno.h>
#else
#include <errno.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_ERRNO_H */
arch/arm/mach-bcmring/include/csp/intcHw.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file intcHw.h
*
* @brief generic interrupt controller API
*
* @note
* None
*/
/****************************************************************************/
#ifndef _INTCHW_H
#define _INTCHW_H
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/intcHw_reg.h>
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
static inline void intcHw_irq_disable(void *basep, uint32_t mask);
static inline void intcHw_irq_enable(void *basep, uint32_t mask);
#endif /* _INTCHW_H */
arch/arm/mach-bcmring/include/csp/module.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_MODULE_H
#define CSP_MODULE_H
/* ---- Include Files ---------------------------------------------------- */
#ifdef __KERNEL__
#include <linux/module.h>
#else
#define EXPORT_SYMBOL(symbol)
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_MODULE_H */
arch/arm/mach-bcmring/include/csp/secHw.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file secHw.h
*
* @brief Definitions for accessing low level security features
*
*/
/****************************************************************************/
#ifndef SECHW_H
#define SECHW_H
typedef void (*secHw_FUNC_t) (void);
typedef enum {
secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */
secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */
} secHw_MODE;
/****************************************************************************/
/**
* @brief Requesting to execute the function in secure mode
*
* This function requests the given function to run in secure mode
*
*/
/****************************************************************************/
void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */
);
/****************************************************************************/
/**
* @brief Sets the mode
*
* his function sets the processor mode (secure/non-secure)
*
*/
/****************************************************************************/
void secHw_SetMode(secHw_MODE /* Processor mode */
);
/****************************************************************************/
/**
* @brief Get the current mode
*
* This function retieves the processor mode (secure/non-secure)
*
*/
/****************************************************************************/
void secHw_GetMode(secHw_MODE *);
#endif /* SECHW_H */
arch/arm/mach-bcmring/include/csp/stdint.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_STDINT_H
#define CSP_STDINT_H
/* ---- Include Files ---------------------------------------------------- */
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_STDINT_H */
arch/arm/mach-bcmring/include/csp/string.h deleted 100644 → 0
View file @ 19ec6cac
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_STRING_H
#define CSP_STRING_H
/* ---- Include Files ---------------------------------------------------- */
#ifdef __KERNEL__
#include <linux/string.h>
#else
#include <string.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_STRING_H */
arch/arm/mach-bcmring/include/cfg_global_defines.h → arch/arm/mach-bcmring/include/mach/cfg_global.h
View file @ a4c75ba8
...@@ -38,3 +38,14 @@ ...@@ -38,3 +38,14 @@
#define IMAGE_HEADER_SIZE_CHECKSUM 4 #define IMAGE_HEADER_SIZE_CHECKSUM 4
#endif #endif
#ifndef _CFG_GLOBAL_H_
#define _CFG_GLOBAL_H_
#define CFG_GLOBAL_CHIP BCM11107
#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
#define CFG_GLOBAL_CHIP_REV 0xB0
#define CFG_GLOBAL_RAM_SIZE 0x10000000
#define CFG_GLOBAL_RAM_BASE 0x00000000
#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
#endif /* _CFG_GLOBAL_H_ */
arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
View file @ a4c75ba8
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/cap.h> #include <mach/csp/cap.h>
#include <cfg_global.h> #include <mach/cfg_global.h>
/* ---- Public Constants and Types --------------------------------------- */ /* ---- Public Constants and Types --------------------------------------- */
#define CAP_CONFIG0_VPM_DIS 0x00000001 #define CAP_CONFIG0_VPM_DIS 0x00000001
......
arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
View file @ a4c75ba8
...@@ -17,9 +17,9 @@ ...@@ -17,9 +17,9 @@
/* ---- Include Files ----------------------------------------------------- */ /* ---- Include Files ----------------------------------------------------- */
#include <csp/stdint.h> #include <linux/types.h>
#include <csp/errno.h> #include <linux/errno.h>
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <mach/csp/chipcHw_reg.h> #include <mach/csp/chipcHw_reg.h>
/* ---- Public Constants and Types ---------------------------------------- */ /* ---- Public Constants and Types ---------------------------------------- */
......
arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
View file @ a4c75ba8
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#define CHIPCHW_REG_H #define CHIPCHW_REG_H
#include <mach/csp/mm_io.h> #include <mach/csp/mm_io.h>
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <mach/csp/ddrcReg.h> #include <mach/csp/ddrcReg.h>
#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC
...@@ -131,8 +131,8 @@ typedef struct { ...@@ -131,8 +131,8 @@ typedef struct {
uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
} chipcHw_REG_t; } chipcHw_REG_t;
#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) #define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) #define pChipcPhysical (MM_ADDR_IO_CHIPC)
#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
#define chipcHw_REG_CHIPID_BASE_SHIFT 12 #define chipcHw_REG_CHIPID_BASE_SHIFT 12
......
arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
View file @ a4c75ba8
...@@ -30,8 +30,8 @@ extern "C" { ...@@ -30,8 +30,8 @@ extern "C" {
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <csp/stdint.h> #include <linux/types.h>
#include <mach/csp/mm_io.h> #include <mach/csp/mm_io.h>
...@@ -416,7 +416,7 @@ extern "C" { ...@@ -416,7 +416,7 @@ extern "C" {
} ddrcReg_PHY_ADDR_CTL_REG_t; } ddrcReg_PHY_ADDR_CTL_REG_t;
#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) #define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
/* @todo These SS definitions are duplicates of ones below */ /* @todo These SS definitions are duplicates of ones below */
......
arch/arm/mach-bcmring/include/csp/dmacHw.h → arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
View file @ a4c75ba8
...@@ -23,9 +23,9 @@ ...@@ -23,9 +23,9 @@
#ifndef _DMACHW_H #ifndef _DMACHW_H
#define _DMACHW_H #define _DMACHW_H
#include <stddef.h> #include <linux/stddef.h>
#include <csp/stdint.h> #include <linux/types.h>
#include <mach/csp/dmacHw_reg.h> #include <mach/csp/dmacHw_reg.h>
/* Define DMA Channel ID using DMA controller number (m) and channel number (c). /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
......
arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
View file @ a4c75ba8
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#ifndef _DMACHW_PRIV_H #ifndef _DMACHW_PRIV_H
#define _DMACHW_PRIV_H #define _DMACHW_PRIV_H
#include <csp/stdint.h> #include <linux/types.h>
/* Data type for DMA Link List Item */ /* Data type for DMA Link List Item */
typedef struct { typedef struct {
......
arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
View file @ a4c75ba8
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <cfg_global.h> #include <mach/cfg_global.h>
#include <mach/csp/cap_inline.h> #include <mach/csp/cap_inline.h>
#if defined(__KERNEL__) #if defined(__KERNEL__)
......
arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
View file @ a4c75ba8
...@@ -27,8 +27,8 @@ ...@@ -27,8 +27,8 @@
#define _INTCHW_REG_H #define _INTCHW_REG_H
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h> #include <linux/types.h>
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <mach/csp/mm_io.h> #include <mach/csp/mm_io.h>
/* ---- Public Constants and Types --------------------------------------- */ /* ---- Public Constants and Types --------------------------------------- */
...@@ -37,9 +37,9 @@ ...@@ -37,9 +37,9 @@
#define INTCHW_NUM_INTC 3 #define INTCHW_NUM_INTC 3
/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) #define INTCHW_INTC0 (MM_IO_BASE_INTC0)
#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) #define INTCHW_INTC1 (MM_IO_BASE_INTC1)
#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) #define INTCHW_SINTC (MM_IO_BASE_SINTC)
/* INTC0 - interrupt controller 0 */ /* INTC0 - interrupt controller 0 */
#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
...@@ -232,15 +232,15 @@ ...@@ -232,15 +232,15 @@
/* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */ /* ---- Public Function Prototypes --------------------------------------- */
/* Clear one or more IRQ interrupts. */ /* Clear one or more IRQ interrupts. */
static inline void intcHw_irq_disable(void *basep, uint32_t mask) static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
{ {
__REG32(basep + INTCHW_INTENCLEAR) = mask; writel(mask, basep + INTCHW_INTENCLEAR);
} }
/* Enables one or more IRQ interrupts. */ /* Enables one or more IRQ interrupts. */
static inline void intcHw_irq_enable(void *basep, uint32_t mask) static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
{ {
__REG32(basep + INTCHW_INTENABLE) = mask; writel(mask, basep + INTCHW_INTENABLE);
} }
#endif /* _INTCHW_REG_H */ #endif /* _INTCHW_REG_H */
arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
View file @ a4c75ba8
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#if !defined(CSP_SIMULATION) #if !defined(CSP_SIMULATION)
#include <cfg_global.h> #include <mach/cfg_global.h>
#endif #endif
/* ---- Public Constants and Types --------------------------------------- */ /* ---- Public Constants and Types --------------------------------------- */
......
arch/arm/mach-bcmring/include/mach/csp/mm_io.h
View file @ a4c75ba8
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#include <mach/csp/mm_addr.h> #include <mach/csp/mm_addr.h>
#if !defined(CSP_SIMULATION) #if !defined(CSP_SIMULATION)
#include <cfg_global.h> #include <mach/cfg_global.h>
#endif #endif
/* ---- Public Constants and Types --------------------------------------- */ /* ---- Public Constants and Types --------------------------------------- */
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
#ifdef __ASSEMBLY__ #ifdef __ASSEMBLY__
#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
#else #else
#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ #define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
#endif #endif
#endif #endif
...@@ -60,8 +60,8 @@ ...@@ -60,8 +60,8 @@
#ifdef __ASSEMBLY__ #ifdef __ASSEMBLY__
#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
#else #else
#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ #define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
#endif #endif
#endif #endif
......
arch/arm/mach-bcmring/include/csp/reg.h → arch/arm/mach-bcmring/include/mach/csp/reg.h
View file @ a4c75ba8
...@@ -25,13 +25,14 @@ ...@@ -25,13 +25,14 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h> #include <linux/types.h>
#include <linux/io.h>
/* ---- Public Constants and Types --------------------------------------- */ /* ---- Public Constants and Types --------------------------------------- */
#define __REG32(x) (*((volatile uint32_t *)(x))) #define __REG32(x) (*((volatile uint32_t __iomem *)(x)))
#define __REG16(x) (*((volatile uint16_t *)(x))) #define __REG16(x) (*((volatile uint16_t __iomem *)(x)))
#define __REG8(x) (*((volatile uint8_t *) (x))) #define __REG8(x) (*((volatile uint8_t __iomem *) (x)))
/* Macros used to define a sequence of reserved registers. The start / end */ /* Macros used to define a sequence of reserved registers. The start / end */
/* are byte offsets in the particular register definition, with the "end" */ /* are byte offsets in the particular register definition, with the "end" */
...@@ -84,31 +85,31 @@ ...@@ -84,31 +85,31 @@
#endif #endif
static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
*reg &= value; __raw_writel(__raw_readl(reg) & value, reg);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
*reg |= value; __raw_writel(__raw_readl(reg) | value, reg);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
uint32_t value) uint32_t value)
{ {
REG_LOCAL_IRQ_SAVE; REG_LOCAL_IRQ_SAVE;
*reg = (*reg & mask) | value; __raw_writel((__raw_readl(reg) & mask) | value, reg);
REG_LOCAL_IRQ_RESTORE; REG_LOCAL_IRQ_RESTORE;
} }
static inline void reg32_write(volatile uint32_t *reg, uint32_t value) static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
{ {
*reg = value; __raw_writel(value, reg);
} }
#endif /* CSP_REG_H */ #endif /* CSP_REG_H */
arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
View file @ a4c75ba8
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
/****************************************************************************/ /****************************************************************************/
static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
) { ) {
secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
if (mask & 0x0000FFFF) { if (mask & 0x0000FFFF) {
regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
...@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK ...@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK
/****************************************************************************/ /****************************************************************************/
static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
) { ) {
secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
if (mask & 0x0000FFFF) { if (mask & 0x0000FFFF) {
regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
} }
if (mask & 0xFFFF0000) { if (mask & 0xFFFF0000) {
regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
} }
} }
...@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA ...@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA
/****************************************************************************/ /****************************************************************************/
static inline uint32_t secHw_getStatus(void) static inline uint32_t secHw_getStatus(void)
{ {
secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
return (regp->reg[1].status << 16) + regp->reg[0].status; return (regp->reg[1].status << 16) + regp->reg[0].status;
} }
......
arch/arm/mach-bcmring/include/csp/tmrHw.h → arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
View file @ a4c75ba8
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
#ifndef _TMRHW_H #ifndef _TMRHW_H
#define _TMRHW_H #define _TMRHW_H
#include <csp/stdint.h> #include <linux/types.h>
typedef uint32_t tmrHw_ID_t; /* Timer ID */ typedef uint32_t tmrHw_ID_t; /* Timer ID */
typedef uint32_t tmrHw_COUNT_t; /* Timer count */ typedef uint32_t tmrHw_COUNT_t; /* Timer count */
......
arch/arm/mach-bcmring/include/mach/dma.h
View file @ a4c75ba8
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/semaphore.h> #include <linux/semaphore.h>
#include <csp/dmacHw.h> #include <mach/csp/dmacHw.h>
#include <mach/timer.h> #include <mach/timer.h>
/* ---- Constants and Types ---------------------------------------------- */ /* ---- Constants and Types ---------------------------------------------- */
......
arch/arm/mach-bcmring/include/mach/hardware.h
View file @ a4c75ba8
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
#define __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h> #include <asm/sizes.h>
#include <cfg_global.h> #include <mach/cfg_global.h>
#include <mach/csp/mm_io.h> #include <mach/csp/mm_io.h>
/* Hardware addresses of major areas. /* Hardware addresses of major areas.
......
arch/arm/mach-bcmring/include/mach/reg_nand.h
View file @ a4c75ba8
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#define __ASM_ARCH_REG_NAND_H #define __ASM_ARCH_REG_NAND_H
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <mach/reg_umi.h> #include <mach/reg_umi.h>
/* ---- Constants and Types ---------------------------------------------- */ /* ---- Constants and Types ---------------------------------------------- */
......
arch/arm/mach-bcmring/include/mach/reg_umi.h
View file @ a4c75ba8
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#define __ASM_ARCH_REG_UMI_H #define __ASM_ARCH_REG_UMI_H
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <csp/reg.h> #include <mach/csp/reg.h>
#include <mach/csp/mm_io.h> #include <mach/csp/mm_io.h>
/* ---- Constants and Types ---------------------------------------------- */ /* ---- Constants and Types ---------------------------------------------- */
...@@ -233,5 +233,5 @@ ...@@ -233,5 +233,5 @@
#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
/* location within a page (512 byte) */ /* location within a page (512 byte) */
#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) #define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
#endif #endif
arch/arm/mach-bcmring/mm.c
View file @ a4c75ba8
...@@ -20,12 +20,12 @@ ...@@ -20,12 +20,12 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/csp/mm_io.h> #include <mach/csp/mm_io.h>
#define IO_DESC(va, sz) { .virtual = va, \ #define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \ .length = sz, \
.type = MT_DEVICE } .type = MT_DEVICE }
#define MEM_DESC(va, sz) { .virtual = va, \ #define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \ .length = sz, \
.type = MT_MEMORY } .type = MT_MEMORY }
......
arch/arm/mach-bcmring/timer.c
View file @ a4c75ba8
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/module.h> #include <linux/module.h>
#include <csp/tmrHw.h> #include <mach/csp/tmrHw.h>
#include <mach/timer.h> #include <mach/timer.h>
/* The core.c file initializes timers 1 and 3 as a linux clocksource. */ /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
......
drivers/mtd/nand/bcm_umi_nand.c
View file @ a4c75ba8
...@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd) ...@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
int bcm_umi_nand_inithw(void) int bcm_umi_nand_inithw(void)
{ {
/* Configure nand timing parameters */ /* Configure nand timing parameters */
REG_UMI_NAND_TCR &= ~0x7ffff; writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
/* enable software control of CS */ /* enable software control of CS */
REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
#endif #endif
/* keep NAND chip select asserted */ /* keep NAND chip select asserted */
REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
/* enable writes to flash */ /* enable writes to flash */
REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
nand_bcm_umi_wait_till_ready(); nand_bcm_umi_wait_till_ready();
......
drivers/mtd/nand/nand_bcm_umi.h
View file @ a4c75ba8
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
/* ---- Include Files ---------------------------------------------------- */ /* ---- Include Files ---------------------------------------------------- */
#include <mach/reg_umi.h> #include <mach/reg_umi.h>
#include <mach/reg_nand.h> #include <mach/reg_nand.h>
#include <cfg_global.h> #include <mach/cfg_global.h>
/* ---- Constants and Types ---------------------------------------------- */ /* ---- Constants and Types ---------------------------------------------- */
#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
...@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, ...@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
/* Check in device is ready */ /* Check in device is ready */
static inline int nand_bcm_umi_dev_ready(void) static inline int nand_bcm_umi_dev_ready(void)
{ {
return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
} }
/* Wait until device is ready */ /* Wait until device is ready */
...@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void) ...@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
static inline void nand_bcm_umi_hamming_enable_hwecc(void) static inline void nand_bcm_umi_hamming_enable_hwecc(void)
{ {
/* disable and reset ECC, 512 byte page */ /* disable and reset ECC, 512 byte page */
REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
REG_UMI_NAND_ECC_CSR_256BYTE); REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
/* enable ECC */ /* enable ECC */
REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
&REG_UMI_NAND_ECC_CSR);
} }
#if NAND_ECC_BCH #if NAND_ECC_BCH
...@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void) ...@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
static inline void nand_bcm_umi_bch_enable_read_hwecc(void) static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
{ {
/* disable and reset ECC */ /* disable and reset ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
/* Turn on ECC */ /* Turn on ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
} }
/* Enable BCH Write ECC */ /* Enable BCH Write ECC */
static inline void nand_bcm_umi_bch_enable_write_hwecc(void) static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
{ {
/* disable and reset ECC */ /* disable and reset ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
/* Turn on ECC */ /* Turn on ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
} }
/* Config number of BCH ECC bytes */ /* Config number of BCH ECC bytes */
...@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) ...@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
uint32_t numBits = numEccBytes * 8; uint32_t numBits = numEccBytes * 8;
/* disable and reset ECC */ /* disable and reset ECC */
REG_UMI_BCH_CTRL_STATUS = writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; &REG_UMI_BCH_CTRL_STATUS);
/* Every correctible bit requires 13 ECC bits */ /* Every correctible bit requires 13 ECC bits */
tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
...@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) ...@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
/* Write the settings */ /* Write the settings */
REG_UMI_BCH_N = nValue; writel(nValue, &REG_UMI_BCH_N);
REG_UMI_BCH_T = tValue; writel(tValue, &REG_UMI_BCH_T);
REG_UMI_BCH_K = kValue; writel(kValue, &REG_UMI_BCH_K);
} }
/* Pause during ECC read calculation to skip bytes in OOB */ /* Pause during ECC read calculation to skip bytes in OOB */
static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
{ {
REG_UMI_BCH_CTRL_STATUS = writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
} }
/* Resume during ECC read calculation after skipping bytes in OOB */ /* Resume during ECC read calculation after skipping bytes in OOB */
static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
{ {
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
} }
/* Poll read ECC calc to check when hardware completes */ /* Poll read ECC calc to check when hardware completes */
...@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) ...@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
do { do {
/* wait for ECC to be valid */ /* wait for ECC to be valid */
regVal = REG_UMI_BCH_CTRL_STATUS; regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
return regVal; return regVal;
...@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) ...@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
{ {
/* wait for ECC to be valid */ /* wait for ECC to be valid */
while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
== 0) == 0)
; ;
} }
...@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, ...@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
if (pageSize != NAND_DATA_ACCESS_SIZE) { if (pageSize != NAND_DATA_ACCESS_SIZE) {
/* skip BI */ /* skip BI */
#if defined(__KERNEL__) && !defined(STANDALONE) #if defined(__KERNEL__) && !defined(STANDALONE)
*oobp++ = REG_NAND_DATA8; *oobp++ = readb(&REG_NAND_DATA8);
#else #else
REG_NAND_DATA8; readb(&REG_NAND_DATA8);
#endif #endif
numToRead--; numToRead--;
} }
...@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, ...@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
while (numToRead > numEccBytes) { while (numToRead > numEccBytes) {
/* skip free oob region */ /* skip free oob region */
#if defined(__KERNEL__) && !defined(STANDALONE) #if defined(__KERNEL__) && !defined(STANDALONE)
*oobp++ = REG_NAND_DATA8; *oobp++ = readb(&REG_NAND_DATA8);
#else #else
REG_NAND_DATA8; readb(&REG_NAND_DATA8);
#endif #endif
numToRead--; numToRead--;
} }
...@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, ...@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
while (numToRead > 11) { while (numToRead > 11) {
#if defined(__KERNEL__) && !defined(STANDALONE) #if defined(__KERNEL__) && !defined(STANDALONE)
*oobp = REG_NAND_DATA8; *oobp = readb(&REG_NAND_DATA8);
eccCalc[eccPos++] = *oobp; eccCalc[eccPos++] = *oobp;
oobp++; oobp++;
#else #else
eccCalc[eccPos++] = REG_NAND_DATA8; eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
#endif #endif
numToRead--; numToRead--;
} }
...@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, ...@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
if (numToRead == 11) { if (numToRead == 11) {
/* read BI */ /* read BI */
#if defined(__KERNEL__) && !defined(STANDALONE) #if defined(__KERNEL__) && !defined(STANDALONE)
*oobp++ = REG_NAND_DATA8; *oobp++ = readb(&REG_NAND_DATA8);
#else #else
REG_NAND_DATA8; readb(&REG_NAND_DATA8);
#endif #endif
numToRead--; numToRead--;
} }
...@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, ...@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
nand_bcm_umi_bch_resume_read_ecc_calc(); nand_bcm_umi_bch_resume_read_ecc_calc();
while (numToRead) { while (numToRead) {
#if defined(__KERNEL__) && !defined(STANDALONE) #if defined(__KERNEL__) && !defined(STANDALONE)
*oobp = REG_NAND_DATA8; *oobp = readb(&REG_NAND_DATA8);
eccCalc[eccPos++] = *oobp; eccCalc[eccPos++] = *oobp;
oobp++; oobp++;
#else #else
eccCalc[eccPos++] = REG_NAND_DATA8; eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
#endif #endif
numToRead--; numToRead--;
} }
...@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, ...@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
if (pageSize == NAND_DATA_ACCESS_SIZE) { if (pageSize == NAND_DATA_ACCESS_SIZE) {
/* Now fill in the ECC bytes */ /* Now fill in the ECC bytes */
if (numEccBytes >= 13) if (numEccBytes >= 13)
eccVal = REG_UMI_BCH_WR_ECC_3; eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
/* Usually we skip CM in oob[0,1] */ /* Usually we skip CM in oob[0,1] */
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
...@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, ...@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC 12 */ eccVal & 0xff); /* ECC 12 */
if (numEccBytes >= 9) if (numEccBytes >= 9)
eccVal = REG_UMI_BCH_WR_ECC_2; eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
(eccVal >> 24) & 0xff); /* ECC11 */ (eccVal >> 24) & 0xff); /* ECC11 */
...@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, ...@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
/* Now fill in the ECC bytes */ /* Now fill in the ECC bytes */
if (numEccBytes >= 13) if (numEccBytes >= 13)
eccVal = REG_UMI_BCH_WR_ECC_3; eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
/* Usually skip CM in oob[1,2] */ /* Usually skip CM in oob[1,2] */
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
...@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, ...@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC12 */ eccVal & 0xff); /* ECC12 */
if (numEccBytes >= 9) if (numEccBytes >= 9)
eccVal = REG_UMI_BCH_WR_ECC_2; eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
(eccVal >> 24) & 0xff); /* ECC11 */ (eccVal >> 24) & 0xff); /* ECC11 */
...@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, ...@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC8 */ eccVal & 0xff); /* ECC8 */
if (numEccBytes >= 5) if (numEccBytes >= 5)
eccVal = REG_UMI_BCH_WR_ECC_1; eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
(eccVal >> 24) & 0xff); /* ECC7 */ (eccVal >> 24) & 0xff); /* ECC7 */
...@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, ...@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC4 */ eccVal & 0xff); /* ECC4 */
if (numEccBytes >= 1) if (numEccBytes >= 1)
eccVal = REG_UMI_BCH_WR_ECC_0; eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
(eccVal >> 24) & 0xff); /* ECC3 */ (eccVal >> 24) & 0xff); /* ECC3 */
......
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